CN102360326A

CN102360326A - Field-programmable gate array (FPGA) simulating method and device

Info

Publication number: CN102360326A
Application number: CN2011101365042A
Authority: CN
Inventors: 柴宁
Original assignee: Fujian Star Net Communication Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2011-05-24
Filing date: 2011-05-24
Publication date: 2012-02-22
Anticipated expiration: 2031-05-24
Also published as: CN102360326B

Abstract

The invention provides a field-programmable gate array (FPGA) simulating method and an FPGA simulating device. The method comprises the following steps that: an FPGA control module writes a starting identifier into an FPGA module to be tested so as to start the FPGA module to be tested; the FPGA module to be tested performs direct memory access (DMA) reading operation according to downlink BD ring information to acquire a data content of a downlink BD ring; the FPGA module to be tested performs DMA writing operation according to uplink BD ring information and writes the data content into an uplink BD ring; a BD management module outputs the data content which is written by the FPGA module to be tested to a data file; and when simulation time is over, a comparison output module compares the data content of the downlink BD ring with the data content in the data file and outputs a comparison result. Due to the adoption of the technical scheme, an FPGA of a DMA technology can be subjected to simulation test, so that a testing effect is improved, and testing cost is reduced.

Description

Field programmable gate array emulation mode and device

Technical field

The present invention relates to data communication field, relate in particular to a kind of field programmable gate array (Field-Programmable Gate Array; Abbreviate as: FPGA) emulation mode and device.

Background technology

FPGA is the very high novel high-performance programmable chip of a kind of integrated level, and its internal circuit function is programmable (Programmable), can pass through hardware description language (Hardware Description Language; Abbreviate as: HDL) with the special designs instrument, portion realizes and the complicated circuitry function flexibly within it, is applicable to high speed, highdensity high-end digital logic circuit design field.Direct memory access (Direct Memory Access; Abbreviate as: DMA) technology is meant a kind of high-speed data transmission operation; Allow direct read data between external apparatus and the storer; Whole data transfer operation carries out under a control that is called dma controller, in transmission course, does not need central processing unit (Central Processing Unit; Abbreviate as: intervention CPU), CPU can carry out other work, thereby has improved the operational efficiency of CPU greatly.

If realize the DMA technology, and it is applied in the Ethernet exchange, promptly allow ethernet medium access control (Media Access Control based on FPGA; Abbreviate as: MAC) Ether frame of layer directly is transferred to internal memory; And do not need the interference of CPU; Simultaneously, also allow the data in the internal memory directly are transferred to the ethernet mac layer, also do not need the intervention of CPU; Make full use of the advantage of DMA technology and FPGA technology, can improve the processing data packets ability of network processing unit greatly.

When realizing circuit function, need corresponding simulating, verifying technology usually and come the important component part of FPGA exploitation link is carried out simulating, verifying, to guarantee correctness based on the function logic of FPGA realization based on FPGA.

A kind of mode is the waveform that adopts after the emulation tool Direct observation emulation of main flow in the prior art; Judge whether design is correct; This method is applicable to the design that scale is minimum; Because its density and complexity are all higher, this method is inapplicable, can't guarantee the quality that designs for the FPGA that realizes the DMA technology.Another kind of mode is directly the FPGA code to be changed among the burned FPGA of programming file in the prior art, on the enterprising andante of the integrated circuit board of being built, verifies, this mode not only testing efficiency is low higher, and testing cost is also higher.

Summary of the invention

The present invention provides a kind of field programmable gate array emulation mode and device, in order to realize that the emulation testing of the FPGA that the DMA technology is reduced testing cost.

The present invention provides a kind of on-site programmable gate array FPGA emulation mode, is applicable to the FPGA simulator, and said FPGA simulator comprises: buffer description BD administration module, FPGA control module, memory module and comparison output module; Said method comprises:

Said FPGA control module is to FPGA module write-enable sign to be measured, to start said FPGA module to be measured;

Said FPGA module to be measured is obtained the corresponding data content of descending BD ring according to pre-configured descending BD ring information and executing direct memory access DMA read operation from said memory module;

Said FPGA module to be measured is according to pre-configured up BD ring information and executing DMA write operation, and said data content is write in the said memory module in the up BD ring corresponding memory space;

Said BD administration module will output to data file by the data content that said FPGA module to be measured is written in the said storage space;

When simulation time finished, data content that said relatively output module is corresponding with said descending BD ring and the data content in the said data file compared, and the output comparative result.

The present invention provides a kind of on-site programmable gate array FPGA simulator, comprising:

Memory module is used to store descending buffer description BD ring, up BD ring and the corresponding data content of said descending BD ring;

The FPGA control module; Be used for to FPGA module write-enable sign to be measured; To start said FPGA module to be measured; So that said FPGA module to be measured is according to pre-configured descending BD ring information and executing direct memory access DMA read operation; From said memory module, obtain the corresponding data content of descending BD ring, and make said FPGA module to be measured, said data content is written in the said memory module in the up BD ring corresponding memory space according to pre-configured up BD ring information and executing DMA write operation;

The BD administration module is used for the data content that is written to said storage space by said FPGA module to be measured is outputed in the data file;

Relatively output module is used for when simulation time finishes, and data content that said descending BD ring is corresponding and the data content in the said data file compare, and the output comparative result.

Field programmable gate array emulation mode of the present invention and device; The FPGA simulator is simulated CPU and memory headroom respectively through FPGA control module and memory module; And through starting FPGA module to be measured; Make FPGA module to be measured carry out the DMA read-write operation, the data content of up BD is write among the descending BD, the data content of the descending BD that writes by BD management module records FPGA module to be measured; After emulation finishes; The data content of up BD and the data content of descending BD are compared and export comparative result, judge through comparative result whether the function logic of FPGA module to be measured is correct, reached the purpose that the FPGA module that realizes the DMA technology is carried out emulation testing; Simultaneously, compared with prior art, technical scheme of the present invention need not the FPGA code is changed among the burned FPGA of programming file, has improved testing efficiency, has reduced testing cost.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply; Obviously, the accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 be the embodiment of the invention based on the structural representation of FPGA simulator;

The process flow diagram of the FPGA emulation mode that Fig. 2 provides for one embodiment of the invention;

The process flow diagram of the FPGA emulation mode that Fig. 3 provides for another embodiment of the present invention;

The process flow diagram of the FPGA emulation mode that Fig. 4 provides for further embodiment of this invention;

The structural representation of the FPGA simulator that Fig. 5 provides for one embodiment of the invention;

The structural representation of the FPGA simulator that Fig. 6 provides for another embodiment of the present invention.

Embodiment

For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer; To combine the accompanying drawing in the embodiment of the invention below; Technical scheme in the embodiment of the invention is carried out clear, intactly description; Obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.

Fig. 1 be the embodiment of the invention based on the structural representation of FPGA simulator.As shown in Figure 1, this FPGA simulator comprises: FPGA control module 11, buffer description (Buffer Descriptor; Abbreviate as: BD) administration module 12, memory module 13 and comparison output module 14.

Wherein, FPGA control module 11 is used to simulate the CPU of real network equipment, and main being responsible for carried out necessary configuration to FPGA module 10 to be measured, the quantity of available BD etc. during for example first address, mode of operation, the BD of configurating downlink BD ring and up BD ring encircle.Wherein, BD is a kind of data structure, constitutes circular linked list usually and uses, and in various embodiments of the present invention, the BD circular linked list is called the BD ring, and the BD ring is meant the circular linked list that is made up of a plurality of BD.In various embodiments of the present invention; The BD ring that will be used for supplying FPGA module 10 to be measured to use from memory module 13 reading of data is called descending BD ring; To be used for supplying FPGA module 10 to be measured to write the BD ring that data use and be called up BD ring to memory module 13, and the first address of descending BD ring and up BD ring be meant respectively descending BD ring and up BD encircle in the memory location of first BD in memory module 13.In addition, FPGA control module 11 also is used for to FPGA module 10 write-enable signs to be measured, and promptly the register to FPGA module 10 to be measured writes the startup sign, to start FPGA module 10 to be measured, makes FPGA module 10 to be measured carry out the DMA read-write operation.

Wherein, Memory module 13 is used for the internal memory of analog network equipment; Be used to store descending BD ring, up BD ring and the corresponding data content of descending BD ring, the corresponding data content of descending BD ring is meant the data content that FPGA module 10 to be measured will read from memory module 13.In addition, memory module 13 also is used to store the data content that is write up BD ring by FPGA module 10 to be measured, and FPGA module 10 promptly to be measured writes data content in the memory module 13 according to up BD ring automatically.

Wherein, BD administration module 12 is mainly through carrying out alternately with memory module 13; Descending BD ring in the managed storage module 13 and up BD ring; And the data content of being responsible for FPGA module 10 to be measured is written in the memory module 13 outputs in the data file, compares with the data content that FPGA module 10 to be measured writes for the data content that relatively output module 14 is corresponding with descending BD ring, and exports comparative result.In addition, BD administration module 12 also is used for being responsible for descending BD ring and up BD ring are upgraded, and is about to used BD and reclaims, and write new BD again.

Further, as shown in Figure 1, this FPGA simulator also comprises: interface modular converter 15 and storage control module 16.Interface modular converter 15; Be connected with FPGA module 10 to be measured with storage control module 16 respectively; Be used to be responsible between FPGA module 10 to be measured and FPGA simulator, carrying out the conversion of EBI form; For example: the EBI format conversion that FPGA module 10 to be measured is used becomes the inner interface format that uses of FPGA simulator, and the interface format that perhaps the FPGA simulator is used converts the EBI form that FPGA module 10 to be measured is used to.Said form mainly is meant interface sequence, and promptly interface modular converter 15 is specifically through resolving and change each other two kinds of interface sequences, to guarantee that FPGA module 10 to be measured can proper communication with the FPGA simulator.Storage control module 16 is connected between interface modular converter 15 and the memory module 13, is responsible for memory module 13 is carried out read-write operation.

The process flow diagram of the FPGA emulation mode that Fig. 2 provides for one embodiment of the invention.Present embodiment realizes that based on FPGA simulator shown in Figure 1 as shown in Figure 2, the method for present embodiment comprises:

Step 201, FPGA control module are to FPGA module write-enable sign to be measured, to start FPGA module to be measured.

Concrete, the FPGA control module is the write-enable sign in a register of FPGA module to be measured, to start FPGA module to be measured, makes the FPGA module carry out dma operation, promptly starts the emulation testing process to FPGA to be measured.FPGA module to be measured is the FPGA code that writes, and is used to realize the DMA function.

Step 202, FPGA module to be measured are obtained the corresponding data content of descending BD ring according to pre-configured descending BD ring information and executing DMA read operation from memory module.

Wherein, before emulation began, the FPGA control module had been carried out the configuration of relevant information to FPGA module to be measured in advance, comprised descending BD ring information.This descending BD ring information comprises: the first address of descending BD ring, and the start address of promptly descending BD ring in memory module, the length of descending BD ring, promptly what BD this descending BD ring comprises, number of available BD or the like in the descending BD ring.

When FPGA module to be measured need read the data content in the memory module, in memory module, read the corresponding data content of descending BD ring according to these descending BD ring information.Wherein, for ease of describing, " FPGA module to be measured reads the data content in the descending BD corresponding memory space " is referred to as " reading the data content of descending BD ".The data content that FPGA module to be measured reads descending BD ring can be to read the corresponding data content of each BD in the whole descending BD ring, also can be to read one of them or some corresponding data contents of BD.Because the operation that FPGA module to be measured is read descending BD belongs to prior art, does not do too much description at this.

Step 203, FPGA module to be measured be according to pre-configured up BD ring information and executing DMA write operation, and the data content that reads is written in the memory module in the up BD ring corresponding memory space.

Wherein, when the relevant information of the pre-configured FPGA module to be measured of FPGA control module, also comprise collocating uplink BD ring information.This up BD ring information comprises: the first address of up BD ring, and the start address of promptly up BD ring in memory module, the length of up BD ring, promptly what BD this up BD ring comprises, number of available BD or the like in the up BD ring.

When, arrive first according to these up BD ring information and to read up BD in the memory module, obtain the address information that will write data content, and then data content is write in the memory module in the pairing storage space of this address information.For ease of describing, " FPGA module to be measured writes data content in up BD corresponding memory space " is referred to as " writing data content to up BD ".

In the present embodiment; The data content that FPGA module to be measured writes among the up BD is the data content that FPGA module to be measured is read from descending BD; Promptly carry out the operation of writing BD, but present embodiment does not limit the mode of carrying out the operation of writing BD according to the operation of reading BD according to the operation of reading BD.For example: FPGA module to be measured can whenever read a data content from descending BD, and then carry out the operation that the data content of reading is write up BD.Again for example: FPGA module to be measured can also read a plurality of descending BD continuously, obtains after a plurality of data contents, carries out the operation that a plurality of data contents that will read write up BD successively again, and then carries out the operation of reading BD.Again for example: FPGA module to be measured is carried out the operation that all data contents that will read write up BD successively after also can the descending BD in the whole descending BD ring having been read again.Wherein, because the operation that FPGA module to be measured is write BD belongs to prior art, do not do too much description at this.

Step 204, BD administration module will output to data file by the data content that FPGA module to be measured is written in the storage space.

In the present embodiment, the BD administration module is responsible for up BD in the detection of stored space, is used to find whether there is the BD by FPGA module write-back to be measured.Wherein, the BD of write-back is meant the up BD that is write data content by FPGA module to be measured.

When FPGA module to be measured writes data content in up BD, can rewrite the zone bit of corresponding up BD, for example: the zone bit of up BD is rewritten as " 0 " by " 1 ", identifies this up BD by write-back.Based on this, the BD administration module is specifically found by the up BD of write-back through the zone bit that detects each up BD in the up BD ring.

When the BD administration module is found by the up BD of write-back; Data content in this up BD corresponding memory space (the follow-up data content that abbreviates as among the up BD) is outputed in the data file, so that record writes the data content among the up BD by FPGA module to be measured.In this explanation, in the present embodiment, FPGA module to be measured is that sequential read is taken off the data content among the capable BD, and the BD administration module to be order write data content output among the up BD with FPGA module to be measured.

Step 205, when simulation time finishes, relatively output module compares the corresponding data content of descending BD ring with the data content in the data file, and exports comparative result.

In the present embodiment, the tester pre-estimates emulation and finishes the required time, and sets simulation time in view of the above.Before simulation time finishes, FPGA module to be measured will continue to carry out the DMA read-write operation according to above-mentioned steps 202 and step 203, and write the data content among the up BD by the BD administration module according to step 204 output FPGA module to be measured.

When simulation time finishes, read the data content among the descending BD successively by the order that the comparison output module is read descending BD according to FPGA module to be measured, then data content among the descending BD and the data content in the data file are compared, and the output comparative result.Wherein, if all data contents are all consistent in the comparative result, explain to be under the test condition of test case with current BD data excitation file, the DMA of this FPGA module to be measured action is correct, i.e. dma logic design is correct; If occur inconsistent data content in the comparative result, explain that problem has appearred in the DMA action of FPGA module to be measured.When finding the design existing problems; The tester can further adopt other instruments or the method inspection place of ging wrong; For example can be, or further through places of pinpointing the problems such as wave form analyses through the daily record (log) of checking and analyze the BD administration module, and to DMA design is made amendment.

The FPGA emulation mode of present embodiment; The FPGA simulator is simulated CPU and memory headroom respectively through FPGA control module and memory module, and through starting FPGA module to be measured, makes FPGA module to be measured carry out the DMA read-write operation; The data content of descending BD is write among the up BD; The data content of the up BD that is write by BD management module records FPGA module to be measured after emulation finishes, compares and exports comparative result with the data content of up BD and the data content of descending BD; Whether the function logic of judging FPGA module to be measured through comparative result is correct, reached the purpose that the FPGA module that realizes the DMA technology is carried out emulation testing; Simultaneously; Compared with prior art, the emulation test method of present embodiment need not convert the FPGA code in the burned special FPGA module of programming file to and carry out, and can directly test the FPGA module that is realized by the FPGA code; Therefore, can reduce testing cost.

The process flow diagram of the FPGA emulation mode that Fig. 3 provides for another embodiment of the present invention.Present embodiment is based on realization embodiment illustrated in fig. 2, and is as shown in Figure 3, and the method for present embodiment comprises:

Step 301, FPGA control module are to FPGA module write-enable sign to be measured, to start FPGA module to be measured.

Step 302, BD administration module are according to update cycle and BD data excitation file, up BD ring in the updated stored module and/or descending BD ring.

Before emulation testing begins; The tester is in advance according to testing requirement; Configuration interface through the FPGA simulator has disposed many descending BD information and many up BD information, and these descending BD information and up BD information have constituted the BD data excitation file that emulation testing is used.Wherein, Every descending BD information comprises the information (for example next BD pointer, length field etc.) of this descending BD, the data content of this descending BD correspondence and the memory address information such as (i.e. first memory addresss) of storing this data content; Wherein, first memory address is represented the memory location of data content in memory module of descending BD.Every up BD information comprises the information (for example next BD pointer, length field etc.) of this up BD, the memory address information such as (i.e. second memory addresss) that this up BD is corresponding; Wherein, second memory address representes to write the memory location of data content in memory module among the up BD.

Wherein, The capacity of descending BD ring and up BD ring is normally limited; And in order to carry out emulation testing to FPGA module to be measured more accurately; The tester can dispose more descending BD information and up BD information usually, the capacity that these descending BD information and up BD information are generally encircled greater than descending BD ring and up BD.Carrying out along with the emulation testing process; BD in descending BD ring and the up BD ring can be consumed; For this reason, the BD administration module has been set the update cycle of upgrading descending BD ring and up BD ring, when the update cycle arrives; The BD administration module is inquired about descending BD ring and up BD ring respectively in memory module, to find whether to exist descending BD and the up BD that has been used.Wherein, whether the BD administration module is rewritten through the zone bit of judging each BD, judges whether BD is used.For example: if the zone bit of descending BD is rewritten as " 0 " by " 1 "; Show that this descending BD is used; Show that promptly FPGA module to be measured carried out the DMA read operation to this descending BD, and when read operation finishes, it has been carried out write-back (be about to zone bit and be rewritten as " 0 " by original value " 1 "); In like manner; If the zone bit of up BD is rewritten as " 0 " by " 1 "; Show that this up BD is used, show that promptly FPGA module to be measured carried out the DMA write operation to this up BD, and when write operation finishes, it has been carried out write-back (be about to zone bit and be rewritten as " 0 " by original value " 1 ").

When in inquiring descending BD ring, having the descending BD that crosses by FPGA module execution DMA read operation write-back to be measured; The BD administration module reads a descending BD information that was not used from BD data excitations file, and the descending BD that crosses with the descending BD information updating write-back that reads.This renewal process specifically is meant with the descending BD information that reads and covers original information, comprises with the data content in the descending BD information that reads covering original data content.In this explanation; For fear of the problem that the data content that originally should not cover occurs having covered with the data content in the descending BD information that reads; Requirement guarantees that first memory address of every descending BD correspondence is different, promptly not overlapped when configurating downlink BD information.

When in inquiring up BD ring, having the up BD that crosses by FPGA module execution DMA write operation write-back to be measured; The BD administration module reads a up BD information that was not used from BD data excitation file; And, promptly cover original information with the up BD information that reads with the up BD that the up BD information updating write-back that reads is crossed.

In this explanation, the BD administration module not only can be set the update cycle, can also set the BD quantity of each renewal, and promptly the BD administration module not only can once upgrade a descending BD and/or up BD, can also upgrade a plurality of descending BD and/or a plurality of up BD simultaneously.

Realize recycling of descending BD ring and up BD ring through aforesaid operations, and then made and to test the DMA function of FPGA module to be measured through more BD information, improved test accuracy and test effect.

Step 303, FPGA module to be measured are obtained the corresponding data content of descending BD ring according to pre-configured descending BD ring information and executing DMA read operation from memory module.

Step 304, FPGA module to be measured be according to pre-configured up BD ring information and executing DMA write operation, and the data content that reads is written in the memory module in the up BD ring corresponding memory space.

Step 305, BD administration module will output to data file by the data content that FPGA module to be measured is written in the storage space.

Step 306, when simulation time finishes, relatively output module compares the corresponding data content of descending BD ring with the data content in the data file, and exports comparative result.

Wherein, above-mentioned steps 303-step 306 can repeat no more at this referring to the description of above-mentioned steps 202-step 205.

In this explanation; The operation that the BD administration module encircles descending BD and/or up BD ring upgrades in the present embodiment is a step 302; Can separately carry out with the operation of step 303-step 306, it does not have sequencing, upgrades operation and is triggered and carried out by the update cycle.

The FPGA emulation mode of present embodiment; The BD administration module is through upgrading descending BD ring and/or up BD ring; Make descending BD ring and up BD ring to recycle; And then make and can test the DMA function of FPGA module to be measured through more BD information, improve test accuracy and test effect.

Further; The BD administration module can be equal to the situation that CPU in the network equipment handles descending BD or up BD to the renewal operation of descending BD ring and/or up BD ring; And can simulate the various processing sights of CPU, and then be implemented under the CPU different disposal sight performance test to FPGA module to be measured through the different update cycles is set.For example: shorter through the update cycle is set, it is comparatively frequent promptly to upgrade operation, can simulate CPU and handle each BD situation more timely, and then test FPGA module to be measured various performances in this case, and for example whether logic is correct, and whether response is timely etc.Again for example: longer through the update cycle is set, promptly after the long period, carry out and once upgrade operation, can simulate the situation that CPU has little time to handle each BD, and then test FPGA module to be measured various performances in this case.

The process flow diagram of the FPGA emulation mode that Fig. 4 provides for further embodiment of this invention.As shown in Figure 4, present embodiment can realize that as shown in Figure 4, the method for present embodiment comprises based on the foregoing description:

Step 401, tester are according to testing requirement, through the configuration interface configuration FPGA configuration excitation file of FPGA simulator.

This FPGA configuration excitation file comprises descending BD ring information and up BD ring information, is used to supply the FPGA control module before emulation testing begins, FPGA module to be measured to be carried out the configuration of necessary information.

Step 402, tester are according to testing requirement, through the configuration interface configuration BD data excitation file of FPGA simulator.

This BD data excitation file comprises many descending BD information and many up BD information, and required BD information when being used to emulation DMA function is provided is for the emulation testing process lays the first stone.

Wherein, the tester disposes FPGA configuration excitation file and does not do qualification with the sequencing of configuration BD data excitation file.Wherein, descending BD ring information and up BD ring information are used for making FPGA module to be measured to find descending BD and up BD in memory module.

Step 403, FPGA control module write descending BD ring information and up BD ring information to FPGA module to be measured, so that FPGA module to be measured is configured according to FPGA configuration excitation file.

Wherein, descending BD ring information comprises: the size (promptly comprising what descending BD) of the first address of descending BD ring, descending BD ring; Up BD ring information comprises: the information such as size of the first address of up BD ring, up BD ring.

Concrete, the FPGA control module writes the information such as first address of the first address of descending BD ring, up BD ring respectively in the different registers of FPGA module to be measured, to realize FPGA modules configured to be measured.In addition; In this layoutprocedure; The FPGA control module can also dispose the mode of operation of FPGA module to be measured, for example: can dispose FPGA to be measured and be operated in the repeating query pattern, under this mode of operation; FPGA module to be measured can be carried out dma operation according to the first address of descending BD ring and the first address of up BD ring automatically, and the FPGA control module only need once dispose FPGA module to be measured and get final product.Not only for example: can also dispose FPGA to be measured and be operated in initiatively and inform (but also can be described as write tail) pattern; Under this mode of operation; Once descending BD ring of the every renewal of BD administration module and/or up BD ring just need reconfigure once FPGA module to be measured through the FPGA control module, need carry out adaptive renewal to FPGA modules configured information to be measured in other words.

In the present embodiment, FPGA module to be measured is operated in and is example under the repeating query pattern.

Step 404, FPGA control module are to FPGA module write-enable sign to be measured, to start FPGA module to be measured.

Step 405, BD administration module are according to update cycle and BD data excitation file, up BD ring in the updated stored module and/or descending BD ring.

After above-mentioned preliminary work finished, the FPGA control module started FPGA module to be measured, the beginning emulation testing.Wherein, step 404 and step 405 can be referring to the descriptions of step 301 and step 302.

Step 406, FPGA module to be measured are obtained the corresponding data content of descending BD ring according to pre-configured descending BD ring information and executing DMA read operation from memory module.

In actual application, FPGA module to be measured is often different with the EBI that the network equipment is adopted, and therefore, need carry out format conversion to two kinds of EBIs.Wherein, said format conversion mainly is meant the sequential of two kinds of EBIs is changed.

Based on this, in the emulation testing process of present embodiment, be responsible for two kinds of EBIs are carried out format conversion by the interface modular converter of FPGA simulator, FPGA module more to be measured is tested.Wherein, this interface modular converter look the difference of the EBI that FPGA module to be measured adopted can be by different implementations.

The concrete implementation of this step 406 comprises following substep: step 4601, FPGA module to be measured are when needs read the data content in the memory module, and according to the BD eye address in the descending BD ring information, transmission is read first of descending BD and read the BD instruction.Step 4602, interface modular converter are read the BD instruction with first and are carried out format conversion; Promptly reading the corresponding interface sequence of BD instruction to first resolves; And after converting the inner interface sequence that uses of FPGA simulator into, send to the storage control module of FPGA simulator.Step 4603, storage control module first after according to format conversion read the BD instruction, from memory module, obtains first memory address among the descending BD, and sends to interface modular converter.Step 4064, interface modular converter carry out format conversion with first memory address, and the interface sequence when being about to send first memory address sends to FPGA module to be measured after converting the interface sequence that FPGA module to be measured can discern into.Step 4605, FPGA module to be measured are sent the read data instruction of reading of data according to first memory address.After step 4606, interface modular converter carried out format conversion with the read data instruction, the corresponding interface sequence of read data instruction soon sent to storage control module after resolving and convert into the inner interface sequence that uses of FPGA simulator.The read data instruction after according to format conversion of step 4607, storage control module is obtained the corresponding data content of descending BD, and is sent to interface modular converter from the storage space of the corresponding memory module of first memory address.After step 4608, the interface modular converter data content that descending BD is corresponding carried out format conversion, the interface sequence when being about to the FPGA simulator and sending data content sent to FPGA module to be measured after converting the interface sequence that FPGA module to be measured can discern into.

Step 407, FPGA module to be measured be according to pre-configured up BD ring information and executing DMA write operation, and the data content that reads is written in the memory module in the up BD ring corresponding memory space.

Based on above-mentioned, the embodiment of step 407 comprises following substep: step 4071, FPGA module to be measured when memory module writes data content, according to the BD eye address in the up BD ring information, are sent the second reading BD instruction of reading up BD at needs.Step 4072, interface modular converter are promptly resolved the corresponding interface sequence of second reading BD instruction after format conversion is carried out in second reading BD instruction, and after converting the inner interface sequence that uses of FPGA simulator into, send to storage control module.The second reading BD instruction after according to format conversion of step 4073, storage control module is read second memory address among the up BD, and is sent to interface modular converter.After step 4074, interface modular converter carried out format conversion with second memory address, the interface sequence when being about to send second memory address sent to FPGA module to be measured after converting the interface sequence that FPGA module to be measured can discern into.Step 4075, FPGA module to be measured are sent the write data instruction that writes data, and this write data instruction comprises second memory address and data content.After step 4076, interface modular converter carried out format conversion with the write data instruction, the corresponding interface sequence of write data instruction soon sent to storage control module after resolving and convert into the inner interface sequence that uses of FPGA simulator.The write data instruction after according to format conversion of step 4077, storage control module is stored data content in the storage space of the corresponding memory module of second memory address.

Step 408, BD administration module will output to data file by the data content that FPGA module to be measured is written in the storage space.

Step 409, when simulation time finishes, relatively output module compares the corresponding data content of descending BD ring with the data content in the data file, and exports comparative result.

Above-mentioned steps 408 can be referring to the description of step 204 and step 205 with step 409.

The FPGA emulation mode of present embodiment, pre-configured various excitation files are that emulation testing provides condition; Through interface modular converter two kinds of EBIs are carried out format conversion and guaranteed that emulation testing can carry out under the EBI condition of different, further comprehensive performance test FPGA module to be measured.

In the above-described embodiments; When configuration FPGA module to be measured is operated in when writing the tail pattern; The BD administration module needs according to the renewal result to descending BD ring and/or up BD ring, upgrades descending BD ring information and/or up BD ring information in the FPGA module to be measured through the FPGA control module.In other words, when descending BD ring when wherein any one has renewal with up BD ring, just needs be configured FPGA module to be measured again.This process that reconfigures is: the BD administration module will upgrade the result and inform the FPGA control module, again vicissitudinous information write in the corresponding registers of FPGA module to be measured by the FPGA control module.At this moment, FPGA module to be measured can be carried out dma operation according to the configuration information after upgrading.

From the above, in the emulation testing process, except having the request of DMA reading and writing data, also can exist the FPGA control module to dispose the operation of FPGA module to be measured on two kinds of EBIs.Therefore, the interface modular converter of present embodiment also is used for being responsible for the execution sequence of the various operations of arbitration except the format conversion of carrying out two kinds of EBIs.For example: interface modular converter is responsible for arbitrating the configuration operation of request of DMA reading and writing data and FPGA control module.A kind of simple arbitration embodiment is: adopt the mode of distributing queue number to handle the competition between the different requests, be about to various requests and squeeze into FIFO (First Input First Output according to the principle of FIFO; Abbreviate as: FIFO) in the command queue, when repeating query to is asked, take out this request and carry out subsequent treatment; Request for repeating query is not arrived continues to wait in line.

Through above-mentioned embodiment, can do further test to FPGA module to be measured writing under the tail pattern, FPGA module more to be measured is tested, both can improve the test effect, have lower testing cost again.

Further, the configuration interface that in above-mentioned each embodiment, relates to is each tester's of being provided by the FPGA simulator a interactive interface.This configuration interface can be developed based on excel; The formula and the VBA (Visual Basic for Applications) that utilize excel to provide construct each test suite; Also can the various excitation files of tester's configuration be changed into text (txt) file simultaneously; Make need not compile to generate test case, improved testing efficiency, reduced testing cost.

On this configuration interface, allow the tester that the data content among the descending BD is carried out format configuration.For example: can be configured to fixed mode (fix), certainly increase pattern (inc), from size reduction mode (dec) or random pattern (ram) etc.

In addition, this configuration interface can also be used to show comparative result or location mistake.For example: through calling data content and the data content in the data file among the descending BD; Show two kinds of data contents through this configuration interface; And through code relatively two kinds of data contents are compared, show comparative result simultaneously, can show comparative result more intuitively through this mode; Be convenient to tester's understanding and location errors present, carry out time update.

Further, because the excitation file in the embodiment of the invention is invoked with textual form, need not compile, practice thrift compilation time, the configuration of excitation file is simpler, therefore, can also test FPGA module to be measured through hyperchannel.

In sum, the FPGA emulation mode of the embodiment of the invention has following beneficial effect: 1, utilize the excel instrument, visual configuration interface is provided, be convenient to configuration excitation file, can show comparative result simultaneously, more easily the analyzing and positioning problem.2, compared with prior art, no longer carry out simulating, verifying on the plate, belong to logical simulation, can pinpoint the problems fast, testing efficiency is higher, testing cost is low.3, can more comprehensively test FPGA module to be measured.

The structural representation of the FPGA simulator that Fig. 5 provides for one embodiment of the invention.As shown in Figure 5, the device of present embodiment comprises: memory module 51, FPGA control module 52, BD administration module 53 and comparison output module 54.

Wherein, memory module 51 is used to store descending BD ring, up BD ring and the corresponding data content of descending BD ring.FPGA control module 52; Be connected with FPGA module 10 to be measured; Be used for to FPGA module 10 write-enable signs to be measured; To start FPGA module 10 to be measured, so that FPGA module 10 to be measured is obtained the corresponding data content of descending BD ring according to pre-configured descending BD ring information and executing DMA read operation from memory module 51; And make FPGA module 10 to be measured according to pre-configured up BD ring information and executing DMA write operation, data content is written in the memory module 51 in the up BD ring corresponding memory space.BD administration module 53 is connected with memory module 51, is used for the data content that is written to storage space by FPGA module 10 to be measured is outputed in the data file.Relatively output module 54 is connected with memory module 51 with BD administration module 53, is used for when simulation time finishes, and data content that descending BD ring is corresponding and the data content in the data file compare, and the output comparative result.

The FPGA simulator of present embodiment can be used for carrying out the flow process of FPGA emulation mode shown in Figure 2, and its concrete principle of work repeats no more, and sees the description of method embodiment for details.

The FPGA simulator of present embodiment is simulated CPU, internal memory respectively through FPGA control module and memory module, and through starting FPGA module to be measured; Make FPGA module to be measured carry out dma operation, read the data content of descending BD and the data content that reads is write among the up BD, by output module relatively two kinds of data contents are compared the output comparative result again; Thereby realize emulation testing to the FPGA module; Simultaneously, compared with prior art, the FPGA simulator of present embodiment can directly carry out emulation testing to the FPGA code; Belong to logical simulation; Need not the programming of FPGA code is tested to the enterprising andante of FPGA integrated circuit board, both improved testing efficiency, reduced testing cost again.

The structural representation of the FPGA simulator that Fig. 6 provides for another embodiment of the present invention.Present embodiment is based on realization embodiment illustrated in fig. 5, and is as shown in Figure 6, and the device of present embodiment also comprises: interface modular converter 61 and storage control module 62.

Wherein, Interface modular converter 61; Be connected with FPGA module 10 to be measured; Be used for first reading the BD instruction and instructing with read data and carry out format conversion what FPGA module to be measured 10 was sent, and send to storage control module 62, first memory address and the data content that also are used for storage control module 62 is read carry out sending to FPGA module 10 to be measured after the format conversion.Wherein, first to read BD instruction be according to the BD eye address in the descending BD ring information, the instruction of reading descending BD of transmission by FPGA module 10 to be measured; Read data instruction be by FPGA module 10 to be measured according to first memory address, the instruction of the read data of transmission.

Storage control module 62; Be connected with memory module 51 with interface modular converter 61, be used for reading the BD instruction, from memory module 51, obtain first memory address among the descending BD according to first after the format conversion; And send to interface modular converter 61; Also be used for from the storage space of the corresponding memory module 51 of first memory address, obtaining the corresponding data content of descending BD, and sending to interface modular converter 61 according to the instruction of the read data after the format conversion.

The above-mentioned functions module can be used for carrying out the operation of step 4061-step 4068 among the said method embodiment, and its concrete principle of work repeats no more.

Further; When FPGA module 10 to be measured is carried out the DMA write operation; Format conversion is carried out in second reading BD instruction and write data instruction that interface modular converter 61 also is used for FPGA module 10 to be measured is sent; And send to storage control module 62, and second memory address that storage control module 62 reads is carried out sending to FPGA module 10 to be measured after the format conversion.Wherein, second reading BD instruction is according to the BD eye address in the up BD ring information, the instruction of reading up BD of transmission by FPGA module 10 to be measured; Write data instruction be by FPGA module 10 to be measured according to second memory address, the instruction of the write data of transmission.

Storage control module 62 also is used for instructing according to the second reading BD after the format conversion; Read second memory address among the up BD; And send to interface modular converter 61; And be used for data content being stored in the storage space of the corresponding memory module 51 of second memory address according to the instruction of the write data after the format conversion.

Further, the FPGA simulator of present embodiment also comprises: configuration interface 63.This configuration interface 63 can be realized based on excel, is used to supply the tester before starting emulation, according to testing requirement many descending BD information of configuration and many up BD information, generates BD data excitation file; Wherein, every descending BD information comprises the start address of descending BD ring, the data content of each descending BD correspondence and first memory address of storage data content; Every start address second memory address corresponding that up BD information comprises up BD ring with each up BD.

Based on above-mentioned, BD administration module 53 also is connected with configuration interface 63, is used for according to update cycle and BD data excitation file, up BD ring in the updated stored module 51 and/or descending BD ring.Concrete; When the update cycle arrives; BD administration module 53 is inquired about descending BD ring and up BD ring respectively, and in descending BD ring, exists when carrying out the descending BD that DMA read operation write-backs cross by FPGA module 10 to be measured, encourages the file from the BD data and reads a descending BD information; And the descending BD that crosses with the BD information updating write-back that reads; And in up BD ring, exist when carrying out the up BD that DMA write operation write-backs cross by FPGA module 10 to be measured, from BD data excitation file, read a up BD information, and the up BD that crosses with the up BD information updating write-back that reads.

In addition, this configuration interface 63 also is used to supply the tester according to testing requirement, configuration FPGA configuration excitation file; Wherein, this FPGA configuration excitation file comprises descending BD ring information and up BD ring information.

Based on above-mentioned, FPGA control module 52 also is connected with configuration interface 63, is used for writing descending BD ring information and up BD ring information to FPGA module 10 to be measured, so that FPGA module to be measured is configured according to FPGA configuration excitation file.

Wherein, FPGA control module 52 can also dispose the mode of operation of FPGA module 10 to be measured, for example: repeating query pattern or write the tail pattern.When being operated in, FPGA module 10 to be measured writes tail pattern following time; BD administration module 53 also is connected with FPGA control module 52; Be used for according to renewal result, upgrade descending BD ring information and/or up BD ring information in the FPGA module 10 to be measured through FPGA control module 52 to descending BD ring and/or up BD ring.

Above-mentioned each functional module can be used for the corresponding flow process in execution graph 2 or Fig. 3 or the FPGA emulation mode shown in Figure 4, and its principle of work repeats no more, and sees the description of method embodiment for details.

The FPGA simulator of present embodiment; Simulate CPU, internal memory respectively through FPGA control module and memory module, and, make FPGA module to be measured carry out dma operation through starting FPGA module to be measured; Read the data content of descending BD and the data content that reads is write among the up BD; By comparing output module two kinds of data contents are compared the output comparative result again, thereby realize emulation testing, not only improved testing efficiency but also reduced testing cost the FPGA module.Further, the FPGA simulator of present embodiment is convenient to the configuration that the tester carries out test case through configuration interface, has improved testing efficiency, has further reduced testing cost.And the FPGA simulator of present embodiment also allows to have realized the comprehensive coverage test to FPGA module to be measured under various sights, FPGA module to be measured being tested, and has improved the test effect, has reduced testing cost.

One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be accomplished through the relevant hardware of programmed instruction; Aforesaid program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.

What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.

Claims

1. an on-site programmable gate array FPGA emulation mode is characterized in that, is applicable to the FPGA simulator, and said FPGA simulator comprises: buffer description BD administration module, FPGA control module, memory module and comparison output module; Said method comprises:

2. FPGA emulation mode according to claim 1 is characterized in that, said FPGA control module, comprises to start said FPGA module to be measured to FPGA module write-enable sign to be measured afterwards:

Said BD administration module upgrades up BD ring and/or descending BD ring in the said memory module according to update cycle and BD data excitation file.

3. FPGA emulation mode according to claim 2 is characterized in that, said BD administration module is according to update cycle and BD data excitation file, and the up BD ring or the descending BD ring that upgrade in the said memory module comprise:

When the said update cycle arrived, said BD administration module was inquired about said descending BD ring and said up BD ring respectively;

When existing in the said descending BD ring when carrying out the descending BD that DMA read operation write-back crosses by said FPGA module to be measured, from said BD data excitation file, read a descending BD information, and the descending BD that crosses with the said write-back of descending BD information updating that reads;

When existing in the said up BD ring when carrying out the up BD that DMA write operation write-back crosses by said FPGA module to be measured, from said BD data excitation file, read a up BD information, and the up BD that crosses with the said write-back of up BD information updating that reads.

4. FPGA emulation mode according to claim 3 is characterized in that, said FPGA control module, comprises to start said FPGA module to be measured to FPGA module write-enable sign to be measured before:

The tester through configuration interface many said descending BD information of configuration and many said up BD information, generates said BD data excitation file according to testing requirement.

5. according to claim 2 or 3 or 4 described FPGA emulation modes, it is characterized in that said FPGA control module, comprises to start said FPGA module to be measured to FPGA module write-enable sign to be measured before:

Said FPGA control module writes said descending BD ring information and said up BD ring information to said FPGA module to be measured, so that said FPGA module to be measured is configured according to FPGA configuration excitation file.

6. FPGA emulation mode according to claim 5; It is characterized in that; Said FPGA control module writes said descending BD ring information and said up BD ring information according to FPGA configuration excitation file to said FPGA module to be measured, so that said FPGA module to be measured is configured, comprises before:

The tester disposes said FPGA configuration excitation file according to testing requirement through configuration interface, and said FPGA configuration excitation file comprises said descending BD ring information and said up BD ring information.

7. FPGA emulation mode according to claim 5 is characterized in that, said BD administration module upgrades up BD ring and/or descending BD ring in the said memory module according to update cycle and BD data excitation file, comprises afterwards:

Said BD administration module upgrades descending BD ring information and/or said up BD ring information in the said FPGA module to be measured according to upgrading the result through said FPGA control module.

8. according to claim 1 or 2 or 3 or 4 or 6 or 7 described FPGA emulation modes; It is characterized in that; Said FPGA module to be measured is obtained the corresponding data content of descending BD ring and is comprised according to pre-configured descending BD ring information and executing DMA read operation from said memory module:

Said FPGA module to be measured is according to the BD eye address in the said descending BD ring information, and transmission is read first of descending BD and read the BD instruction;

The interface modular converter of said FPGA simulator is read after BD instruction carries out format conversion said first, sends to the storage control module of said FPGA simulator;

Said storage control module first after according to format conversion read the BD instruction, from said memory module, obtains first memory address among the said descending BD, and sends to said interface modular converter;

Said interface modular converter sends to said FPGA module to be measured after said first memory address is carried out format conversion;

Said FPGA module to be measured is sent the read data instruction of reading of data according to said first memory address;

Said interface modular converter sends to said storage control module after format conversion is carried out in said read data instruction;

The read data instruction of said storage control module after according to format conversion obtained the corresponding data content of said descending BD, and sent to said interface modular converter from the storage space of the corresponding said memory module of said first memory address;

Said interface modular converter sends to said FPGA module to be measured after the corresponding data content of said descending BD is carried out format conversion.

9. FPGA emulation mode according to claim 8; It is characterized in that; Said FPGA module to be measured is encircled information and executing DMA write operation according to pre-configured up BD, said data content is write in the said memory module comprise in the up BD corresponding memory space:

Said FPGA module to be measured is sent the second reading BD instruction of reading up BD according to the BD eye address in the said up BD ring information;

Said interface modular converter sends to said storage control module after format conversion is carried out in said second reading BD instruction;

The second reading BD instruction of said storage control module after according to format conversion read second memory address among the said up BD, and sent to said interface modular converter;

Said interface modular converter sends to said FPGA module to be measured after said second memory address is carried out format conversion;

Said FPGA module to be measured is sent the write data instruction that writes data, and the write data instruction comprises said second memory address and said data content;

Said interface modular converter sends to said storage control module after format conversion is carried out in the write data instruction;

The write data instruction of said storage control module after according to format conversion stored said data content in the storage space of the corresponding said memory module of said second memory address.

10. an on-site programmable gate array FPGA simulator is characterized in that, comprising:

11. FPGA simulator according to claim 10 is characterized in that, said BD administration module also is used for upgrading up BD ring and/or descending BD ring in the said memory module according to update cycle and BD data excitation file.

12. FPGA simulator according to claim 11; It is characterized in that; Said BD administration module specifically is used for when the said update cycle arrives; Inquire about said descending BD ring and said up BD ring respectively, and in said descending BD ring, exist when carrying out the descending BD that DMA read operation write-back crosses, encourage the file from said BD data and read a descending BD information by said FPGA module to be measured; And the descending BD that crosses with the said write-back of BD information updating that reads; And in said up BD ring, exist when carrying out the up BD that DMA write operation write-back crosses by said FPGA module to be measured, from said BD data excitation file, read a up BD information, and the up BD that crosses with the said write-back of up BD information updating that reads.

13. FPGA simulator according to claim 12 is characterized in that, also comprises:

Configuration interface is used to supply the tester before starting emulation, according to testing requirement many said descending BD information of configuration and many said up BD information, generates said BD data excitation file.

14. FPGA simulator according to claim 13; It is characterized in that; Said FPGA control module also is used for according to FPGA configuration excitation file, writes said descending BD ring information and said up BD ring information to said FPGA module to be measured, so that said FPGA module to be measured is configured.

15. FPGA simulator according to claim 14; It is characterized in that; Said configuration interface also is used to supply the tester according to testing requirement, disposes said FPGA configuration excitation file, and said FPGA configuration excitation file comprises said descending BD ring information and said up BD ring information.

16. FPGA simulator according to claim 15; It is characterized in that; Said BD administration module also is used for according to the renewal result to said descending BD ring and/or said up BD ring, upgrades said descending BD ring information and/or said up BD ring information in the said FPGA module to be measured through said FPGA control module.

17. according to each described FPGA simulator of claim 10-16, it is characterized in that, also comprise: interface modular converter and storage control module;

Said interface modular converter; Be used for first reading the BD instruction and instructing with read data and carry out format conversion with what said FPGA module to be measured was sent; And send to said storage control module, and first memory address and the data content that are used for said storage control module is read carry out sending to said FPGA module to be measured after the format conversion; Said first to read BD instruction be according to the BD eye address in the descending BD ring information, the instruction of reading descending BD of transmission by said FPGA module to be measured; Said read data instruction is according to said first memory address, the instruction of the read data of transmission by said FPGA module to be measured;

Said storage control module; Be used for reading the BD instruction according to first after the format conversion; From said memory module, obtain first memory address among the said descending BD, and send to said interface modular converter, and be used for instructing according to the read data after the format conversion; From the storage space of the corresponding said memory module of said first memory address, obtain the corresponding data content of said descending BD, and send to said interface modular converter.

18. FPGA simulator according to claim 17; It is characterized in that; Format conversion is carried out in second reading BD instruction and write data instruction that said interface modular converter also is used for said FPGA module to be measured is sent; And send to said storage control module, and be used for second memory address that said storage control module reads is carried out sending to said FPGA module to be measured after the format conversion; Said second reading BD instruction is according to the BD eye address in the said up BD ring information, the instruction of reading up BD of transmission by said FPGA module to be measured; The write data instruction is according to said second memory address, the instruction of the write data of transmission by said FPGA module to be measured;

Said storage control module also is used for instructing according to the second reading BD after the format conversion; Read second memory address among the said up BD; And send to said interface modular converter; And be used for said data content being stored in the storage space of the corresponding said memory module of said second memory address according to the instruction of the write data after the format conversion.