CN102354678A - Silicon-on-insulator (SOI) structures with step-type buried oxide layers - Google Patents
Silicon-on-insulator (SOI) structures with step-type buried oxide layers Download PDFInfo
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Abstract
The invention provides two types of silicon-on-insulator (SOI) structures with step-type buried oxide layers. The first type of SOI structure comprises a P-type semiconductor substrate, a gate insulation layer formed above a P-type channel, a grid electrode formed above the gate insulation layer and a side wall which covers the grid electrode and the side edge of the gate insulation layer, wherein an N-type source region, an N-type drain region, the step-type buried oxide layers positioned in the N-type source region and the N-type drain region and below the P-type channel are formed on the semiconductor substrate; the thicknesses of the buried oxide layers positioned in the N-type source region and the N-type drain region are respectively greater than that of the buried oxide layer positioned below the P-type channel; and a P-type element heavily doped region is arranged in the P-type semiconductor substrate below the corresponding thinner buried oxide layer below the side wall adjacent to one side of the N-type drain region. Different from the first type of SOI structure, the second type of SOI structure is characterized in that the top of the substrate is provided with the N-type doped region, and the source region and the drain region are P-type. By utilizing the technical scheme of the invention, the short channel effect of the existing SOI structures can be solved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to soi structure with notch cuttype buried oxide.
Background technology
In SOI (silicon-on-insulator) material; Because of existing insulating buried layer (to be generally the silicon dioxide buried regions between top silicon fiml and the substrate silicon; Be called for short buried oxide); Make the SOI technology have many advantages that surmounts the conventional bulk silicon technology; For example: compare with the CMOS of conventional bulk silicon; Use the CMOS of SOI made to have the speed height, the little characteristics of living electric capacity are omitted in low in energy consumption, source, have avoided the latch-up among the body silicon CMOS simultaneously.
Shown in Figure 1 is the soi structure with buried oxide of the prior art; This structure comprises: Semiconductor substrate 10, be formed on gate insulator 14 and grid 15 on the substrate 10; The side of this gate insulator 14 and grid 15 is formed with insulative sidewall 16, the source region 12 that is formed with corresponding grid 15 in the substrate with drain region 13, have the buried oxide 11 of two thickness; Wherein, thicker buried oxide 11 is positioned at the below in source region 12 and drain region 13, and thin buried oxide 11 is below the raceway groove between source region 12 and the drain region 13.Because buried oxide 11 has two thickness, generally be to bury through two-step oxidation that (Double Step Buried Oxide DSBO) forms, and therefore, the buried oxide with two thickness 11 shown in Figure 1 is called for short DSBO SOI.In addition; The below that is positioned at source region 12 and drain region 13 is thicker buried oxide 11; Below the raceway groove between source region 12 and the drain region 13 is thin buried oxide 11; Whole buried oxide 11 is just as notch cuttype; Therefore, DSBO SOI shown in Figure 1 also weighing-appliance the soi structure of notch cuttype buried oxide is arranged.With length is 0.15um; Thicker buried oxide 11 thickness are 100nm; Thin buried oxide 11 thickness are that 20nm is an example, and the soi structure with single thickness 100nm buried oxide and the lattice temperature comparison diagram of the soi structure with notch cuttype buried oxide are as shown in Figure 2; Wherein, Peak temperature is that the curve of 425K is the soi structure lattice temperature corresponding at SOI device different length place with single thickness 100nm buried oxide; Peak temperature is that the curve of 315K is the soi structure lattice temperature corresponding at SOI device different length place with notch cuttype buried oxide; Can find out; Thin buried oxide 11 can play thermolysis, thereby has better suppressed in the traditional SOI structure because the problem that self-heating effect causes carrier mobility to be degenerated.
Yet this soi structure with notch cuttype buried oxide is along with compact in size, and particularly, channel length shortens, and serious short-channel effect can occur.Short-channel effect shows as particularly: (1) threshold voltage constantly diminishes along with channel length shortens; (2), make that the depletion layer in drain region and source region is very close, when source region and drain region apply bias voltage along with channel length shortens; Electric field line in the raceway groove can traverse to the source region from the drain region; And cause source region end barrier height to reduce, and when the result causes soi structure to be in OFF state, i.e. V
GSWhen not reaching cut-in voltage, leakage current increases, and this is unfavorable for the performance of soi structure device.
In view of this, be necessary in fact to propose a kind of new soi structure, solve the short-channel effect that existing soi structure occurs with notch cuttype buried oxide.
Summary of the invention
The problem that the present invention solves is to propose a kind of new soi structure with notch cuttype buried oxide, solves the short-channel effect that existing soi structure occurs.
For addressing the above problem, the present invention provides two kinds of soi structures with notch cuttype buried oxide, and first kind of soi structure comprises:
The P type semiconductor substrate is formed with the notch cuttype oxide layer of N type source region, N type drain region and N type source region, N type drain region and P type raceway groove below on the said Semiconductor substrate; Wherein, the oxidated layer thickness that is positioned at N type source region and N type drain region is respectively greater than the thickness of oxide layer that is positioned at P type raceway groove below;
Be formed at the gate insulator of P type raceway groove top;
Be positioned at the grid on the gate insulator;
The sidewall of cover gate and gate insulator side;
Wherein, near being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of N type drain region one side than the below of thin oxide layer.
Alternatively, near being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of N type source region one side than the below of thin oxide layer.
Alternatively, P type element is identical in the P type element in the P type element heavily doped region and other regional P type semiconductor substrate.
Alternatively, the P type element in the P type element heavily doped region is a boron element.
Alternatively, the P type concentration of element in the P type element heavily doped region is 1000 times to 10000 times of concentration that are positioned at other regional P type element.
Provided by the invention another have the soi structure of notch cuttype buried oxide, comprising:
P type semiconductor substrate, the top layer of said Semiconductor substrate are N type doped region, and said N type doped region is formed with P type source region, P type drain region and N type raceway groove, and the N type doped region below in the said Semiconductor substrate is formed with the notch cuttype oxide layer; Wherein, the corresponding oxidated layer thickness in P type source region and P type drain region below respectively greater than with N type raceway groove below corresponding thickness of oxide layer;
Be formed at the gate insulator of N type raceway groove top;
Be positioned at the grid on the gate insulator;
The sidewall of cover gate and gate insulator side;
Wherein, near being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of P type drain region one side than the below of thin oxide layer.
Alternatively, near also being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of P type drain region one side than the below of thin oxide layer.
Alternatively, P type element is identical in the P type element in the P type element heavily doped region and P type source region, the P type drain region.
Alternatively, the P type element in the P type element heavily doped region is a boron element.
Alternatively, the P type concentration of element scope in the P type element heavily doped region is 10
18-10
19Every cubic centimetre in individual atom.
Compared with prior art; The present invention has the following advantages: be employed on the existing DSBOSOI basis near being provided with P type element heavily doped region in the corresponding P-type semiconductor substrate than the below of thin oxide layer in the side wall below of N type drain region one side; Utilized P type element heavily doped region electromotive force minimum; The electric field line that to draw from the drain region terminates in P type element heavily doped region; Thereby avoid the electric field line that draw in the drain region in the existing DSBOSOI structure partly to terminate in the source region; And the source region end barrier height that causes thus reduces; And then the electron amount that causes the source region to be injected into raceway groove increases problem; Thereby the threshold voltage that effectively suppresses the DSBOSOI device reduces; And when making soi structure in off position; Leakage current reduces, and has improved the performance of soi structure device;
Further; Near also being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of N type source region one side than the below of thin oxide layer; Make not to be terminated corresponding P type element heavily doped region below the side wall that electric field line at P type element heavily doped region corresponding below the side wall of drain region one side terminates in source region one side, further reduce leakage current;
Provided by the invention another be employed in the improvement structure on the existing DSBOSOI basis; Correspondingly below near the side wall of P type drain region one side be provided with P type element heavily doped region in than the P-type semiconductor substrate below the thin oxide layer; Utilized P type element heavily doped region electromotive force minimum equally; The electric field line that to draw from the drain region terminates in P type element heavily doped region; Thereby avoid the electric field line that draw in the drain region in the existing DSBOSOI structure partly to terminate in the source region; And the source region end barrier height that causes thus reduces; And then the electron amount that causes the source region to be injected into raceway groove increases problem; Thereby the threshold voltage that effectively suppresses the DSBOSOI device reduces; And when making soi structure in off position; Leakage current reduces, and has also improved the performance of soi structure device;
Further; Near also being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of P type source region one side than the below of thin oxide layer; Make not to be terminated corresponding P type element heavily doped region below the side wall that electric field line at P type element heavily doped region corresponding below the side wall of drain region one side terminates in source region one side, also further reduced leakage current.
Description of drawings
Fig. 1 is the soi structure with buried oxide of the prior art;
Fig. 2 is the soi structure and the lattice temperature comparison diagram with soi structure of notch cuttype buried oxide with single thickness buried oxide;
Fig. 3 is the PGP DSBO soi structure sketch map that embodiment one provides;
Fig. 4 be the soi structure with buried oxide of the prior art source electrode and substrate ground connection, drain electrode is when applying 1V, the potential line distribution sketch map that this structure is corresponding;
Fig. 5 is provided with P type element heavily doped region on structure shown in Figure 4, and source electrode and substrate ground connection, when drain electrode applies 1V, the potential line distribution sketch map that this structure is corresponding;
Fig. 6 is that Fig. 4 and structure corresponding threshold voltage shown in Figure 5 and channel length with different channel lengths concern sketch map;
Fig. 7 is Fig. 4 drain region institute making alive every decline 0.1V corresponding with structure shown in Figure 5 with different channel lengths, and threshold voltage decline degree and channel length concern sketch map;
Fig. 8 is that Fig. 4 leakage current and the channel length corresponding with structure shown in Figure 5 with different channel lengths concerns sketch map;
Fig. 9 is the manufacture method flow chart of the PGP DSBO soi structure that provides of embodiment one;
Figure 10-Figure 19 is the intermediate structure sketch map that manufacture method shown in Figure 9 forms;
Figure 20-Figure 22 is the intermediate structure sketch map that another manufacture method that embodiment one provides forms;
Figure 23 is the PGP DSBO soi structure sketch map that embodiment two provides.
Embodiment
Described in background technology; The very big problem of leakage current often appears in existing soi structure when OFF state; The present inventor proposes to be employed on the existing DSBOSOI basis and correspondingly below near the side wall of N type drain region one side to be provided with P type element heavily doped region in than the P-type semiconductor substrate below the thin oxide layer; Utilized P type element heavily doped region electromotive force minimum; The electric field line that to draw from the drain region terminates in P type element heavily doped region; Thereby avoid the electric field line that draw in the drain region in the existing DSBOSOI structure partly to terminate in the source region; And the source region end barrier height that causes thus reduces; And then the source region electronics that causes is crossed this potential barrier easily and is entered into the drain region problem; Improved the threshold voltage of soi structure; When making soi structure in off position; Leakage current reduces, and has improved the performance of soi structure device.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.Since focus on explanation principle of the present invention, therefore, drawing not in scale.
First embodiment
The soi structure one PGP DSBO SOI that present embodiment one provides (Partially Ground Plane Double Step Buried Oxide SOI) as shown in Figure 3, comprising:
P type semiconductor substrate 20 is formed with the notch cuttype oxide layer 21 of N type source region 22, N type drain region 23 and N type source region 22, N type drain region 23 and P type raceway groove below on the said Semiconductor substrate; Wherein, oxide layer 21 thickness that are positioned at N type source region 22 and N type drain region 23 are respectively greater than the thickness of the oxide layer 21 that is positioned at P type raceway groove below;
Be formed at the gate insulator 24 of P type raceway groove top;
Be positioned at the grid 25 on the gate insulator;
The sidewall 26 of cover gate 25 and gate insulator 24 sides;
Wherein, near being provided with P type element heavily doped region 27 in the corresponding P type semiconductor substrate 20 in side wall 26 belows of N type drain region 23 1 sides than the below of thin oxide layer 21.
Through correspondence position below drain region 23 P type element heavily doped region 27 is set, has utilized P type element heavily doped region electromotive force minimum, will terminate in P type element heavily doped region 27 by 23 electric field lines of drawing from the drain region.
In the practical implementation process; Escape for the part electric field line of avoiding drain region 23 to draw and to terminate in P type element heavily doped region 27; Correspondingly below near the side wall 26 of N type source region 22 1 sides be provided with P type element heavily doped region 28 in than the P type semiconductor substrate 20 below the thin oxide layer 21, guarantee that further all electric field lines that drain region 23 is drawn all terminate in P type element heavily doped region.
In the practical implementation process; P type element is generally boron group element in the Semiconductor substrate 20, boron for example, and the P type element in the P type element heavily doped region 27,28 is identical with other regional P type in the Semiconductor substrate 20; Also be boron, can certainly be set to different boron group elements as required.
Further, the concentration that is arranged in Semiconductor substrate 20 other regional P type elements is generally 10
15Every cubic centimetre of magnitude of individual atom, the P type concentration of element in the P type element heavily doped region 27,28 is generally 10
18-10
19Every cubic centimetre in individual atom, therefore, the P type concentration of element in the P type element heavily doped region 27,28 is 1000 times to 10000 times of concentration that are arranged in Semiconductor substrate 20 other regional P type elements.
In order to verify the effect of the technical scheme that present embodiment one provides; The present inventor has carried out the comparative simulation test to DSBOSOI structure and PGP DSBO soi structure; The soi structure that adopts all is long 0.15 micron; High 0.6 micron (wide is 1 micron); Than thin oxide layer 21 thickness 20 nanometers; Than thick oxide layer 21 thickness 100 nanometers; The DSBO soi structure that P type element heavily doped region is not set as shown in phantom in Figure 4, the PGP DSBO soi structure that P type element heavily doped region 27,28 is set is as shown in phantom in Figure 5.Wherein, the condition of comparative simulation all is: P type semiconductor substrate 20 and source region 22 difference ground connection, drain region 23 applies 1V voltage.The potential lines of DSBO soi structure is (except the horizontal ordinate scale graticule) shown in fine line among Fig. 4, and electric field line is shown in heavy line, and the direction of arrow is represented the direction of electromotive force reduction, i.e. direction of an electric field.The potential lines of PGP DSBO soi structure is (except the horizontal ordinate scale graticule) shown in fine line among Fig. 5, and electric field line is shown in heavy line, and the direction of arrow is represented the direction of electromotive force reduction, i.e. direction of an electric field.In conjunction with Fig. 4 and Fig. 5; Can find out; The electric field line that draw in the drain region in the DSBO soi structure partly terminates in the source region; This can cause source region end barrier height to reduce; And then cause the source region electronics to cross the problem that this potential barrier enters into the drain region easily; And PGP DSBO soi structure is provided with P type element heavily doped region 27 through correspondence position below drain region 23; Source region 22 below correspondence positions are provided with P type element heavily doped region 28; Utilized P type element heavily doped region electromotive force minimum, will terminate in P type element heavily doped region 27,28 by 23 electric field lines of drawing from the drain region.
Whether crossing this potential barrier easily for source region 22 electronics enters into the drain region and can be weighed by the size of threshold voltage (Vth).Can improve threshold voltage in order to verify through P type element heavily doped region 27,28 is set; The present inventor has simulated for the PGP DSBO soi structure of different channel lengths and DSBOSOI structure; Both threshold voltages (Vth) respectively with the corresponding relation of channel length; As shown in Figure 6; Wherein source region and drain region length all are 0.05 micron; Highly all be 0.6 micron, width all is 1 micron.Can find out, same channel length, the threshold voltage of PGP DSBO soi structure illustrates that greater than the threshold voltage of DSBO soi structure the PGP DSBO soi structure that is provided with P type element heavily doped region 27,28 has improved threshold voltage.The channel length of Fig. 4 and structure shown in Figure 5 all is 0.05 micron, and corresponding threshold voltage is respectively about 0.45V and 0.6V.
In addition; The inventor has also simulated for the PGP DSBO soi structure of different channel lengths and DSBO soi structure; Be applied to the every decline 0.1V of voltage in the drain region of two kinds of structures respectively, the relation of corresponding threshold voltage decline degree and channel length, as shown in Figure 7.Can find out; For same channel length; The threshold voltage decline degree of PGP DSBO soi structure illustrates also that less than the threshold voltage decline degree of DSBO soi structure the PGP DSBO soi structure that is provided with P type element heavily doped region 27,28 has improved threshold voltage.
When PGP DSBO soi structure can also make soi structure in off position, leakage current reduced, and the inventor has simulated PGP DSBO soi structure and the DSBO soi structure with different channel lengths, both leakage current (I
Off) respectively with the corresponding relation of channel length, as shown in Figure 8.Wherein, simulated conditions all are: source region 22 ground connection, grid 25 is making alive not, applies 1V voltage on the drain region 23.As can be seen from Figure 8, for same channel length, the leakage current of PGP DSBO soi structure illustrates that less than the leakage current of DSBO soi structure the PGPDSBO soi structure that is provided with P type element heavily doped region 27,28 has improved the performance of soi structure device.The channel length of Fig. 4 and structure shown in Figure 5 all is 0.05 micron, and corresponding leakage current is respectively 10
-14A and 10
-13The A magnitude.
The present invention provides the manufacture method of the soi structure with notch cuttype buried oxide among the embodiment one simultaneously, and this manufacture method flow process as shown in Figure 9.Below in conjunction with Figure 10-Figure 19 this method is specifically described.
At first; Execution in step S11; P type semiconductor with BOX layer substrate is provided; Said P type semiconductor substrate comprises first area, the second area that is used to form grid that is used to form the source region, the 3rd zone that is used to form the drain region, is formed with grid, gate insulator and hard mask layer on the said second area.
This step can may further comprise the steps S111-S114 in the practical implementation process.
Step S111; P type semiconductor substrate 20 is provided; Structure as shown in figure 10, said Semiconductor substrate 20 comprises the first area that is used to form the source region (indicating), be used to form the second area (indicating) of grid, be used to form the 3rd zone (indicating) in drain region.
Step S112,201 pairs of Semiconductor substrate 20 are carried out the oxonium ion injection through the surface of said Semiconductor substrate 20, and high annealing forms BOX layer 202, forms structure as shown in figure 11; Said surperficial 201 can be the upper surface of Semiconductor substrate 20; It is techniques well known that said oxonium ion injects formation BOX layer process, repeats no more at this.
Step S113, deposit first insulating barrier 24, polysilicon layer 25 and hard mask layer 29 successively on the surface 201 of said Semiconductor substrate 20 form structure as shown in figure 12; In this step, first insulating barrier, 24 materials can be silicon dioxide, and hard mask layer 29 can be the three-decker of oxide-nitride thing-oxide.
Step S114, the said hard mask layer of selective etch 29, polysilicon layer and 25 first insulating barriers 24 to keep grid 25, gate insulator 24 and the hard mask layer 29 on the second area, form structure as shown in figure 13.Said selective etch technology is techniques well known, repeats no more at this.Need to prove,, therefore adopt same label sign because grid 25, gate insulator 24 and hard mask layer 29 on the second area are the part of polysilicon layer 25, first insulating barrier 24 and hard mask layer 29.Structure shown in Figure 13 also can be provided by prior art.
Follow execution in step S12; The Semiconductor substrate 20 of 201 couples the 3rd area B OX layer, 202 adjacent lower zone is carried out the injection of P type ion through the surface of said P type semiconductor substrate 20; To form the corresponding P type element heavily doped region 27 in 202 times drain region of BOX layer, form structure as shown in figure 14.P type element is generally boron group element in the Semiconductor substrate 20; Boron for example, in the ion implantation process, the P type element that forms in the P type element heavily doped region 27 can be identical with other regional P type in the Semiconductor substrate 20; Also be boron, can certainly be set to different boron group elements as required.In addition, the degree of depth that ion injects is relevant with the injection energy of ions, and the concentration that ion injects is relevant with the dosage that ion injects, and the concentration that is arranged in Semiconductor substrate 20 other regional P type elements is generally 10
15Every cubic centimetre of magnitude of individual atom, the P type concentration of element in the P type element heavily doped region 27 is generally 10
18-10
19Every cubic centimetre in individual atom, therefore, when ion injected, P type concentration of element was 1000 times to 10000 times of concentration that are arranged in Semiconductor substrate 20 other regional P type elements.
In this step implementation, can also comprise: the Semiconductor substrate 20 of first area BOX layer 202 adjacent lower zone is carried out P type ion inject,, form structure as shown in figure 15 to form the corresponding P type element heavily doped region 28 in 202 times source region of BOX layer.
Then execution in step S13, deposit second insulating barrier (not shown) on the Semiconductor substrate 20 in said hard mask layer 29 and first area and the 3rd zone eat-backs to form the sidewall 26 of the said hard mask layer of covering 29, grid 25 and gate insulator 24 sides; Said sidewall 26 is positioned at first area and the 3rd zone, forms structure as shown in figure 16.The second insulating barrier material can be silicon dioxide, and deposit and etch-back technics are techniques well known, repeat no more at this.
Execution in step S14 then, dry etching is removed the sidewall 26 of hard mask layer 29 sides, forms structure as shown in figure 17.
Follow execution in step S15; 201 pairs of Semiconductor substrate 20 that are positioned at BOX layer 202 below corresponding with the 3rd zone, first area except that sidewall 26 are carried out the oxonium ion injection through the surface of said Semiconductor substrate 20; Form oxonium ion injection region 203, form structure as shown in figure 18.
Execution in step S16, the first area and the 3rd regional Semiconductor substrate 20 that are positioned on the BOX layer 202 through 201 pairs on the surface of said P type semiconductor substrate 20 are carried out the injection of N type ion, to form source region 22 and drain region 23, form structure as shown in figure 19; This step ion implantation technology is a techniques well known, repeats no more at this.
Execution in step S17 removes hard mask layer 29; The removal method of said hard mask layer is a techniques well known, repeats no more at this.
Step S18; Behind the high annealing; Oxonium ion injection region 203 has formed the oxide layer 21 with notch cuttype with BOX layer 202, so accomplishes the making of PGP DSBO SOI (Partially Ground Plane Double Step Buried Oxide SOI) structure, forms structure as shown in Figure 3.
Need to prove that the execution sequence of step S15 and step S16 also can be first execution in step S16, execution in step S15 that is: forms source region 22 and drain region 23 earlier again, forms oxonium ion injection region 203 again.Owing to can may form defective to source region 22 and drain region 23, therefore preferred first execution in step S15, execution in step S16 again through source region 22 and drain region 23 in the oxonium ion injection process.
Alternatively; Among the step S14 of present embodiment one; Dry etching is removed the sidewall 26 of hard mask layer 29 sides; Because dry etching is the process of downward " eating ", therefore, the sidewall that is positioned at grid 25 and gate insulator 24 sides is also shorter in the size in first area and the 3rd zone; Execution in step S15 process afterwards; Be in the oxonium ion implantation step, formation also bigger than the thick oxide layer width dimensions, and then cause the width dimensions of P type element heavily doped region 27,28 to diminish.In order to form the long P type element heavily doped region 27,28 of width dimensions; Can take to execute on the architecture basics shown in Figure 16 of formation at step S13; Follow execution in step S15; 201 pairs of Semiconductor substrate 20 that are positioned at BOX layer 202 below corresponding with the 3rd zone, first area except that sidewall 26 are carried out the oxonium ion injection through the surface of said Semiconductor substrate 20; Form oxonium ion injection region 203, form structure as shown in figure 20.
Execution in step S16, the first area and the 3rd regional Semiconductor substrate 20 that are positioned on the BOX layer 202 through 201 pairs on the surface of said P type semiconductor substrate 20 are carried out the injection of N type ion, to form source region 22 and drain region 23, form structure as shown in figure 21; This step ion implantation technology is a techniques well known, repeats no more at this.
Execution in step S14 then, dry etching is removed the sidewall 26 of hard mask layer 29 sides, and then execution in step S17 removes hard mask layer 29; The structure that forms as shown in figure 22.
Be understandable that; Structure shown in Figure 22 is through step S18; Behind the high annealing; Oxonium ion injection region 203 is after BOX layer 202 forms notch cuttype oxide layer 21, and the width dimensions of P type element heavily doped region 27,28 of so accomplishing PGP DSBO soi structure is bigger than the width dimensions of P type element heavily doped region 27,28 among Fig. 3.When the electric field line that draw in the drain region in 27,28 pairs of existing DSBO soi structures of solution of said large-sized P type element heavily doped region partly terminates in the problem in source region, the better effects if that reaches.
Second embodiment
If claim that the soi structure that first embodiment provides is NMOS; Different with first embodiment is; The soi structure that present embodiment two provides is PMOS; Be understandable that; No matter NMOS or PMOS; P type element heavily doped region all is the minimum zone of electromotive force; Therefore; P type element heavily doped region is set in the soi structure of PMOS also can be played and avoid the electric field line that draw in the drain region in the existing DSBOSOI structure partly to terminate in the source region; And the source region end barrier height that causes thus reduces; And then the source region electronics that causes is crossed this potential barrier easily and is entered into the drain region problem; Improved the threshold voltage of soi structure; When making soi structure in off position, leakage current reduces, and has improved the performance of soi structure device.
Particularly, the second embodiment of the present invention provide another have the soi structure of notch cuttype buried oxide, as shown in figure 23, comprising:
P type semiconductor substrate 20; The top layer of said Semiconductor substrate 20 is a N type doped region 30; Said N type doped region 30 is formed with P type source region 22 ', P type drain region 23 ' and N type raceway groove, and N type doped region 30 belows in the said Semiconductor substrate 20 are formed with the notch cuttype oxide layer; Wherein, the oxidated layer thickness corresponding with P type source region 22 ' and P type drain region 23 ' below respectively greater than with N type raceway groove below corresponding thickness of oxide layer;
Be formed at the gate insulator 24 of N type raceway groove top;
Be positioned at the grid 25 on the gate insulator 24;
The sidewall 26 of cover gate 25 and grid 24 insulating barrier sides;
Wherein, near being provided with P type element heavily doped region 27 in the corresponding P type semiconductor substrate 20 in side wall 26 belows of P type drain region 23 ' one side than the below of thin oxide layer.
With first embodiment similarly, near being provided with P type element heavily doped region 28 in the corresponding P type semiconductor substrate 20 in side wall 28 belows of P source region 22 ' one side than the below of thin oxide layer.
Further, P type element in the P type element heavily doped region and P type source region 22 ', P type element is identical in the P type drain region 23 ', all is boron group element, for example boron.
Further, the P type concentration of element scope in the P type element heavily doped region 27,28 is 10
18-10
19Every cubic centimetre in individual atom.
In conjunction with flow chart Fig. 9 that embodiment one provides, the present invention also provides second kind of manufacture method with soi structure of notch cuttype buried oxide, and different with first embodiment is:
(1) the P type semiconductor substrate that provides among the step S11 with BOX layer; The top layer of said Semiconductor substrate 20 is N type doped region 30 (referring to shown in Figure 23); Said N type doped region 30 comprises first area, the second area that is used to form grid that is used to form the source region, the 3rd zone that is used to form the drain region, is formed with grid, gate insulator and hard mask layer on the said second area.
In this step, N type doped region 30 can carry out N type ion and inject through the top layer in 201 pairs of Semiconductor substrate 20 of upper surface of Semiconductor substrate 20.In the present embodiment two, the upper surface 201 of Semiconductor substrate 20 is same surface with the topsheet surface 201 of N type doped region 30, therefore, adopts same sign.Said ionic type is a nitrogen group element, for example nitrogen or phosphorus, and the purpose that said N type ion injects is to form N type top layer substrate.
(2) step S12, corresponding Semiconductor substrate 20 is carried out the injection of P type ion through the topsheet surface below, 201 pairs the 3rd zones of said N type doped region 30, to form the corresponding P type element heavily doped region 27 in 202 times drain region of BOX layer.This step implementation can also comprise: the corresponding Semiconductor substrate 20 in below, first area is carried out P type ion inject, to form the corresponding P type element heavily doped region 28 in source region under the BOX layer.
(3) step S13, second insulating barrier of deposit is formed in the topsheet surface 201 of N type doped region 30.
(4) step S15, the surface of carrying out the oxonium ion injection is the topsheet surface 201 of said N type doped region 30.
(5) step S16, the N type doped region 30 that is positioned at first area and the 3rd zone on the BOX layer 202 through 201 pairs of the topsheet surface of said N type doped region 30 carries out P type ion and injects, to form source region 22 ' and drain region 23 '.
Need to prove that among second embodiment, in order to form the soi structure of PMOS, the execution sequence of step S15 and step S16 also can be first execution in step S16, carries out S15 again, that is: form source region 22 ' and drain region 23 ' earlier, form oxonium ion injection region 203 again.Similarly, owing to can may form defective to source region 22 ' and drain region 23 ', therefore preferred first execution in step S15, execution in step S16 again through source region 22 ' and drain region 23 ' in the oxonium ion injection process.
Alternatively; Among the step S14 of present embodiment two; Dry etching is removed the sidewall 26 of hard mask layer 29 sides; Because dry etching is the process of downward " eating ", therefore, the sidewall that is positioned at grid 25 and gate insulator 24 sides is also shorter in the size in first area and the 3rd zone; Execution in step S15 process afterwards; Be in the oxonium ion implantation step, formation also bigger than thick oxide layer 21 width dimensions, and then cause the width dimensions of P type element heavily doped region 27,28 to diminish.With first embodiment similarly; For the electric field line that will draw from the drain region better terminates in P type element heavily doped region 27,28; Can form the long P type element heavily doped region 27,28 of width dimensions; Said formation method can be taked to execute on the architecture basics of formation at step S13; Follow execution in step S15; Carry out oxonium ion through 201 pairs of Semiconductor substrate 20 that are positioned at BOX layer 202 below corresponding, first area except that sidewall 26 of topsheet surface of N type doped region 30 and inject, form oxonium ion injection region 203 with the 3rd zone.
Execution in step S16, the Semiconductor substrate 20 that is positioned at first area and the 3rd zone on the BOX layer 202 through 201 pairs of the topsheet surface of said N type doped region 30 is carried out P type ion and is injected, to form source region 22 ' and drain region 23 '.
Execution in step S14 then, dry etching is removed the sidewall 26 of hard mask layer 29 sides, and then execution in step S17 removes hard mask layer 29.
Be understandable that; Pass through step S18 again; Behind the high annealing; Oxonium ion injection region 203 is so accomplished the width dimensions of the P type element heavily doped region 27,28 of PGP DSBO soi structure and can be realized the big purpose of width dimensions than P type element heavily doped region 27,28 among Figure 23 after BOX layer 202 forms notch cuttype oxide layer 21.
Compared with prior art; The present invention is employed on the existing DSBOSOI basis near being provided with P type element heavily doped region in the corresponding P-type semiconductor substrate than the below of thin oxide layer in the side wall below of N/P type drain region one side; Utilized P type element heavily doped region electromotive force minimum; The electric field line that to draw from the drain region terminates in P type element heavily doped region; Thereby avoid the electric field line that draw in the drain region in the existing DSBOSOI structure partly to terminate in the source region; And the source region end barrier height that causes thus reduces; And then the electron amount that causes the source region to be injected into raceway groove increases problem; Thereby the threshold voltage that effectively suppresses the DSBOSOI device reduces; And when making soi structure in off position; Leakage current reduces, and has improved the performance of soi structure device.
Further; Near also being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of N/P type source region one side than the below of thin oxide layer; Make not to be terminated corresponding P type element heavily doped region below the side wall that electric field line at P type element heavily doped region corresponding below the side wall of drain region one side terminates in source region one side, further reduce leakage current.
Further; Carry out the oxonium ion implantation step earlier; Dry etching is removed the sidewall of hard mask layer side again; Utilizing said sidewall to stop influences the width that oxonium ion injects the oxonium ion injection region that forms; Make behind the high annealing; What form is also smaller than the thick oxide layer width dimensions, thereby makes that the width dimensions of P type element heavily doped region is bigger, can better the electric field line of drawing from the drain region be terminated in P type element heavily doped region.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. soi structure with notch cuttype buried oxide comprises:
The P type semiconductor substrate is formed with the notch cuttype oxide layer of N type source region, N type drain region and N type source region, N type drain region and P type raceway groove below on the said P type semiconductor substrate; Wherein, the oxidated layer thickness that is positioned at N type source region and N type drain region is respectively greater than the thickness of oxide layer that is positioned at P type raceway groove below;
Be formed at the gate insulator of P type raceway groove top;
Be positioned at the grid on the gate insulator;
The sidewall of cover gate and gate insulator side;
It is characterized in that, near being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of N type drain region one side than the below of thin oxide layer.
2. soi structure according to claim 1 is characterized in that, near also being provided with P type element heavily doped region in the corresponding P type semiconductor substrate than the below of thin oxide layer in the side wall below of N type source region one side.
3. soi structure according to claim 1 and 2 is characterized in that, P type element is identical in the P type element in the P type element heavily doped region and other regional P type semiconductor substrate.
4. soi structure according to claim 1 and 2 is characterized in that, the P type element in the P type element heavily doped region is a boron element.
5. soi structure according to claim 1 and 2 is characterized in that, the P type concentration of element in the P type element heavily doped region is 1000 times to 10000 times of concentration that are positioned at other regional P type element.
6. soi structure with notch cuttype buried oxide comprises:
P type semiconductor substrate, the top layer of said Semiconductor substrate are N type doped region, and said N type doped region is formed with P type source region, P type drain region and N type raceway groove, and the N type doped region below in the said Semiconductor substrate is formed with the notch cuttype oxide layer; Wherein, the corresponding oxidated layer thickness in P type source region and P type drain region below respectively greater than with N type raceway groove below corresponding thickness of oxide layer;
Be formed at the gate insulator of N type raceway groove top;
Be positioned at the grid on the gate insulator;
The sidewall of cover gate and gate insulator side;
It is characterized in that, near being provided with P type element heavily doped region in the corresponding P type semiconductor substrate in the side wall below of P type drain region one side than the below of thin oxide layer.
7. soi structure according to claim 6 is characterized in that, near also being provided with P type element heavily doped region in the corresponding P type semiconductor substrate than the below of thin oxide layer in the side wall below of P type source region one side.
8. according to claim 6 or 7 described soi structures, it is characterized in that P type element is identical in the P type element in the P type element heavily doped region and P type source region, the P type drain region.
9. according to claim 6 or 7 described soi structures, it is characterized in that the P type element in the P type element heavily doped region is a boron element.
10. soi structure according to claim 9 is characterized in that, the P type concentration of element scope in the P type element heavily doped region is 10
18-10
19Every cubic centimetre in individual atom.
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| CN103311301A (en) * | 2013-05-09 | 2013-09-18 | 北京大学 | SOI (Silicon On Insulator) device for inhibiting current leakage of back gate due to radiation and preparation method thereof |
| CN112436051A (en) * | 2020-11-03 | 2021-03-02 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with symmetrical stepped oxygen buried layer |
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| CN1623226A (en) * | 2002-03-28 | 2005-06-01 | 先进微装置公司 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
| CN101794712A (en) * | 2010-01-28 | 2010-08-04 | 中国科学院上海微系统与信息技术研究所 | Method for inhibiting floating-body effect of SOI (Signal Operation Instruction) MOS (Metal Oxide Semiconductor) device by large-angle ion implantation |
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| CN1623226A (en) * | 2002-03-28 | 2005-06-01 | 先进微装置公司 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
| CN101794712A (en) * | 2010-01-28 | 2010-08-04 | 中国科学院上海微系统与信息技术研究所 | Method for inhibiting floating-body effect of SOI (Signal Operation Instruction) MOS (Metal Oxide Semiconductor) device by large-angle ion implantation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103311301A (en) * | 2013-05-09 | 2013-09-18 | 北京大学 | SOI (Silicon On Insulator) device for inhibiting current leakage of back gate due to radiation and preparation method thereof |
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| CN112436051A (en) * | 2020-11-03 | 2021-03-02 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with symmetrical stepped oxygen buried layer |
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