CN102354255A

CN102354255A - Phase amplitude converting method in direct digital synthesizer (DDS)

Info

Publication number: CN102354255A
Application number: CN2011101552000A
Authority: CN
Inventors: 朱晨阳; 王海兵; 宗渭钧; 郭斌
Original assignee: WUXI JINGYUAN MICROELECTRONICS CO Ltd
Current assignee: WUXI JINGYUAN MICROELECTRONICS CO Ltd
Priority date: 2011-06-10
Filing date: 2011-06-10
Publication date: 2012-02-15

Abstract

The invention discloses a phase amplitude converting method in a direct digital synthesizer (DDS). In a phase amplitude converter of the DDS, the output theta of a phase accumulator is directly converted into amplitude after being logically corrected; only primary time-delay buffer is performed on the output of the phase accumulator before the output of the phase accumulator reaches a digital/analog (D/A) converter, and compared with a coordinated rotation digital computer (CORDIC) method, the phase time-delay quality is much smaller; and moreover, programming thinking is very simple; the source of the basic theory of the programming thinking is to sample 255 points from a sine function; amplitudes y which correspond to the 255 points are worked out and are compared with the theta, and then, logic correction is performed so as to approach the amplitudes y which correspond to the 255 points. In the recovery of the color carrier of a digital television, the advantage of the phase amplitude converting method in the DDS is more obvious, and moreover, the phase amplitude converting method in the DDS is successfully applied to a chroma decoding module in a television decoding chip. The phase generating the carrier of the phase amplitude converting method in the DDS is very small, and can be completely synchronous with the carrier.

Description

Phase amplitude conversion method among the DDS

Technical field

The present invention is suitable for and the signal Processing field, can be applied to the carrier synchronization system in numeral or the digital-to-analogue commingled system, provides a kind of DDS of being applied to phase accumulator to output to the method for amplitude conversion.

Background technology

Direct Digital synthetic (DDS) is the mode that a kind of pure digi-tal produces carrier wave, generally comprises three parts: phase accumulator, phase amplitude converter, D/A analog to digital converter.Phase accumulator is made up of N position totalizer and N position phase register, a similar simple counter.Totalizer is delivered to the result after the addition data input pin of accumulator register with the phase data addition that adds up of frequency control word and accumulator register output.Accumulator register is produced totalizer after a last time clock effect new phase data feeds back to the input end of totalizer, so that totalizer continues under the effect of next time clock and the frequency control word addition.Like this, phase accumulator constantly carries out linear phase to frequency control word and adds up under the clock effect.Phase amplitude converter mainly leans on the sine look up table mode now; Shown in Figure 1; It is a programmable read-only memory (prom); What store is to be the sample code value of the one-period sinusoidal signal of address with the phase place; Comprise the sinusoidal wave digital amplitude information of one-period, each address is corresponding to a phase point of 0 to 360 degree scope in the sine wave.The data that the output and the phase control words addition of phase register obtains are carried out addressing as an address offset of sinusoidal question blank, and question blank is mapped to sinusoidal wave range signal to the address phase information of input; But the method needs large-area ROM, and data volume is huge.Also have the conversion of CORDIC polar axis shaft rotary process realization phase amplitude in addition, shown in Figure 2, but it also needs the ROM of some; And need multistage iteration; There is phase bit time-delay, if among the dynamic PLL of the phase place of being applied in and strictness thereof, its PLL phase deviation is bigger.

Through the D/A transducer digital quantity is become analog quantity at last, pass through the level and smooth and unwanted sampling component of filtering of low-pass filter again, so that the pure sine wave signal of output spectrum.

Summary of the invention

Technical matters: the purpose of this invention is to provide a kind of novel conversion method that is applied to phase amplitude in the DDS system, be devoted to solve excessive problem and the bigger problem of DDS phase deviation of amplitude-phase modular converter area occupied in the digital carrier DDS mode.

Technical scheme:

This method is that example is set forth with add < 9:0>10 bit accumulators, and the highest two are used as division quadrant position, add < 9 >=0, add < 8 >=0; First quartile; Add < 9 >=0, add < 8 >=1; Second quadrant, add < 9 >=1, add < 8 >=0; Third quadrant, add < 9 >=1, add < 8 >=1; Four-quadrant.Four-quadrant possesses the characteristic of symmetry, is limited to example with four-quadrant at present; The value θ that remains 8 is as sample point, and the scope of θ is (0,255), uses following relational expression y=128+128*sin (θ * pi/2 * 255) the horizontal ordinate sample point of phase value φ as the string function, obtains ordinate just with the amplitude of sampling spot.

Y=128+128*sin (θ * pi/2 * 255) is the core foundation of this chip; This mode sampling spot is 256; The value of 256 sampling spots is obtained 256 range values by above-mentioned function calculation; Just obtain the amplitude of the sine function of 256 samplings; Being worth with this is foundation; Remove to revise totalizer output valve θ through logical operation, and then approach the amplitude of the sine function of 256 required samplings, and then accomplish the conversion of phase amplitude.

Beneficial effect: this circuit is relatively unique on realize thinking, fully independently with look-up table method and polar axis shaft rotary process, the more important thing is and has realized under the situation of same spuious inhibition, having dwindled chip area greatly.Be easier to integrated.

Description of drawings

Fig. 1 DDS structural drawing is based on the look-up table method.Comprise among the figure: phase accumulator, ROM look-up table, D/A converter.

Fig. 2 is that the DDS structural drawing is based on the CORDIC method.Comprise among the figure: phase accumulator, CORDIC, D/A converter.

Fig. 3 is a DDS structural drawing phase amplitude conversion logic method.Comprise among the figure: phase accumulator, phase amplitude conversion logic, D/A converter.

The table of comparisons of Fig. 4 totalizer θ and y=128+128*sin (θ * pi/2 * 255).

Fig. 5 simulation waveform.

Embodiment

What the present invention adopted is that width is 10 phase accumulation device add < 9:0 >, is divided into four quadrants, add < 9 >=0, add < 8 >=0; First quartile; Add < 9 >=0, add < 8 >=1; Second quadrant, add < 9 >=1, add < 8 >=0; Third quadrant, add < 9 >=1, add < 8 >=1; Four-quadrant.First quartile is an increasing sequence, and corresponding sine function amplitude range (128,255), accumulator count scope are (0,255); Second quadrant is a descending series, corresponding sine function amplitude range (255,128); And the phase accumulator counting region is (0,255), or ascending series; So must depend on add < 9 >=0, y=255-128*sin (θ * pi/2 * 255) is revised in add < 8 >=1 combination.The corresponding sine function amplitude range (128,0) of third quadrant, and the phase accumulator counting region is (0,255), or ascending series, so depend on add < 9 >=0, add < 8 >=1 revises y=128-128*sin (θ * pi/2 * 255); Four-quadrant string function amplitude range (0,128), so must depend on add < 9 >=1, add < 8 >=1 revises.

Suppose that sinusoidal amplitude is y, it is 255 that sampling is counted, and θ is phase accumulator output, and then the expression formula of its discrete sampling function is:

y=128*sin(θ*π/2*255)。

The concrete derivation as follows:

Y=128*sin (θ * pi/2 * 255) can find out that from figure four θ counting region (0,255) is sampled 256 times altogether, that is to say that the value of y is reduced by 256 points, and the scope of y is (128,255); So the maximum modified value of θ is 128, so θ proofreaies and correct through logic, and the theory origin of proofreading and correct is exactly the data of figure four, and hypothesis is revised the back value and is Δ θ=θ-y here.Δ θ scope (0.5 ,+0.5).

The corresponding y=8.66. Δ in θ=10 θ=10-8.66=1.34 for instance, but Δ θ must be an integer, thus just need Δ θ=1, θ=10 o'clock, the back logical operation module, what done is exactly to subtract one.θ=234 o'clock for another example, y=128, Δ θ=106; θ=255 o'clock for another example, y=128, Δ θ=127, the logical operation of back logic module subtracts 127 exactly.

The logical design that logic module is just static does not relate to the register delay process, so sequential processing is fairly simple, can obviously find out among Fig. 3.And the logical design thinking is very simple, and it is also very simple to encode, and according to the requirement of figure four data, different θ gives different correction coefficient, just does some simple static subtraction process.

Claims

1. the phase amplitude conversion method among the DDS; It is characterized in that adopting phase accumulator, phase amplitude converter and D/A converter; With θ as sample point; The scope of θ is (0; 255); Use following relational expression y=128+128*sin (θ * pi/2 * 255) the horizontal ordinate sample point of phase value φ, obtain ordinate just with the amplitude of sampling spot as the string function.