CN102348324B - There is between wiring pattern the electronic module of feedthrough conductor - Google Patents

There is between wiring pattern the electronic module of feedthrough conductor Download PDF

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Publication number
CN102348324B
CN102348324B CN201110205912.9A CN201110205912A CN102348324B CN 102348324 B CN102348324 B CN 102348324B CN 201110205912 A CN201110205912 A CN 201110205912A CN 102348324 B CN102348324 B CN 102348324B
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China
Prior art keywords
wiring layer
conductor
micro
via hole
feedthrough
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CN201110205912.9A
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CN102348324A (en
Inventor
A·伊郝拉
R·图奥米宁
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Imberatec Co., Ltd
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Imbera Electronics Oy
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Priority claimed from US12/842,056 external-priority patent/US8455994B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Electronic module comprises: dielectric (1031) substrate with first surface and second surface; Installation cavity, extend through dielectric substrate and have lateral wall; The first wiring layer (1032) on the first surface; The second wiring layer (1033) on a second surface; Feedthrough conductor (1034) on lateral wall, makes at least one conductor in the first wiring layer be electrically connected at least one conductor in the second wiring layer; At least one IC is had in installation cavity; The first insulating barrier (1035) on the second wiring layer; The second insulating barrier (1036) on the first wiring layer; The 3rd wiring layer (1037) on the first insulating barrier.In first insulating barrier first micro-via hole (1038) makes the second wiring layer and the electrical connection of the 3rd wiring layer.IC is connected at least one in the second wiring layer and the 3rd wiring layer by second micro-via hole (1039).Electronic module comprises: the 4th wiring layer (1040) over the second dielectric; The 3rd micro-via hole (1041) in second insulating barrier, makes the first wiring layer and the electrical connection of the 4th wiring layer.

Description

There is between wiring pattern the electronic module of feedthrough conductor
Technical field
The present invention relates to electronic module and structure member thereof.
Especially, the present invention relates to so a kind of electronic module: it at least one semiconductor subassembly comprising at least four wiring diagram pattern layer and be embedded at least partly in the insulating barrier between this wiring diagram pattern layer.
Background technology
Publication number is that the United States Patent (USP) (Asahi etc.) of 2002/0135058A1 discloses a kind of assembly built-in module using plated-through-hole method.By means of introduced embodiment, wiring density (routingdensity) can be increased and do not need to build many increasing layers or do not need to build to increase layer.But when being used for this method to have the microcircuit such as becoming hundred pads, this method efficiency is low waits a moment, thus adds manufacturing time and cost.
At present, many diverse ways and available technology is had between the both sides of wiring plate, to form electrical connection by means of through hole (also referred to as through hole).An early stage method for the formation of through hole uses the conduction riveting pin be assemblied in the through hole of the other wiring plate made.The assembling of riveting pin method is slow and expensive, unreliable and fully can not reduce the size of necessary through hole.Other art methods is plated-through-hole (PTH) and via hole-upper-via hole (via-on-via) structure.The method of all prior aries all can not solve the problem.
Such as, the micro-via hole of reliable conduction using chemistry and/or electroplating technology in fact can not realize aspect ratio (high/wide) when the diameter of micro-via hole is 150 μm or following to be greater than 100.Under general aspect ratio is 8:1 and maximum aspect ratio is the through hole of 12:1, be also the same.In other words, throwing power limits narrow and deep through hole or micro-via hole becomes reliably conducting and is combined securely with electric conducting material.Throwing power refers to the ability making to be full of in narrow and deep through hole or micro-via hole electric conducting material by chemistry or electrolytic growth method.When the diameter of micro-via hole and through hole is 150 μm or following, is greater than in micro-via hole of above-mentioned aspect ratio and through hole in respective aspect ratio and uses the situation of the conductive paste of any kind or adhesive to be also similar.
Therefore, background technology comprises different solutions, but they all can not fully provide high wiring efficiency in product price acceptable situation.Consider wiring efficiency and price, especially when being intended to the number of contacts of increase assembly and making the pitch between the contact weld district on assembly or projection narrow, also need the further technology seeking there is potential improvement characteristic.
Summary of the invention
According to an aspect of the present invention, a kind of electronic module is provided, comprises:
Dielectric substrate, has first surface and second surface;
Installation cavity, extends through this dielectric substrate and have peripheral sidewall between this first surface and this second surface;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
Feedthrough conductor, the peripheral sidewall being arranged in this installation cavity makes at least one conductor of this first wiring layer be electrically connected at least one conductor of this second wiring layer;
At least one semiconductor subassembly, is positioned at this installation cavity at least partly;
First insulating barrier, is positioned on this second wiring layer;
Second insulating barrier, is positioned on this first wiring layer;
3rd wiring layer, is positioned on this first insulating barrier;
First micro-via hole, makes to be electrically connected between this second wiring layer and the 3rd wiring layer in this first insulating barrier;
Second micro-via hole, makes this at least one semiconductor subassembly be connected to this second wiring layer and at least one in the 3rd wiring layer;
4th wiring layer, is positioned on this second insulating barrier; And
3rd micro-via hole, makes to be electrically connected between this first wiring layer and the 4th wiring layer in this second insulating barrier.
According to a further aspect in the invention, a kind of manufacture method of electronic module is provided, comprises:
The dielectric substrate with first surface and second surface is provided;
Formed and extend through dielectric substrate and the installation cavity between first surface and second surface with peripheral sidewall;
The first surface of dielectric substrate is formed the first wiring layer;
The second surface of dielectric substrate is formed the second wiring layer;
The peripheral sidewall of installation cavity is formed at least one feedthrough conductor and at least one conductor in the first wiring layer is electrically connected at least one conductor in the second wiring layer;
At least one semiconductor subassembly is arranged in installation cavity at least in part;
Second wiring layer is formed the first insulating barrier;
First wiring layer is formed the second insulating barrier;
First insulating barrier forms the 3rd wiring layer;
In the first insulating barrier, form first micro-via hole and make to be electrically connected between the second wiring layer and the 3rd wiring layer;
At least one semiconductor subassembly is electrically connected at least one second micro-via hole in the second wiring layer and the 3rd wiring layer by formation;
Form the 4th wiring layer over the second dielectric; And
In the second insulating barrier, form the 3rd micro-via hole and make to be electrically connected between the first wiring layer and the 4th wiring layer.
According to another aspect of the invention, the feedthrough conductor being positioned at installation cavity is divided into multiple part, thus on the peripheral sidewall of installation cavity, forming multiple feedthrough conductor, this feedthrough conductor makes this first wiring layer and this second wiring layer be electrically connected to each other by multiple independent power path.
Therefore, according to another aspect of the invention, electronic module comprises:
Dielectric substrate, has first surface and the second surface relative with this first surface;
Installation cavity, extends through this dielectric substrate and have peripheral sidewall between this first surface and this second surface;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
At least two feedthrough conductors, the peripheral sidewall being positioned at this installation cavity makes this first wiring layer and this second wiring layer be electrically connected to each other by least two independent power paths; And
At least one semiconductor subassembly, is positioned at this installation cavity at least partly.
According to another aspect of the invention, electronic module comprises:
Dielectric substrate, has first surface and the second surface relative with this first surface;
Installation cavity, extends through this dielectric substrate and have peripheral sidewall between this first surface and this second surface;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
At least two feedthrough conductors, the peripheral sidewall being positioned at this installation cavity makes this first wiring layer and this second wiring layer be electrically connected to each other by least two independent power paths;
At least one semiconductor subassembly, is positioned at this installation cavity at least partly.
In accordance with a further aspect of the present invention, a kind of semiconductor die package is provided, comprises:
Dielectric substrate, has first surface and the second surface relative with this first surface;
Installation cavity, extends through the dielectric substrate between this first surface and this second surface and has the sidewall limiting described installation cavity;
At least one semiconductor chip, has contact pad in this installation cavity;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
Feedthrough conductor, the first wiring layer is electrically connected with the second wiring layer by the sidewall being positioned at this installation cavity;
First insulating barrier, is positioned on this second wiring layer;
3rd wiring layer, is positioned on this first insulating barrier;
First micro-via hole, makes to be electrically connected between this second wiring layer with the 3rd wiring layer in this first insulating barrier; And
Second micro-via hole, is electrically connected to the 3rd wiring layer by least some contact pad of this semiconductor chip.
According to another aspect of the invention, the manufacture method of a kind of electronic module or semiconductor die package is provided, comprises:
The dielectric substrate with first surface and the second surface relative with first surface is provided;
Formed and extend through dielectric substrate and the installation cavity between first surface and second surface with peripheral sidewall;
The first surface of dielectric substrate is formed the first wiring layer;
The second surface of dielectric substrate is formed the second wiring layer;
The peripheral sidewall of installation cavity is formed at least two feedthrough conductors and by feedthrough conductor, the first wiring layer and the second wiring layer is electrically connected to each other; And
At least one semiconductor subassembly is at least partially disposed in installation cavity.
According to another aspect of the invention, the manufacture method of a kind of electronic module or semiconductor die package is provided, comprises:
The dielectric substrate with first surface and the second surface relative with first surface is provided;
Form at least two extend to second surface in dielectric substrate feed-through hole from first surface;
The first surface of dielectric substrate is formed the first wiring layer;
The second surface of dielectric substrate is formed the second wiring layer;
In feed-through hole, form at least two feedthrough conductors, this feedthrough conductor makes the first wiring layer and the second wiring layer be electrically connected to each other;
By cutting a part of dielectric substrate and a part of feed-through hole and feedthrough conductor, form the installation cavity through dielectric substrate, wherein installation cavity has peripheral sidewall between first surface and second surface, and the remainder of the feed-through hole after cutting forms a part for peripheral sidewall and the remainder of the feedthrough conductor after cutting is positioned on peripheral sidewall; And
At least one semiconductor subassembly is at least partially disposed in installation cavity.
Utilize the present invention can obtain considerable advantage.This is because: by the present invention, circuit board can be manufactured with form semiconductor subassembly being embedded circuit board inside.The present invention can also manufacture little and reliable component package around assembly.
The present invention also allows a large amount of embodiments providing significant added benefit.
Such as, utilize the preferred embodiment of the present invention, the assembling of the fabrication stage of component package stage, circuit board and semiconductor subassembly and contact fabrication stage can be combined to be formed one overall.The combination of various operation stage brings important logic benefit and allows manufacture less and more reliable electronic module.The further advantage of the present invention is that this manufacture method can adopt conventional circuit board fabrication and mounting technology to a great extent.
According to the preferred embodiment of the present invention, the population proportion of combination process is as used flip-chip technology to manufacture circuit board and being attached simpler on circuit boards by assembly.Compared to Traditional solutions, following advantage can be obtained by this preferred embodiment:
Do not need to weld to be formed and component touch, and electric contact can be manufactured by making conductor in the contact area grown on top of semiconductor subassembly.This means not need to use molten metal to carry out coupling assembling, therefore between metal, do not form compound.Compound between metal is normally crisp, and therefore compare the connector formed by welding, reliability improves.Especially, in little connector, the brittleness of metallic compound produces very large problem in connection procedure.Compared with welding method, according to preferred embodiment, obviously less structure can be realized than welding method without soldering method.The contact manufacture method of solderless also has does not need high temperature to form the advantage of contact.Lower technological temperature allows there are more more options when other material of selection circuit plate, component package or electronic module.In the method, the temperature of the circuit board, assembly and the conductive layer that are directly connected with assembly can remain in the scope of 20-85 DEG C.The higher temperature of such as about 150 DEG C only may be needed when solidifying the polymer film that (polymerization) uses.But, the temperature of substrate and assembly can be remained on less than 200 DEG C during whole technique.If the method adopts the polymer film hardened in other modes (such as chemistry or electromagnetic radiation) except high-temperature effect, then substrate and assembly temperature can be made in a preferred embodiment during whole technique to remain on less than 100 DEG C.
Allow owing to using the method to manufacture less structure, the interval therefore between assembly can be tightr.So the conductor between assembly also can be shorter simultaneously by reducing the loss, disturbing and improve the electrical characteristics of electronic circuit time of delay.
The method also allows to manufacture three-dimensional structure, this is because substrate and embedding assembly in the substrate can be assembled in top of each other.
In the method, the contact-making surface between different metal can also be reduced.
The method allows lead-free process.
The present invention also allows other preferred embodiment.About the present invention, such as flexible PCB can be used.In addition, this technique allows circuit board assembling on top of each other.
Utilize the present invention, can also manufacture very thin structure, wherein regardless of the thickness of substrate (such as circuit board), semiconductor subassembly can by whole protection in the substrate.
Because semiconductor subassembly can wholely be placed in circuit board, the junction therefore between circuit board and semiconductor subassembly is that machinery is durable and reliable.
Especially, when object is the quantity of increase component contacts and makes the pitch between the contact bonding pad on assembly, projection narrow, embodiment provides the possibility improving wiring efficiency with lower price.
Accompanying drawing explanation
In order to intactly understand the present invention and advantage thereof, existing by example and present invention is described with reference to appended accompanying drawing, wherein:
Fig. 1 display is according to the diagrammatic top view of the electronic module area of coverage of prior art.
Fig. 2 A-Fig. 2 I shows the first method according to the manufacture feedthrough conductor of the embodiment of the present invention.
Fig. 3 A shows the cross section view of parts needed for the electronic module of the embodiment of the present invention manufactured by first party method.
Fig. 3 B shows the cross section view of the electronic module according to the embodiment of the present invention manufactured by first party method.
Fig. 4 A-Fig. 4 J shows the second method according to the manufacture feedthrough conductor of the embodiment of the present invention.
Fig. 5 A shows the cross section view of parts needed for the electronic module of the embodiment of the present invention manufactured by second party method.
Fig. 5 B shows the cross section view of the electronic module according to the embodiment of the present invention manufactured by second party method.
Fig. 6 A-6I shows the third method according to the manufacture feedthrough conductor of the embodiment of the present invention.
Fig. 7 A shows the cross section view of parts needed for the electronic module of the embodiment of the present invention manufactured by third method.
Fig. 7 B shows the cross section view of the electronic module according to the embodiment of the present invention manufactured by third method.
Fig. 8 A shows the vertical view according to two plated-through-holes of prior art.
Fig. 8 B shows the vertical view of two feedthrough conductors according to a first embodiment of the present invention.
Fig. 8 C shows the vertical view of three feedthrough conductors according to a second embodiment of the present invention.
Fig. 8 D shows the vertical view of three feedthrough conductors according to a third embodiment of the present invention.
Fig. 8 E shows the vertical view of eight feedthrough conductors according to a third embodiment of the present invention.Fig. 8 A, Fig. 8 B, Fig. 8 C, Fig. 8 D and Fig. 8 E are that equal proportion is drawn.
The example of the feedthrough conductor that milling becomes engraved by Fig. 9 A machinery shown according to a third embodiment of the present invention.
Fig. 9 B shows the example of the feedthrough conductor that machine drilling is according to a third embodiment of the present invention made.
Fig. 9 C shows another example of the feedthrough conductor that machine drilling is according to a third embodiment of the present invention made.
Another example of the feedthrough conductor that milling becomes engraved by Fig. 9 D machinery shown according to a third embodiment of the present invention.
Fig. 9 E shows the another example of the feedthrough conductor that machine drilling is according to a third embodiment of the present invention made.
Figure 10 A shows the example of the feedthrough conductor that laser drill is according to a third embodiment of the present invention made.
Figure 10 B laser shown according to a third embodiment of the present invention engraves the example of the feedthrough conductor that milling becomes.
Figure 10 C laser shown according to a third embodiment of the present invention engraves another example of the feedthrough conductor that milling becomes.
Figure 10 D shows another example of the feedthrough conductor that laser drill is according to a third embodiment of the present invention made.
Figure 10 E shows the another example of the feedthrough conductor that laser drill is according to a third embodiment of the present invention made.
Figure 11 shows the electronic module according to the embodiment of the present invention manufactured by third method.
Figure 12 illustrates a series of cross sections according to a technique of the present invention.
Figure 13 illustrates a series of cross sections according to the second technique of the present invention.
Figure 14 illustrates a kind of schematic diagram of possible contact formation method.
Figure 15 display is according to a series of cross sections of the present invention the 3rd technique.
Embodiment
According to embodiments of the invention, feedthrough conductor assembly is made up of dielectric, forms installation cavity for the assembly that will be embedded in electronic module in this dielectric.Dielectric can have the conductive layer being layered in dielectric two sides, such as Copper Foil.Installation cavity is formed by various method.According to embodiments of the invention, first, by forming feedthrough conductor to dielectric holes drilled through.Then by dielectric and via metal and patterning.Finally, preferably engrave milling dielectric in the centre position of plated-through hole, thus present installation cavity.
According to another embodiment of the present invention, first, for milling installation cavity engraved by the assembly that will embed in electronic module.After engraving milling, by dielectric metallization and patterning.Finally, by forming opening (such as by holing or engraving milling) by feedthrough conductor separately to metallization dielectric.In addition, feedthrough conductor assembly generally includes a conductive layer.Conductive layer can be such as interconnected by micro-via hole, plated hole, buried via hole or through hole.The conductor wire of feedthrough conductor must not be straight.Conductor wire can be loop wire, curve or even the system relevant to Functional Design pattern, such as antenna, EMI shielding or similar fashion.In addition, in different layers, conductor wire can be designed to extend (such as, every alternating floor is 90 degrees to each other) along different directions.
The distance each other of the conductor on feedthrough conductor assembly must do not made identical.Such as, one group of intensive feedthrough conductor local can be arranged in the end of feedthrough conductor assembly, ad-hoc location or corner location.Correspondingly, in above-mentioned same instance, ground or EMI shielding can be had in the centre of feedthrough conductor assembly.In addition, according to the embodiment of the present invention, the assembly in electronic module can be shielded by EMI completely.Certainly, can according to designing requirement, arrange one group of intensive conductor and ground conversely.
Electronic module can comprise assembly interconnective multicompartment application by feedthrough conductor assembly, and wherein assembly is positioned at end face each other or trailing flank, and conductive welding disk is positioned at contrary or identical direction.In addition, in multilayer application, feedthrough conductor assembly can be placed together with any conductive layer or connect.The position (and connection) of electronic module inside can be asymmetric.In addition, feedthrough conductor assembly can exceed the one or more wiring layers in electronic module.
By obviously can reduce the occupy-place size of electronic module according to the feedthrough conductor assembly of the design.Use printed circuit board (PCB) as feedthrough conductor assembly, easily can realize the line/space of 30/30.By this measure, produce 100 microns (μm) or less through hole pitch.Compared to the printed circuit board (PCB) of routine, this through hole pitch is generally 300-400 micron (μm).This means easily footprints to be reduced by least 25%, even 50%, than using, the solution such as plated-through-hole and laser pad mode of prior art are less.The advantage that occupy-place size reduces is mainly reflected in be had tens, even becomes on the assembly of hundred contact pads.
Another advantage of the present invention is achieved in that and designs the thick, long of feedthrough conductor assembly and shape as required, thus extends to lower surface and unrestricted from upper surface.For traditional mechanical through hole, aspect ratio be have requirement (normally 8:1, the maximum 12:1 of being) to prepare the hole be evenly coated with.
The minimizing of the number of plies of electronic module can be realized by feedthrough conductor assembly.Due to highdensity connecting joint distance, minimizing is therefore needed to increase the quantity of layer or increasing layer is not set.
Greatly reliability can be improved by feedthrough conductor assembly.According to embodiments of the invention, the feedthrough conductor assembly with the printed circuit board (PCB) of copper (Cu) trace is all metal and is uniform, therefore very reliable when being exposed under thermal cycle or shock test.Bury through hole with the routine being filled with epoxy resin to compare with the through hole being filled with air.
Feedthrough conductor assembly can be made as arbitrarily other electronic building brick in advance, such as microchip, processor or almost Arbitrary Passive or active block.Due to this prefabricated, easily manufacturing cost can be saved.In addition, just as other electronic building brick, all feedthrough conductor assemblies in assembling and can check it before embedding them.Provide cost savings further by improving output.
Semiconductor packages can comprise the one or more semiconductor chips in the electronic module utilizing feedthrough conductor assembly of the present invention.The invention is not restricted to use together with embedded components, in fact can also with integrated circuit, discrete component and other all component in the conventional way, " traditional " printed circuit board (PCB) of assembling of such as surface mounting technology (SMT) uses together with substrate.
Fig. 1 display is according to the diagrammatic top view of the electronic module 1 of prior art.Assembly 10 needs the space of 4mm × 4mm.Assembly 10 has 160 contact pads guided via plated-through-hole 14.Plated-through-hole 14 is arranged in substrate 12 (such as FR4, PI or similar dielectric material).Through hole is positioned at every side (4 side) of assembly 10 with the form of 3 row.Internal rows and outside provisional capital have 13 PTH, and in the middle of each, row has 14 PTH.The whole footprints 18 meeting general plated-through-hole design rule in this example is 6,7mm × 6,7mm.
Fig. 2 A-Fig. 2 I shows the first method for the manufacture of feedthrough conductor assembly according to the embodiment of the present invention.In Fig. 2 A-Fig. 2 I, institute's drawings attached all comprises the cross section, A-A of the vertical view of right-hand side and this vertical view of left-hand side ' cutaway view.
Fig. 2 A shows the panel 100 of feedthrough conductor assembly.Panel can be lamellated plate 100, such as stratiform printed circuit board (PCB).Lamellated plate 100 comprises core 102, and core 102 can be dielectric, and has conductive layer on the surface at two of dielectric core 102, i.e. top conductive layer 104 and bottom conductive layer 106.
According in the first method of embodiment, get through by modes such as brill, punching, Emission Lasers the hole that whole lamellated plate 100 forms feedthrough conductor 108A and 108B, as shown in Figure 2 B.
Fig. 2 C shows the coating of feedthrough conductor.After the hole forming feedthrough conductor 108A and 108B, be coated with hole with electric conducting material 110.Complete being coated with of hole in the following way: make electric conducting material 110 cover all Free Surfaces of lamellated plate 100 and the surface of hole 108A and 108B.After process for plating completes, hole is coated with 112A and 112B electric conducting material 110.Electroless process such as can be used to complete above-mentioned being coated with.
Fig. 2 D shows and form the state that light limits mask on two surface 114 and 116 of lamellated plate 100.It can be positive or negative that light limits mask.Because those skilled in the art understand the difference of both, therefore this patent is not introduced it in disclosing.
Fig. 2 E shows the state light being positioned at mask desired location 118 place being limited mask 114 and 116 exposure.In this embodiment, erect image exposure technology is employed.This means, the light beyond exposure area 118 limits mask 114 and 116 and will stay the position of practical wiring pattern 120A and 120B of lamellated plate 100.
Fig. 2 F shows dissolving 119 light and limits the state of mask 114 and 116 away from desired location 118, and the light now only retained on the surface at practical wiring pattern 120A and 120B place limits mask.
Fig. 2 G shows the state of the conductive surface by such as etching removal 111 desired location place.
Fig. 2 H show stripping 115 and 117 lamellated plate 100 two on the surface unexposed light limit the state of mask.Removing the middle part of lamellated plate by such as engraving milling line 126, in the middle part of this, comprising the half-sum dielectric 124 that plated-through-hole 123A is vertical with 123B.The remainder of feedthrough conductor comprises: dielectric core 125, conductor 122A and 122B that dielectric top surface extends, conductor 132A and 132B that dielectric basal surface extends and feedthrough conductor 112A and 112B vertically extended between dielectric 125 top surface and basal surface.
Fig. 2 I shows and engraves to plated-through-hole the state that milling 126 proceeds to halfway point place.Milling machine can be engraved by machinery or laser to complete and engrave milling.After this state, feedthrough conductor assembly 100 is ready to be assembled together with the semiconductor subassembly embedded.
Fig. 3 A shows the cross section view of the parts needed for the electronic module 2 of the embodiment of the present invention and the layer manufactured by first party method.Electronic module 2 comprises with lower component and layer:
● the feedthrough conductor assembly 100 that manufactures of the first method described by Fig. 2 A-Fig. 2 I, comprises the first wiring layer 122 and the second wiring layer 132 and the feedthrough conductor 112 between the first wiring layer 122 and the second wiring layer 132;
● comprise the prepackage part 150 of assembly 20, the 3rd wiring layer 142 that assembly 20 is positioned at patterning is electrically connected with the 3rd wiring layer 142 via micro-via hole 153;
● be positioned at the 4th wiring layer 144 at top wiring layer place;
● micro-via hole connector 152A and 152B, mainly between the first wiring layer 122 and the 4th wiring layer 144 and between the second wiring layer 132 and the 3rd wiring layer 142;
● insulation material layer 156A and 156B;
● passivation/solder mask 158A and 158B;
● solder ball 160.
Prepackage part 150 can be formed in every way.It is US6 that these method and structures (and their parts of at least some) are mainly described in U.S. Patent number, 991, 966, US7, 294, 529, US7, 299, 546, US7, 609, 527, US7, 663, 215, US7, 673, 387, US7, 696, 005 and U.S. Patent Application No. be US11/797, 609, US11/878, 557, US12/603, 324, US11/570, 673, US11/667, 429, US11/791, 547, US11/587, 586, US11/917, 724, US11/917, 711, US11/917, 737, US12/293, 412, US12/506, 519, US12/420, 617 and US12/546, in 454, it is incorporated into this by quoting.
Fig. 3 B shows the cross section view of the electronic module 2 made, and this module 2 made comprises the feedthrough conductor assembly 100 according to the embodiment of the present invention manufactured by first party method.Feedthrough conductor assembly 100 is positioned at the centre position of electronic module encapsulation 2 substantially.Electronic module 2 comprises the embedded components 20 being connected to the 3rd wiring layer 142 by micro-via hole 153.4th wiring layer 144 also can comprise functional parts 145, such as EMI shielding or ground.Embedded components 20 other all side except the 3rd wiring layer 142 by insulating material such as solidify prepreg (curedprepreglayer) 156 around.
Fig. 4 A-4J shows the second method according to the manufacture feedthrough conductor of the embodiment of the present invention.In Fig. 4 A-Fig. 4 I, institute's drawings attached all comprises the cross section, A-A of the vertical view of right-hand side and this vertical view of left-hand side ' cutaway view.
Fig. 4 A shows the panel 200 of feedthrough conductor assembly.Panel can be lamellated plate 200, such as stratiform printed circuit board (PCB).Lamellated plate 200 comprises core 202, and core 202 can be dielectric, and has conductive layer on the surface at two of dielectric core 202, i.e. top conductive layer 204 and bottom conductive layer 206.
According in the second method of embodiment, get through by modes such as brill, punching, Emission Lasers the hole that whole lamellated plate 200 forms feedthrough conductor 208A and 208B, as shown in Figure 4 B.
Fig. 4 C shows the coating of feedthrough conductor.After the hole forming feedthrough conductor 208A and 208B, be coated with hole with electric conducting material 210.Complete being coated with of hole in the following way: make electric conducting material 210 cover all Free Surfaces of lamellated plate 200 and the surface of hole 208A and 208B.After process for plating completes, hole is coated with 212A and 212B electric conducting material 210.Electroless process such as can be used to complete above-mentioned being coated with.
Fig. 4 D shows by insulating material 213A and 213B filling plated hole 208A and 208B.The filler of filling can be such as permanent or lasting rabbet ink, and it can engraved milling machine mill off afterwards.Insulating material 213A and 213B can build the conductor narrower than through hole 208A and 208B got out.
Two surfaces 214 and 216 that Fig. 4 E is presented at lamellated plate 200 form light and limits the state of mask.It can be positive or negative that light limits mask.Because those skilled in the art understand the difference of both, therefore this patent is not introduced it in disclosing.
Fig. 4 F shows the state light being positioned at mask desired location 218 place being limited mask 214 and 216 exposure.In this embodiment, erect image exposure technology is employed.This means, the light beyond exposure area 218 limits mask 214 and 216 and will stay the position of practical wiring pattern 220A and 220B of lamellated plate 200.
Fig. 4 G shows dissolving 219 light and limits the state of mask 214 and 216 away from desired location 218, and the light now only retained on the surface at practical wiring pattern 220A and 220B place limits mask.
Fig. 4 H shows the state of the conductive surface by such as etching removal 211 desired location place.
Fig. 4 I show stripping 215 and 217 lamellated plate 200 two on the surface unexposed light limit the state of mask.The middle part of lamellated plate is removed, the vertical half of insulating material 213A with 213B comprising filling in the middle part of this and plated-through-hole 223A and 223B and dielectric 224 by such as engraving milling line 226.The remainder of feedthrough conductor comprises: dielectric core 225, conductor 222A and 222B that dielectric top surface extends, conductor 232A and 232B that dielectric basal surface extends and feedthrough conductor 212A and 212B vertically extended between dielectric top surface and basal surface.Insulating material 213A and 213B that this feedthrough conductor 212A and 212B is filled covers.
Fig. 4 J shows and engraves to plated-through-hole the state that milling 226 proceeds to halfway point place.Milling machine can be engraved by machinery or laser to complete and engrave milling.After this state, feedthrough conductor assembly 200 is ready to be assembled together with the semiconductor subassembly embedded.
Fig. 5 A shows the cross section view of the parts needed for the electronic module 3 and layer manufactured by second party method according to the embodiment of the present invention.Electronic module 3 comprises with lower component and layer:
● the feedthrough conductor assembly 200 that the second method described by Fig. 4 A-Fig. 4 J is manufactured, comprise the first wiring layer 222 and the second wiring layer 232 and the feedthrough conductor 212 between the first wiring layer 222 and the second wiring layer 232, the dielectric material block 213 that this feedthrough conductor 212 is filled covers;
● comprise the prepackage part 250 of assembly 20, the 3rd wiring layer 242 that assembly 20 is positioned at patterning is electrically connected with the 3rd wiring layer 242 via micro-via hole 253;
● be positioned at the 4th wiring layer 244 at top wiring layer place;
● micro-via hole connector 252A and 252B, mainly between the first wiring layer 222 and the 4th wiring layer 244 and between the second wiring layer 232 and the 3rd wiring layer 242;
● insulation material layer 256A and 256B;
● passivation/solder mask 258A and 258B;
● solder ball 260.
Prepackage part 250 can be formed, in every way see description and Fig. 3 A of the first embodiment.
Fig. 5 B shows the cross section view of the electronic module 3 made, and this module 3 made comprises the feedthrough conductor assembly 200 manufactured by second party method according to the embodiment of the present invention.Feedthrough conductor assembly 200 is positioned at the centre position of electronic module encapsulation 3 substantially.Electronic module 3 comprises the embedded components 30 being connected to the 3rd wiring layer 242 by micro-via hole 253.4th wiring layer 244 also can comprise functional parts 245, such as EMI shielding or ground.Embedded components 30 other all side except the 3rd wiring layer 242 by insulating material such as solidify prepreg 256 around.
Fig. 6 A-6I shows the third method according to the manufacture feedthrough conductor of the embodiment of the present invention.In Fig. 6 A-Fig. 6 I, institute's drawings attached all comprises the cross section, A-A of the vertical view of right-hand side and this vertical view of left-hand side ' cutaway view.
Fig. 6 A shows the panel 300 of feedthrough conductor assembly.Panel can be lamellated plate 300, such as stratiform printed circuit board (PCB).Lamellated plate 300 comprises core 302, and core 302 can be dielectric, and has conductive layer on the surface at two of dielectric core 302, i.e. top conductive layer 304 and bottom conductive layer 306.
According in the third method of embodiment, get through whole lamellated plate 300 by modes such as brill, punching, Emission Lasers and form the assembly 40 for embedding and the hole 308 for feedthrough conductor, as shown in Figure 6B.
Being coated with of Fig. 6 C show hole 308.Similarly be coated with conductive layer 304 and 306 with electric conducting material 310.After process for plating, be coated with 312 holes 308 with electric conducting material 310.Electroless process such as can be used to complete above-mentioned being coated with.
Fig. 6 D shows and form the state that light limits mask on two surface 314 and 316 of lamellated plate 300.It can be positive or negative that light limits mask.Because those skilled in the art understand the difference of both, therefore this patent is not introduced it in disclosing.
Fig. 6 E shows the state light being positioned at mask desired location 318 place being limited mask 314 and 316 exposure.In this embodiment, erect image exposure technology is employed.This means, the light beyond exposure area 318 limits mask 314 and 316 and will stay the position of the practical wiring pattern 320 of lamellated plate 300.
Fig. 6 F shows dissolving 319 light and limits the state of mask 314 and 316 away from desired location 318, and the light be now only retained on the surface at practical wiring pattern 320 place limits mask.
Fig. 6 G shows the state of the conductive surface by such as etching removal 311 desired location place.
Fig. 6 H show stripping 315 and 317 lamellated plate 300 two on the surface unexposed light limit the state of mask.After lift-off, the hole 308 being evenly coated with 312 is presented on below unexposed light restriction mask.Side leftward, cuts out opening 328 afterwards without any need for feedthrough conductor.At right-hand side, need feedthrough conductor 312.Lamellated plate 300 comprises: dielectric core 325, the conductor 322 that the top surface of dielectric 325 extends, the conductor 332 that the basal surface of dielectric 325 extends and the feedthrough conductor 312 vertically extended between dielectric top surface and basal surface.
Fig. 6 I shows the opening 328 by being formed in the hole 308 being evenly coated with 312 and forms the state of 326 feedthrough conductors 312 in desired location.326 openings 328 are formed by brill, the mode such as milling, Emission Lasers of engraving.After this state, feedthrough conductor assembly 300 is ready to be assembled together with the semiconductor subassembly embedded.
Fig. 7 A shows the cross section view of the parts needed for the electronic module 4 of the embodiment of the present invention and the layer manufactured by third method.Electronic module 4 comprises with lower component and layer:
● the feedthrough conductor assembly 300 that manufactures of third method described by Fig. 6 A-Fig. 6 I, comprises the first wiring layer 322 and the second wiring layer 332 and the feedthrough conductor 312 between the first wiring layer 322 and the second wiring layer 332;
● comprise the prepackage part 350 of assembly 40, the 3rd wiring layer 342 that assembly 40 is positioned at patterning is electrically connected with the 3rd wiring layer 342 via micro-via hole 353;
● be positioned at the 4th wiring layer 344 at top wiring layer place;
● micro-via hole connector 352A and 352B, mainly between the first wiring layer 322 and the 4th wiring layer 344 and between the second wiring layer 332 and the 3rd wiring layer 342;
● insulation material layer 356A and 356B;
● passivation/solder mask 358A and 358B;
● solder ball 360.
Prepackage part 350 can be formed, in every way see description and Fig. 3 A of the first embodiment.
Fig. 7 B shows the cross section view of the electronic module 4 made, and this module 4 made comprises the feedthrough conductor assembly 300 according to the embodiment of the present invention manufactured by third method.Feedthrough conductor assembly 300 is positioned at the centre position of electronic module encapsulation 4 substantially.Electronic module 4 comprises the embedded components 40 being connected to the 3rd wiring layer 342 by micro-via hole 353.4th wiring layer 344 also can comprise functional parts 345, such as EMI shielding or ground.Embedded components 40 other all side except the 3rd wiring layer 342 by insulating material such as solidify prepreg 356 around.
Fig. 8 A shows the diagrammatic top view according to two plated through holes 14 of prior art.A general space W (PTH) needing 300 μm of plated through holes 14, for bonding pad L (PTH) 15 (general radius is 75 μm) and for actual apertures D (PTH) 16 (general diameter is 150 μm).Free space S (PTH) 17A at the general needs of plated-through-hole 14 and 50 μm, next through hole interval.Same size (S (PTH)) is also used on conductor 17B that wiring layer extends.Therefore, the pitch 13 (pitch (PTH)) of plated-through-hole is generally 350 μm, is approximately 350 μm × 350 μm by the area 19 needed for a contact of dielectric layer.
Fig. 8 B shows the vertical view of two feedthrough conductors according to a first embodiment of the present invention.According to the first embodiment of the present invention, plated-through-hole will be divided into two halves.The space W (E1) 28 of feedthrough conductor, the general needs 150 μm of the plated-through-hole 24 of namely separating, for bonding pad L (E1) 25 (general radius is 75 μm) and for actual apertures D (E1) 26 (general diameter is 150 μm).Free space S (E1) 27A at the general needs of plated-through-hole 24 and next 50 μm, through hole interval separated.Same size (S (E1)) is also used on conductor 27B that wiring layer extends.Therefore, the pitch 23 (pitch (E1)) of the plated-through-hole of separating is generally 350 μm, and the area 29 needed for a feedthrough conductor is according to a first embodiment of the present invention about 350 μm × 200 μm.Therefore, compared with prior art, the area 29 needed for feedthrough conductor is reduced to half by the first embodiment of the present invention.
Fig. 8 C shows the vertical view of three feedthrough conductors according to a second embodiment of the present invention.According to a second embodiment of the present invention, a general space W (E2) 38 needing 75 μm of feedthrough conductor 34.Due to without any need for bonding pad, Attention question is therefore only answered to be actual apertures D (E2) 36 (general diameter is 100 μm).Second embodiment of feedthrough conductor 34 generally needs the free space S (E2) 37 with next feedthrough conductor separation 100 μm.Because the width of free space 37 is enough, therefore do not need any size of the conductor size (27B) being similar to the first embodiment.Therefore, the pitch 33 (pitch (E2)) of feedthrough conductor is generally 200 μm and the area 39 needed for a feedthrough conductor is according to a second embodiment of the present invention approximately 200 μm × 75 μm.Therefore, compared with prior art, the area 39 needed for feedthrough conductor is reduced 85% by the second embodiment of the present invention.
Fig. 8 D shows the vertical view of three feedthrough conductors according to a third embodiment of the present invention.According to the third embodiment of the invention, a general space W (E3) 48 needing 90 μm of feedthrough conductor 44.Space W (E3) 48 comprises general value to be the vertical conductor 41 (it corresponds to the Reference numeral 312 in such as Fig. 6 I and Fig. 7 B) of 15 μm and the general value that extends on the top surface or basal surface of dielectric 42 the be conductor (it is corresponding to the Reference numeral 322 and 332 in such as Fig. 6 I and Fig. 7 B) of 75 μm.Therefore, the gross space W (E3) 48 needed for feedthrough conductor is generally 90 μm.The feedthrough conductor 44 of the 3rd embodiment does not need the free space of any type similar with previous embodiment.Only need to make opening be formed in the required all positions that there is not conductor 41 and 42 (it corresponds to the Reference numeral 312,322 and 332 in such as Fig. 6 I and Fig. 7 B).In this embodiment, drill through feedthrough conductor assembly to form hole 46, to form opening and to make feedthrough conductor be separated from each other.In addition, the pitch 43 (pitch (E3)) of feedthrough conductor is generally 150 μm and the area 49 needed for a feedthrough conductor is according to a third embodiment of the present invention approximately 150 μm × 90 μm.Therefore, compared with prior art, the area 49 needed for feedthrough conductor is almost reduced 90% by the third embodiment of the present invention.
Fig. 8 E shows the vertical view of eight feedthrough conductors according to another the 3rd embodiment improved of the present invention.According to the 3rd embodiment of improvement of the present invention, a general space W (E4) 58 needing 50 μm of feedthrough conductor 54.Space W (E4) 58 comprises general value to be the vertical conductor 51 (it corresponds to the Reference numeral 312 in such as Fig. 6 I and Fig. 7 B) of 15 μm and the general value that extends on the top surface or basal surface of dielectric 42 the be conductor (it is corresponding to the Reference numeral 322 and 332 in such as Fig. 6 I and Fig. 7 B) of 35 μm.Therefore, the gross space W (E4) 58 needed for feedthrough conductor is generally 50 μm.3rd embodiment of the feedthrough conductor 54 improved does not need the free space of any type similar with the first and second embodiments.Only need to make opening be formed in the required all positions that there is not conductor 41 and 42 (it corresponds to the Reference numeral 312,322 and 332 in such as Fig. 6 I and Fig. 7 B).In this embodiment, drill through feedthrough conductor assembly to form hole 56, to form opening and to make feedthrough conductor be separated from each other.In addition, the pitch 53 (pitch (E4)) of feedthrough conductor is generally 70 μm and the area 59 needed for a feedthrough conductor is according to a third embodiment of the present invention approximately 70 μm × 50 μm.Therefore, compared with prior art, the area 59 needed for feedthrough conductor is reduced 97% by the third embodiment of the present invention.It should be noted that Fig. 8 A, Fig. 8 B, Fig. 8 C, Fig. 8 D and Fig. 8 E are that equal proportion is drawn.
In institute's drawings attached of Fig. 9 A-Fig. 9 E, Reference numeral is identical.Which show dissimilar feedthrough conductor 64.In an embodiment, the conductor (it corresponds to the Reference numeral 322 and 332 in such as Fig. 6 I and Fig. 7 B) that the gross space 68 needed for feedthrough conductor comprises vertical conductor parts 61 (it corresponds to the Reference numeral 312 in such as Fig. 6 I and Fig. 7 B) and extends on the top surface or basal surface part of dielectric 62.Engrave milling or bore mode to the vertical conductor opening be evenly coated with by machinery, form vertical conductor separately.By the distance of conductor selecting to extend on dielectric top surface and basal surface part, the width of line 67 and/or space 69 and boring or the diameter engraving milling tool 66, the pitch 63 of feedthrough conductor 64 can be changed.
Fig. 9 A shows the example that the feedthrough conductor according to a third embodiment of the present invention that milling becomes engraved by machinery.Such as, the centre position of the conductor dielectric top surface and basal surface part extended completes general machinery and engraves milling to form opening in vertical conductor parts 61.What in Fig. 9 D, show that another kind meets L-type feedthrough conductor engraves milling.Engrave in milling mode existing, the general value of live width 67 is about 50 μm, and space is about 150 μm.In the embodiment improved, corresponding value is such as 40 μm and 100 μm.The pitch 63 of general embodiment is about 200 μm, and the embodiment of improvement is 140 μm.
Fig. 9 B shows the example of the feedthrough conductor according to a third embodiment of the present invention that machine drilling is made.Such as, the centre position of the conductor dielectric top surface and basal surface part extended completes general machine drilling to form opening in vertical conductor parts 61.The example of the feedthrough conductor according to a third embodiment of the present invention that the machine drilling that Fig. 9 C shows improvement is made.Show the improvement boring that another kind meets L-type feedthrough conductor in fig. 9e.In existing bore mode, the general value of live width 67 is about 50 μm, and space is about 100-150 μm.In the embodiment improved, corresponding value is such as 40 μm and 75 μm.The pitch 63 of general embodiment is about 150-200 μm, and the embodiment of improvement is 115 μm.
In institute's drawings attached of Figure 10 A-Figure 10 E, Reference numeral is identical.Which show dissimilar feedthrough conductor 74.In an embodiment, the conductor (it corresponds to the Reference numeral 322 and 332 in such as Fig. 6 I and Fig. 7 B) that the gross space 78 needed for feedthrough conductor comprises vertical conductor parts 71 (it corresponds to the Reference numeral 312 in such as Fig. 6 I and Fig. 7 B) and extends on the top surface or basal surface part of dielectric 72.By laser drill mode to the vertical conductor opening be evenly coated with, form vertical conductor separately.By the beam diameter of the distance of conductor selecting to extend on dielectric top surface and basal surface part, the width of line 77 and/or space 79 and laser drilling tool 76, the pitch 73 of feedthrough conductor 74 can be changed.In institute's drawings attached of Figure 10 A-Figure 10 E, also show combination feedthrough conductor 75, do not separate conductor in this position.This also makes the design for the electronic module according to the embodiment of the present invention have the larger degree of freedom.
Figure 10 A shows the example of the feedthrough conductor according to a third embodiment of the present invention that laser drill is made.Such as, the centre position of the conductor dielectric top surface and basal surface part extended completes general laser drill to form opening in vertical conductor parts 71.Figure 10 B shows the example that laser engraves milling feedthrough conductor according to a third embodiment of the present invention.The example of milling is engraved in Figure 10 C display to the laser that feedthrough conductor according to a third embodiment of the present invention improves.Figure 10 D shows the example of the feedthrough conductor of the third embodiment of the invention made according to the laser drill improved.Another example of the feedthrough conductor according to a third embodiment of the present invention that the laser drill (twice brill punching) that Figure 10 E shows improvement is made.In existing laser drill mode, the general value of live width 67 is about 50 μm, and space is about 75 μm.In the embodiment improved, corresponding value is such as 40 μm and 30 μm.The pitch 63 of general embodiment is about 125 μm, and the embodiment of improvement is 70 μm.
Figure 11 shows the electronic module 5 according to the embodiment of the present invention manufactured by third method.In fig. 11, on dielectric 502, can find the dielectric 502 of feedthrough conductor assembly, vertical conductor 512, extend conductor 522, opening 528 and combined conductor 542, it may be used for different objects, such as interconnection vias (interconnectrouting), EMI shielding or ground.
A series of shown in Figure 12 diagrammatically show according to according to the present invention a kind of may technique.Below, the technique of Figure 12 is detected stage by stage:
Stage A (Figure 12 A):
At stage A, select suitable substrate 1001 for circuit board manufacturing process.Substrate 1001 can be such as glass fiber reinforced epoxy resin plate, such as FR4 template.Because case process does not need high temperature, therefore in case process, substrate 1001 can be organic plates.Therefore can select flexibility and cheap organic plates for substrate 1001.Usually, the plate being coated with electric conducting material 1002 (normally copper) is selected to be used for substrate 1001.Certainly, also inorganic board can be used.
Stage B (Figure 12 B)
At stage B, form through hole 1003 in a substrate for electrical contact.Such as form through hole 1003 with the known method adopted in some circuit board manufacturing process (as machine drilling).
Stage C (Figure 12 C)
At stage C, grow in the through hole that metal is formed at stage B.In case process, also at the grown on top metal 1004 of circuit board, therefore too increase the thickness of conductive layer 1002.
The electric conducting material 1004 grown be copper or some other there is the material of enough conductivity.Copper metallization is carried out by then using electrochemical copper growth method to continue plating with very thin one deck chemical copper coating hole.Chemical copper is used to be because it also will occur that (surface) is used as electric conductor on the top of polymer and when electrochemistry plating in this example.Therefore, wet chemical method growing metal can be used, thus this growth is cheap.Alternatively, can such as by manufacturing conductive layer 1004 with conductive paste filling vias.
Stage D (Figure 12 D)
At stage D, by the conductive layer pattern on circuit board surface.This can utilize generally known method of manufacturing circuit board.The patterning of conductive layer is such as aimed at the hole formed at stage B.
Such as can manufacturing conductive pattern by photolithographic polymer film stacked on the surface of metal 1004, on this photolithographic polymer film, forming required conductive pattern by pattern mask by guiding light.After exposition, polymer film is developed, now the polymer film of desired zone is removed and the copper 1004 exposed below polymer.Then, the copper exposed below film is etched away, leave required conductive pattern.Polymer is used as so-called etching mask, and forms opening 1005 in metal level 1004, exposes the substrate of circuit board in the bottom of opening 1005.After this, polymer film is also removed from the top of copper 1004.
Stage E (Figure 12 E)
At stage E, form hole 1006 in a substrate for microcircuit.Hole extends through whole substrate from first surface 1001a and arrives second surface 1001b.Such as can carry out manufacturing hole by the milling of milling machine machinery.Hole 1006 can also such as be manufactured by punching press.Hole 1006 is aimed at relative to the conductive pattern 1004 of circuit board.The hole 1003 manufactured during stage B can also be used to auxiliary aligning, and this aligning is also relative to conductive pattern 1004, because conductive pattern 1004 has ad-hoc location relative to hole 1003.
Stage F (Figure 12 F)
At stage F, on the second surface of substrate and above hole 1006, manufacture the polymer film 1007 for the formation of electric insulation.Polymer film 1007 manufactures by this way: it is enough hard keeping the principal character of its shape but be not sclerosis, thus can be attached in film by assembly by press component.Polymer film also should be enough hard so that the assembly in press-in film can be made substantially to keep motionless at ensuing operation stage relative to substrate.
The polymer film manufactured at stage F can be such as pre-preg type film.
If needed, also metal coating 1008 can be formed at the top of polymer film 1007 at stage F.
In case process, carry out stage F by laminated thin thin polymer film on the surface of circuit board (such as about 40 μm), the top of this thin polymer film has layers of copper (such as about 5 μm).Carry out stacked by means of pressure and heat.In case process, therefore film is RCC (copper of resinizing) paper tinsel.And, not exclusively with carrying out must carry out that this is stacked, thus make polymer cokey.This is by setting stacked temperature enough low and/or realizing by shortening the heat treated duration.
Stage G (Figure 12 G)
At stage G, from the first surface 1001a side of substrate, microcircuit 18 is assemblied in hole 1006.Accurate assembly machine can be used to assemble, and microcircuit 18 is aimed at relative to the conductive pattern of circuit board.As stage E, aligning is assisted in the hole that can be used in stage B formation.
Microcircuit 18 is assembled in the mode of the polymer film 1007 adhered in " bottom " in hole 1006 by microcircuit 18.Optimal assembling mode uses such power: to be shifted onto slightly by microcircuit 18 in polymer film 1007 thus to make microcircuit better stay appropriate location.If the microcircuit be assembled has the contact projection 1009 penetrating polymer film 1007 inside, be more favourable for technique.
Figure 14 shows the alternate embodiment attracted people's attention, and wherein the contact projection 1009 of microcircuit 1018 is grown thus just extended through polymer film 1007 and arrives metal coating 1008 very much.In the case, do not need in polymer film 1007, form through hole (stage K) and in microcircuit, form contact, because hole shape becomes relevant with the assembling of assembly.In addition, the metalization level (stage L) in hole can be simplified, because contact projection 1009 forms the conductor pin through polymer film 1007 automatically.In the embodiment of Figure 14, contact projection also can be made to be sharp-pointed shape, thus to improve its penetration capacity.If contact projection 1009 long enough and sharp-pointed, they also can penetrating metal coating 1008 and the electrical contact formed substantially between microcircuit 18 and metal coating 1008.
Stage H (not shown)
At stage H, by solidification, polymer film 1007 is hardened.Solidification generally includes heat treatment, but this technique can also adopt other processing methods in addition to heating by polymer hardens.If needed, also can omitting stage H, especially omitting the step relevant to passing through heat treatment for solidification polymer.But can prevent microcircuit from moving relative to substrate during stage I polymer hardens in this stage.
Stage I (Figure 12 H)
At stage I, by being filled to the hole that microcircuit is formed with packing material 1010, microcircuit is fixed on the substrate of circuit board.In case process, by the epoxy resin of cast to be applied to hole and this stage is carried out at the top being applied to microcircuit from the first surface (1001a) of circuit board.With the floating epoxy resin of scraper, and make this epoxy cure by solidification in autoclave (autoclave).If technique does not comprise stage H, then polymer film 1007 is also hardened at this moment.
Stage J (Figure 12 I)
At stage J, at first surface (1001a) the upper formation polymer film 1011 of circuit board, then on the top of polymer film, form thin metal coating 1012.
In case process, carry out stage J by the polymer film (such as about 40 μm) of laminated thin on the surface of circuit board, the top of this polymer film has layers of copper (such as about 5 μm).Carry out stacked by means of pressure and heat.In case process, therefore film is RCC (copper of resinizing) paper tinsel.
Can also by such as the polymer-coated of liquid form being manufactured polymer film on circuit boards.Therefore not necessarily stacked at stage J.Necessarily manufacture insulating barrier on circuit boards, be generally polymer film, this insulating barrier comprises embedded components, especially embeds microcircuit.According to embodiment, polymer film itself can be filled polymeric membranes or non-filled polymeric membranes.Polymer film can also be coated with metal, but this not necessarily, because also will form conductive surface on the top of polymeric layer being attached to circuit board afterwards.
The working stage that stage J can use traditional manufacture method and use in the circuit board fabrication process of case process, but microcircuit and other assembly can be imbedded in circuit board.
Stage K (Figure 12 J)
At stage K, in polymer film 1007 and 1011 (simultaneously at conductive foil 1008 and 1012), form hole 1013, can with the conductive pattern of circuit board with feedthrough (electric conducting material 1004) and contact with microcircuit by this hole 1013.
Laser or some other suitable method can be such as used to form hole 1013.Stage D formed conductive pattern or stage B formed through hole may be used for aim at.
Stage L (Figure 12 K)
Stage L corresponds to stage C.At stage L, in hole 1013 and on the surface of circuit board, form conductive layer 1014.
In case process, the decontamination process of three stages is first used to clean feedthrough (hole 1013).After this, then thin chemical layers of copper (about 2FmVAI2 micron) is deposited on the surface by forming catalysis SnPd surface first on polymer.The thickness of copper 1014 is increased by electrochemical deposition.
Alternatively, with conductive paste fill feedthrough or use some other suitable micro-via metal method to form feedthrough.
Stage M (Figure 12 L)
At stage M, form conductive pattern in the mode identical with stage D.
Stage N and O (Figure 12 M and 12N)
At stage N and O, the surface of circuit board is coated with photolithographic polymer 1015 and in polymer 1015, forms required pattern (mode with similar with stage D and M).By the development of the polymer film of exposure, but the polymer film pattern retained on circuit boards is not removed.
Stage P (Figure 12 O)
At stage P, coating 1016 is at the join domain of the polymer film pattern of formation previous stage.Coating 1016 can be formed with such as Ni/Au coating or OSP (organic surface protection).
The example delineation of Figure 12 can be used to realize a technique of the present invention.But the present invention is never limited to above-mentioned technique, the gamut interior also permission equivalence that the present invention makes a different set of technique and end product thereof cover claims is on the contrary explained.More specifically, the present invention is never limited to the layout shown in example, it will be apparent to one skilled in the art that technique according to the present invention may be used for manufacturing the very not identical circuit board of multiple and disclosed herein example on the contrary.Therefore, the microcircuit in figure and connector are only depicted as and are illustrated manufacturing process.
Multiple change can be made to above disclosed case process, and not depart from according to concept of the present invention.These changes can relate to the manufacturing technology of each stage description, or such as relate to the mutual order in stage.Such as, can after stage D execution phase B equivalently, namely step can be make boring aligned pattern instead of make pattern aim at boring.Correspondingly, the order of stage D and E also can be conversely.Then, before formation conductive pattern, component holes 1006 is formed.In the case, conductive pattern is aimed at relative to hole 1006 (also porose 1003).No matter the stage B, D, E execution sequence how, make polymer film 1007 coverage hole 1006 manufactured at stage F and the conductive pattern be formed on the second surface 1001b of substrate.
Think that the stage needed also can add in above disclosed case process.Such as, the paper tinsel carrying out protective circuit plate surface between casting cycle at stage H can be laminated on first side (1001a) of circuit board.Manufacturing this protective foil makes it cover other regions all except hole 1006.Protective foil is to make circuit board keep clean during doctor blade casting epoxy resin.The suitable stage before stage I can form protective foil, and after cast, immediately from the surface removal protective foil of circuit board.
By means of the method, the component package will be attached on circuit boards can also be manufactured.This encapsulation can also comprise several semiconductor subassembly be electrically connected to each other.
The method can also for the manufacture of whole electrical module.Can also apply the technique shown in Figure 12 as follows: only on second side (1001b) of circuit board, manufacture conductive structure, the contact surface of microcircuit is towards this second side.
The method can Production Example as circuit board or electronic module, wherein used substrate thickness is in 50-200 micrometer range, and the thickness of microcircuit is in 50-150 micrometer range.The pitch of conductor can change in the scope of such as 50-250 micron, and the diameter of micro-feedthrough can be such as 15-50 micron.Therefore, the gross thickness of the single plate of a Rotating fields will be about 100-300 micron.
The present invention can also be applied as follows: circuit board assembles in top of each other, thus form multilayer circuit structure, wherein be electrically connected to each other in top of each other according to several circuit board layout of Figure 12 manufacture.Arrange that circuit board on top of each other can also be such circuit board: conductive structure is only formed on the second side 1001b of circuit board, but it comprises feedthrough, can also be formed into the electrical contact of microcircuit by this conductive structure from the first side of circuit board.Figure 13 illustrates such a technique.
Figure 13 shows circuit board connection each other.Next, this technique is described stage by stage.Stage 2A (Figure 13 A)
Stage 2A describes layout circuit board on top of each other.Such as after the J stage of Figure 12 technique of change, undermost circuit board can be obtained.So in the case, revise the technique of Figure 12 by omitting stage 1C.
Such as after the M stage of Figure 12 technique of distortion, circuit board that is middle and upper strata can be obtained successively.In the case, by omitting stage 1C and only revising the technique of Figure 12 at the second side (1001b) upper execution phase J, K and L of circuit board.
Except circuit board, Figure 13 A also show the prepreg epoxy resin layer 1021 be placed between circuit board.
Stage 2B (Figure 13 B)
At stage 2B, by prepreg epoxy resin layer 1021, board layer is stacked.In addition, the epoxy resin film 1022 being covered with metal is formed on the upper surface of the circuit board.This technique corresponds to the stage J of the technique of Figure 12.In case process, this epoxy resin film 1022 being covered with metal has been positioned on the lower surface of circuit board.
Stage 2C (Figure 13 C)
At stage 2C, in order to form contact, drilling bore hole 1023 in the circuit board.
After stage 2C, such as, continue this technique as shown below:
Stage 2D
At stage 2D, in the mode similar with stage 1C, electric conducting material is grown on the top of circuit board and in through hole 1023.
Stage 2E
At stage 2E, with the similar mode of stage 1D by the conductive layer pattern on circuit board surface.Stage 2F
At stage 2F, with the similar mode of stage 1N and 1O by the surface of photolithographic polymer deposited traces plate and form required pattern in the polymer.The polymer film of exposure is developed, but does not remove the polymer film pattern stayed on circuit boards.
Stage 2G
At stage 2G, in the mode similar with stage 1P, the join domain of the polymer film pattern being formed in previous stage is metallized.
On the instance basis of Figure 13, obvious the method can also for the manufacture of multiple three-dimensional circuit structures.Such as the method can use as follows: several memory circuitry is placed on top of each other, thus form the encapsulation comprising several memory circuitry, wherein memory circuitry is connected to each other to be formed and runs overall (operationaltotality).The encapsulation in this module can be freely selected and easily contact can be formed between the chips according to selected circuit.
The present invention also allows the assembly embedded in substrate to carry out electromagnetic protection.This is because the method for Figure 12 can be modified as follows: the hole 1006 described in stage 1E can be relevant to the hole 1003 that formed in stage 1B and manufactured.In the case, the conductive layer 1004 formed at stage 1C also will be covered as the sidewall in the hole 1006 that assembly manufactures.Figure 15 A shows the cross section of underlying structure, and it is the state after the former stage F stating the technique that mode is revised.
Can also revise as follows this technique: after the sidewall being covered as the hole 1006 (this hole is also referred to as installation cavity) that assembly manufactures, such as, by boring, the covering in peripheral sidewalls is divided into parallel part.Then, the metal structure around semiconductor subassembly (IC) shown in Figure 15 D is divided into the several feedthrough conductors be connected with the layer 1004 on the first surface 1001a of dielectric substrate 1001 and second surface 1001b.Therefore, the structure of similar Fig. 5 B to Fig. 7 B can be manufactured by this technique.
After the interstage shown in Figure 15 A, can polymer film be hardened by assembling microcircuit in the mode similar with stage 1G, as stage 1H and be attached microcircuit similarly with stage 1I and continue this technique.After this, polymer and metal forming can be formed similarly on the first surface of circuit board with stage 1J.Figure 15 B illustrates the example cross-section of the underlying structure after these operation stages.
After the interstage shown in Figure 15 B, continue this technique by the hole manufactured in polymer film with being similar to stage 1K for the formation of contact.After this, be similar to stage 1L ground, in hole, form conductive layer on the surface with plate.Figure 15 C shows the example cross-section of the underlying structure after these technique.In order to clear, be similar to stage 1L in hole and the conductive layer that manufactures on the surface of plate highlight with black.
After the interstage shown in Figure 15 C, by as stage 1M over the surface of the panel patterned conductive layer, as stage 1N, this technique is continued on coated board surface.After these stages, by the metal forming of nearly continuity around microcircuit, this metal forming forms available protecting and makes it not by the interference that electromagnetic interaction causes.This structure shown in Figure 15 D.After the interstage shown in Figure 15 D, carry out corresponding to the stage that stage 1O and 1P manufactures protective foil and connector on the surface of circuit board.
In Figure 15 D, the cross section of the metal level of protection microcircuit highlights with black.In addition, the background of microcircuit highlights with crosshatch.All sides that crosshatch is intended to the hole prompting for microcircuit manufacture are covered by metal forming.Therefore, with continuous print metal forming side direction around microcircuit.In addition, metallic plate is designed on microcircuit, and the manufacture of metallic plate is relevant with the manufacture of circuit board conductive pattern.Similarly, below microcircuit, as far as possible intactly metal forming is formed.As shown in figure 15d, below microcircuit, such as form contact to mean and must form small―gap suture in metal forming.But these gaps can be laterally formed as very narrow or be correspondingly formed as Vertical dimension very thin, so that they can not weaken the protective effect of obtained opposing electromagnetic interference.
When checking the example of Figure 15 D, also must consider that final structure also comprises the parts extended in the mode that plane to that indicated in the drawings is at a right angle.This structure extended with right angle is shown by the conductor being connected to the contact salient point on the left-hand side being positioned at Figure 15 D left-hand side microcircuit, and it extends to observer between the conductive layer laterally below the metal forming and microcircuit of microcircuit.
Therefore the solution shown in Figure 15 D provides and has extraordinary protection to make it not by the microcircuit of electromagnetic interference.Owing to tightly forming protection around microcircuit, therefore this structure also protects it not by the interactive interference produced between the assembly comprised in circuit board.The all right ground connection of most of electromagnetic protective structure, because the horizontal metal forming around microcircuit can be electrically connected to the metallic plate above circuit.Can with the conductive structure by circuit board by the connection of the mode of metallic plate ground connection successively design circuit plate.
The electronic module of Figure 15 D comprise there is first surface and second surface dielectric 1031 substrate, extend through dielectric substrate and there is the installation cavity of peripheral sidewall between first surface and second surface.Electronic module also comprises the first wiring layer 1032 be arranged on the first surface of dielectric substrate, be arranged in the second wiring layer 1033 on the second surface of dielectric substrate and be positioned on installation cavity peripheral sidewall and by the feedthrough conductor 1034 of at least one conductor electrical connection of at least one conductor of the first wiring layer and the second wiring layer.Also there is at least one semiconductor subassembly IC being positioned at installation cavity inside at least in part.The 3rd wiring layer 1037 that electronic module also comprises the first insulating barrier 1035 be positioned on the second wiring layer, is positioned at the second insulating barrier 1036 on the first wiring layer and is positioned on this first insulating barrier.This electronic module also comprises at the first insulating barrier inner and make first micro-via hole 1038 of being electrically connected between the second wiring layer and the 3rd wiring layer.Electronic module also comprises the second micro-via hole 1039 at least one semiconductor subassembly being electrically connected at least one wiring layer in the second wiring layer and the 3rd wiring layer.According to Figure 15 D, electronic module also comprises the 4th wiring layer 1040 on the second insulating barrier and inner and make the 3rd micro-via hole 1041 of being electrically connected between the first wiring layer and the 4th wiring layer at the second insulating barrier.
As described above, the embodiment of the present invention has about electronic module, the described ground of such as Fig. 5 B or Figure 15 D, and it comprises:
Dielectric substrate 225,1031 (referring to the Reference numeral in Fig. 5 B and Figure 15 D respectively), has first surface and second surface;
Installation cavity, extends through dielectric substrate 225,1031 and have peripheral sidewall between first surface and second surface;
First wiring layer 222,1032, is positioned on the first surface of dielectric substrate 225,1031;
Second wiring layer 232,1033, is positioned on the second surface of dielectric substrate 225,1031;
Feedthrough conductor 212,1034, at least one conductor of the first wiring layer 222,1032 at least one conductor with the second wiring layer 232,1033 is electrically connected by the peripheral sidewall being arranged in installation cavity;
At least one semiconductor subassembly 30, IC, be positioned at installation cavity inside at least partly;
First insulating barrier ..., 1035, be positioned on the second wiring layer 232,1033;
Second insulating barrier ..., 1036, be positioned on the first wiring layer 222,1032;
3rd wiring layer 242,1037, is positioned at the first insulating barrier ..., on 1035;
First micro-via hole 252B, 1038, is positioned at the first insulating barrier ..., make to be electrically connected between the second wiring layer the 232,1033 and the 3rd wiring layer 242,1037 in 1035;
Second micro-via hole 253,1039, is electrically connected at least one semiconductor subassembly 30, IC with among the second wiring layer the 232,1033 and the 3rd wiring layer 242,1037;
4th wiring layer 244,1040, is positioned at the second insulating barrier ..., on 1036; And
3rd micro-via hole 252A, 1041, is positioned at the second insulating barrier ..., make to be electrically connected between the first wiring layer the 222,1032 and the 4th wiring layer 244,1040 in 1036.
In a further embodiment, this at least one semiconductor subassembly comprises at least two contact pads towards the second wiring layer, and at least some at least two contact pads is electrically connected to the second wiring layer by the micro-via hole of at least some second.
In a further embodiment, this at least one semiconductor subassembly comprises at least two contact pads towards the 3rd wiring layer, and at least some at least two contact pads is electrically connected to the 3rd wiring layer by the micro-via hole of at least some second.
In a further embodiment, electronic module also comprises the insulating material of the installation cavity of filling between peripheral sidewall and at least one semiconductor subassembly.
In a further embodiment, at least one conductor in 3rd wiring layer is connected at least one conductor in the 4th wiring layer by least one electric pathway, and this at least one electric pathway is through at least one first micro through hole, at least one conductor being arranged in the second wiring layer, at least one feedthrough conductor, at least one conductor being arranged in the first wiring layer and at least one the 3rd micro through hole.
In a further embodiment, feedthrough conductor is electrically connected, solderless connects and metallurgy is connected to the first wiring layer and the second wiring layer.
In a further embodiment, the 4th wiring layer limits conductive plate above the position of installation cavity and this at least one semiconductor subassembly.
In a further embodiment, feedthrough conductor covers the whole peripheral sidewall of installation cavity.
In a further embodiment:
4th wiring layer limits conductive plate above the position of installation cavity and this at least one semiconductor subassembly;
Feedthrough conductor covers the whole peripheral sidewall of installation cavity; And
Conductive plate and feedthrough conductor can be connected to earth potential to be formed above opposing semiconductor subassembly and the shielding of the electromagnetic interference of surrounding.
In a further embodiment, feedthrough conductor is divided into multiple part, thus on the peripheral sidewall of installation cavity, forming multiple feedthrough conductor, this feedthrough conductor makes the first wiring layer and the second wiring layer be electrically connected to each other by multiple independent power path (electricalroute).
Another embodiment is relevant with electronic module, and this electronic module comprises:
Dielectric substrate, has first surface and the second surface relative with first surface;
Installation cavity, extends through dielectric substrate and have peripheral sidewall between first surface and second surface;
First wiring layer, is positioned on the first surface of dielectric substrate;
Second wiring layer, is positioned on the second surface of dielectric substrate;
At least two feedthrough conductors, the peripheral sidewall being positioned at installation cavity makes the first wiring layer and the second wiring layer be electrically connected to each other by least two independent power paths;
First insulating barrier, is positioned on the second wiring layer;
3rd wiring layer, is positioned on the first insulating barrier;
At least one semiconductor subassembly, is positioned at installation cavity at least in part and comprises at least two contact pads towards the 3rd wiring layer;
First micro-via hole, makes to be electrically connected between the second wiring layer with the 3rd wiring layer in the first insulating barrier;
Second micro-via hole, is electrically connected to the 3rd wiring layer by least some contact pad of semiconductor subassembly;
Second insulating barrier, is positioned on the first wiring layer;
4th wiring layer, is positioned on the second insulating barrier;
3rd micro-via hole, makes to be electrically connected between the first wiring layer with the 4th wiring layer in the second insulating barrier.
In a further embodiment, further electronic module comprises the insulating material of the installation cavity of filling between peripheral sidewall and at least one semiconductor subassembly.
In a further embodiment, at least one conductor in 3rd wiring layer is connected at least one conductor in the 4th wiring layer by least one electric pathway, and this at least one electric pathway is through at least one conductor at least one conductor at least one first micro-via hole, the second wiring layer, at least one feedthrough conductor, the first wiring layer and at least one the 3rd micro-via hole.
In a further embodiment, feedthrough conductor is electrically connected, solderless connects and metallurgy is connected to the first wiring layer and the second wiring layer.
In a further embodiment, wherein
This at least one semiconductor subassembly comprises the contact pad towards the 3rd wiring layer;
These at least two feedthrough conductors comprise multiple feedthrough conductor;
Second wiring layer comprises multiple first conductor, and this first conductor limits contact area and at least some feedthrough conductor be connected to by described contact area in the plurality of feedthrough conductor;
3rd wiring layer comprises multiple second conductor, and this second conductor extends to the position of at least some contact area from the position of at least some contact pad;
This module also comprises first micro-via hole at least some contact area being electrically connected at least some second conductor in the 3rd wiring layer;
This module also comprises second micro-via hole at least some contact pad being electrically connected at least some second conductor in the 3rd wiring layer.
In a further embodiment, electronic module also comprises the electric insulation adhesive phase between semiconductor subassembly and the 3rd wiring layer; And this second micro-via hole at least two contact pads being electrically connected to the 3rd wiring layer is positioned at electric insulation adhesive phase.
In one embodiment, electronic module comprises:
Dielectric substrate, has first surface and the second surface relative with first surface;
Installation cavity, extends through dielectric substrate and have peripheral sidewall between first surface and second surface;
First wiring layer, is positioned on the first surface of dielectric substrate;
Second wiring layer, is positioned on the second surface of dielectric substrate;
At least two feedthrough conductors, the peripheral sidewall being positioned at installation cavity makes the first wiring layer and the second wiring layer be electrically connected to each other by least two independent power paths;
At least one semiconductor subassembly, is positioned at installation cavity at least in part.
In a further embodiment, electronic module also comprises the insulating material of the installation cavity of filling between peripheral sidewall and at least one semiconductor subassembly.
In a further embodiment, electronic module also comprises:
First insulating barrier, is positioned on the second wiring layer;
3rd wiring layer, is positioned on the first insulating barrier;
First micro-via hole, makes to be electrically connected between the second wiring layer and the 3rd wiring layer in the first insulating barrier.
In a further embodiment, this at least one semiconductor subassembly comprises towards at least two contact pads of the 3rd wiring layer; And this module also comprises the second micro-via hole at least two contact pads being electrically connected to the 3rd wiring layer.
In a further embodiment, electronic module also comprises:
Second insulating barrier, is positioned on the first wiring layer;
4th wiring layer, is positioned on the second insulating barrier; And
3rd micro-via hole, makes to be electrically connected between the first wiring layer and the 4th wiring layer in the second insulating barrier.
In a further embodiment, at least one conductor in 3rd wiring layer is connected at least one conductor in the 4th wiring layer by least one electric pathway, and this at least one electric pathway is through at least one first micro-via hole, at least one conductor being arranged in the second wiring layer, at least one feedthrough conductor, at least one conductor being arranged in the first wiring layer and at least one the 3rd micro-via hole.
In a further embodiment, feedthrough conductor is electrically connected, solderless connects and metallurgy is connected to the first wiring layer and the second wiring layer.
In a further embodiment, these at least two feedthrough conductors comprise multiple parallel feedthrough conductor, each feedthrough conductor has width and is interval in adjacent feedthrough conductor, make the pitch between described multiple conductor be less than 300 microns, wherein this pitch is defined as the width of single conductor and this single conductor and is adjacent interval sum between feedthrough conductor.
In a further embodiment, the pitch between described multiple conductor is less than 200 microns.
In a further embodiment, the pitch between described multiple conductor is less than 100 microns.
In a further embodiment:
At least one semiconductor subassembly comprises the contact pad towards the 3rd wiring layer;
At least two feedthrough conductors comprise multiple feedthrough conductor;
Second wiring layer comprises multiple first conductor, and this first conductor limits contact area and at least some feedthrough conductor be connected to by described contact area in the plurality of feedthrough conductor;
3rd wiring layer comprises multiple second conductor, and this second conductor extends to the position of at least some contact area from the position of at least some contact pad;
This module also comprises first micro-via hole at least some contact area being electrically connected at least some second conductor in the 3rd wiring layer;
This module also comprises second micro-via hole at least some contact pad being electrically connected at least some second conductor in the 3rd wiring layer.
In a further embodiment, electronic module also comprises the electric insulation adhesive phase between at least one semiconductor subassembly and the 3rd wiring layer; And this second micro-via hole at least two contact pads being electrically connected to the 3rd wiring layer is positioned at electric insulation adhesive phase.
In a further embodiment, the thickness of each feedthrough conductor from the peripheral sidewall of installation cavity is less than 20 microns.
According to further embodiment, a kind of semiconductor die package is provided, comprises:
Dielectric substrate, has first surface and the second surface relative with first surface;
Installation cavity, extends through the dielectric substrate between first surface and second surface and has the sidewall limiting described installation cavity;
At least one semiconductor chip, has the contact pad being positioned at installation cavity;
First wiring layer, is positioned on the first surface of dielectric substrate;
Second wiring layer, is positioned on the second surface of dielectric substrate;
Feedthrough conductor, the first wiring layer is electrically connected with the second wiring layer by the sidewall being positioned at installation cavity;
First insulating barrier, is positioned on the second wiring layer;
3rd wiring layer, is positioned on the first insulating barrier;
First micro-via hole, makes to be electrically connected between the second wiring layer with the 3rd wiring layer in the first insulating barrier; And
Second micro-via hole, is electrically connected to the 3rd wiring layer by least some contact pad of semiconductor chip.
In a further embodiment, semiconductor die package comprises:
Second insulating barrier, is positioned on the first wiring layer;
4th wiring layer, is positioned on the second insulating barrier; And
3rd micro-via hole, makes to be electrically connected between the first wiring layer with the 4th wiring layer in the second insulating barrier.
In a further embodiment, at least some contact pad of semiconductor chip is connected to the first wiring layer be positioned on dielectric substrate first surface by multiple electric pathway.
In a further embodiment, described multiple electric pathway is through at least one second micro-via hole, at least one conductor being arranged in the 3rd wiring layer, at least one first micro-via hole, at least one conductor being arranged in the second wiring layer and at least one feedthrough conductor.
The present invention also provides the manufacture method of electronic module.
According to embodiment, the manufacture method of electronic module comprises:
The dielectric substrate with first surface and second surface is provided;
Formed and extend through dielectric substrate and the installation cavity between first surface and second surface with peripheral sidewall;
The first surface of dielectric substrate is formed the first wiring layer;
The second surface of dielectric substrate is formed the second wiring layer;
The peripheral sidewall of installation cavity is formed at least one feedthrough conductor and at least one conductor in the first wiring layer is electrically connected at least one conductor in the second wiring layer;
At least one semiconductor subassembly is at least partially disposed in installation cavity;
Second wiring layer is formed the first insulating barrier;
First wiring layer is formed the second insulating barrier;
First insulating barrier forms the 3rd wiring layer;
In the first insulating barrier, form first micro-via hole and make to be electrically connected between the second wiring layer and the 3rd wiring layer;
At least one semiconductor subassembly is electrically connected at least one second micro-via hole in the second wiring layer and the 3rd wiring layer by formation;
Form the 4th wiring layer over the second dielectric; And
In the second insulating barrier, form the 3rd micro-via hole and make to be electrically connected between the first wiring layer and the 4th wiring layer.
In the further embodiment of the method, form copper facing on peripheral sidewall that at least one feedthrough conductor is included in installation cavity.
In the further embodiment of the method, form at least one feedthrough conductor and comprise all peripheral sidewalls covering installation cavity with metal.
In the further embodiment of the method, form at least one feedthrough conductor and comprise:
Plating on the sidewall of installation cavity; And
Metal is divided into multiple part, thus on the peripheral sidewall of installation cavity, forms multiple feedthrough conductor, this feedthrough conductor makes the first wiring layer and the second wiring layer be electrically connected to each other by multiple independent power path.
Another manufacture method of electronic module comprises:
The dielectric substrate with first surface and the second surface relative with first surface is provided;
Formed and extend through dielectric substrate and the installation cavity between first surface and second surface with peripheral sidewall;
The first surface of dielectric substrate is formed the first wiring layer;
The second surface of dielectric substrate is formed the second wiring layer;
The peripheral sidewall of installation cavity is formed at least two feedthrough conductors and by feedthrough conductor, the first wiring layer and the second wiring layer is electrically connected to each other; And
At least one semiconductor subassembly is at least partially disposed in installation cavity.
The another manufacture method of electronic module comprises:
The dielectric substrate with first surface and the second surface relative with first surface is provided;
Form at least two extend to second surface in dielectric substrate feed-through hole from first surface;
The first surface of dielectric substrate is formed the first wiring layer;
The second surface of dielectric substrate is formed the second wiring layer;
In feed-through hole, form at least two feedthrough conductors, this feedthrough conductor makes the first wiring layer and the second wiring layer be electrically connected to each other;
By cutting a part of dielectric substrate and a part of feed-through hole and feedthrough conductor, form the installation cavity through dielectric substrate, wherein installation cavity has peripheral sidewall between first surface and second surface, and the remainder of the feed-through hole after cutting forms a part for peripheral sidewall and the remainder of the feedthrough conductor after cutting is positioned on peripheral sidewall; And
At least one semiconductor subassembly is at least partially disposed in installation cavity.
More than describe to be only and illustrate the present invention and be not intended to limit the protection range provided by claim.Claim is also intended to cover equivalence of the present invention and do not answer literalization.

Claims (20)

1. an electronic module, comprising:
Dielectric substrate, has first surface and second surface;
Installation cavity, extends through this dielectric substrate and have peripheral sidewall between this first surface and this second surface;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
Feedthrough conductor, the peripheral sidewall being arranged in this installation cavity makes at least one conductor of this first wiring layer be electrically connected at least one conductor of this second wiring layer;
At least one semiconductor subassembly, is positioned at this installation cavity at least partly;
First insulating barrier, is positioned on this second wiring layer;
Second insulating barrier, is positioned on this first wiring layer;
3rd wiring layer, is positioned on this first insulating barrier;
First micro-via hole, makes to be electrically connected between this second wiring layer and the 3rd wiring layer in this first insulating barrier;
Second micro-via hole, is connected at least one in this second wiring layer and the 3rd wiring layer by this at least one semiconductor subassembly;
4th wiring layer, is positioned on this second insulating barrier; And
3rd micro-via hole, makes to be electrically connected between this first wiring layer and the 4th wiring layer in this second insulating barrier.
2. electronic module as claimed in claim 1, wherein this at least one semiconductor subassembly comprises at least two contact pads, and these at least two contact pads are towards this second wiring layer; And at least some contact pad in these at least two contact pads is electrically connected to this second wiring layer by this second micro-via hole of at least some.
3. electronic module as claimed in claim 1, wherein this at least one semiconductor subassembly comprises at least two contact pads, and these at least two contact pads are towards the 3rd wiring layer; And at least some contact pad in these at least two contact pads is electrically connected to the 3rd wiring layer by this second micro-via hole of at least some.
4. electronic module as claimed in claim 1, also comprises the insulating material of the installation cavity of filling between this peripheral sidewall and this at least one semiconductor subassembly.
5. electronic module as claimed in claim 1, wherein at least one conductor in the 3rd wiring layer is connected at least one conductor in the 4th wiring layer by least one electric pathway, and this at least one electric pathway is through at least one first micro-via hole, at least one conductor being arranged in the second wiring layer, at least one feedthrough conductor, at least one conductor being arranged in this first wiring layer and at least one the 3rd micro-via hole.
6. electronic module as claimed in claim 1, wherein the 4th wiring layer limits conductive plate above the position of this installation cavity and this at least one semiconductor subassembly.
7. electronic module as claimed in claim 1, wherein this feedthrough conductor covers the whole peripheral sidewall of this installation cavity.
8. electronic module as claimed in claim 1, wherein
4th wiring layer limits conductive plate above the position of this installation cavity and this at least one semiconductor subassembly;
This feedthrough conductor covers the whole peripheral sidewall of this installation cavity; And
This conductive plate and this feedthrough conductor can be connected to earth potential, to be formed above shielding opposing semiconductor subassembly and the electromagnetic interference of surrounding.
9. electronic module as claimed in claim 1, wherein this feedthrough conductor is divided into multiple part thus on the peripheral sidewall of this installation cavity, forms multiple feedthrough conductor, and this feedthrough conductor makes this first wiring layer and this second wiring layer be electrically connected to each other by multiple independent power path.
10. an electronic module, comprising:
Dielectric substrate, has first surface and the second surface relative with this first surface;
Installation cavity, extends through this dielectric substrate and have peripheral sidewall between this first surface and this second surface;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
At least two feedthrough conductors, the peripheral sidewall being positioned at this installation cavity makes this first wiring layer and this second wiring layer be connected to each other by least two independent power paths; And
At least one semiconductor subassembly, is positioned at this installation cavity at least partly.
11. electronic modules as claimed in claim 10, also comprise the insulating material of the installation cavity of filling between this peripheral sidewall and this at least one semiconductor subassembly.
12. electronic modules as claimed in claim 11, also comprise:
First insulating barrier, is positioned on this second wiring layer;
3rd wiring layer, is positioned on this first insulating barrier; And
First micro-via hole, makes to be electrically connected between this second wiring layer and the 3rd wiring layer in this first insulating barrier.
13. electronic modules as claimed in claim 12, wherein this at least one semiconductor subassembly comprises at least two contact pads, and these at least two contact pads are towards the 3rd wiring layer; And this module also comprises:
Second micro-via hole, makes these at least two contact pads be connected to the 3rd wiring layer;
Second insulating barrier, is positioned on this first wiring layer;
4th wiring layer, is positioned on this second insulating barrier; And
3rd micro-via hole, makes to be electrically connected between this first wiring layer and the 4th wiring layer in this second insulating barrier.
14. electronic modules as claimed in claim 13, wherein at least one conductor in the 3rd wiring layer is connected at least one conductor in the 4th wiring layer by least one electric pathway, and this at least one electric pathway is through at least one first micro-via hole, at least one conductor being arranged in the second wiring layer, at least one feedthrough conductor, at least one conductor being arranged in this first wiring layer and at least one the 3rd micro-via hole.
15. electronic modules as claimed in claim 12, wherein
This at least one semiconductor subassembly comprises the contact pad towards the 3rd wiring layer;
These at least two feedthrough conductors comprise multiple feedthrough conductor;
This second wiring layer comprises multiple first conductor, and this first conductor limits contact area and at least some feedthrough conductor be connected to by described contact area in the plurality of feedthrough conductor;
3rd wiring layer comprises multiple second conductor, and this second conductor extends to the position of at least some contact area from the position of at least some contact pad;
This module also comprises first micro-via hole at least some contact area being electrically connected at least some second conductor in the 3rd wiring layer; With
This module also comprises second micro-via hole at least some contact pad being electrically connected at least some second conductor in the 3rd wiring layer.
16. electronic modules as claimed in claim 13, also comprise the electric insulation adhesive phase between this at least one semiconductor subassembly and the 3rd wiring layer; And this second micro-via hole making these at least two contact pads be connected to the 3rd wiring layer is positioned at this electric insulation adhesive phase.
17. 1 kinds of semiconductor die package, comprising:
Dielectric substrate, has first surface and the second surface relative with this first surface;
Installation cavity, extends through the dielectric substrate between this first surface and this second surface and has the sidewall of the installation cavity described in restriction;
At least one semiconductor chip, has contact pad in this installation cavity;
First wiring layer, is positioned on the first surface of this dielectric substrate;
Second wiring layer, is positioned on the second surface of this dielectric substrate;
Feedthrough conductor, the first wiring layer is electrically connected with the second wiring layer by the sidewall being positioned at this installation cavity;
First insulating barrier, is positioned on this second wiring layer;
3rd wiring layer, is positioned on this first insulating barrier;
First micro-via hole, makes to be electrically connected between this second wiring layer with the 3rd wiring layer in this first insulating barrier; And
Second micro-via hole, is electrically connected to the 3rd wiring layer by least some contact pad of this semiconductor chip.
18. semiconductor die package as claimed in claim 17, comprising:
Second insulating barrier, is positioned on this first wiring layer;
4th wiring layer, is positioned on this second insulating barrier; And
3rd micro-via hole, makes to be electrically connected between this first wiring layer with the 4th wiring layer in this second insulating barrier.
19. semiconductor die package as claimed in claim 17, wherein at least some contact pad of this semiconductor chip is electrically connected to the first wiring layer on the first surface of this dielectric substrate by multiple electric pathway.
20. semiconductor die package as claimed in claim 19, wherein said multiple electric pathway is through at least one second micro-via hole, at least one conductor being arranged in the 3rd wiring layer, at least one first micro-via hole, at least one conductor being arranged in this second wiring layer and at least one feedthrough conductor.
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CN110473794A (en) * 2019-07-23 2019-11-19 中国科学技术大学 Expansible quantum chip package box structure and preparation method thereof
CN110853516B (en) * 2019-11-21 2022-01-28 青岛歌尔智能传感器有限公司 Display assembly, manufacturing method thereof and electronic equipment

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