CN102347309B - Electric fuse structure and forming method thereof - Google Patents
Electric fuse structure and forming method thereof Download PDFInfo
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- CN102347309B CN102347309B CN 201010246391 CN201010246391A CN102347309B CN 102347309 B CN102347309 B CN 102347309B CN 201010246391 CN201010246391 CN 201010246391 CN 201010246391 A CN201010246391 A CN 201010246391A CN 102347309 B CN102347309 B CN 102347309B
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 229910021332 silicide Inorganic materials 0.000 claims description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 239000000463 material Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000632 Alusil Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010405 anode material Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000007773 negative electrode material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Abstract
The invention provides an electric fuse structure and a forming method thereof, wherein the electric fuse structure is arranged on a semiconductor substrate, the semiconductor substrate comprises at least two shallow trench isolations, and the electric fuse structure comprises: the fusible conductor layer covers the surface of the two shallow trench isolations on the semiconductor substrate; and the cathode and the anode are positioned on the fusible conductor layer and are respectively positioned above the two shallow trench isolations. The electric fuse structure is suitable for integrated circuits with smaller size and can be compatible with a high-k dielectric metal gate process.
Description
Technical field
The present invention relates to semiconductor design and technology field, particularly a kind of electric fuse structure and forming method thereof.
Background technology
Along with the microminiaturization of semiconductor technology and the raising of complicated degree, semiconductor element is easy to be subjected to various defectives or impurity to affect, and single or some metal interconnected, diodes or transistorized inefficacy tend to cause the inefficacy of whole chip.Be head it off, usually be provided with the connecting line (fuse links) of fusible in the integrated circuit, namely fuse (fuse) is used for repairing defective circuit, to improve the rate of finished products of integrated circuit (IC) chip.Fuse can be divided into two kinds of thermo-fuse and electric fuses (eFuse) on the mode of operation.Wherein, electric fuse is to utilize electromigration (electro-migration) principle to make fuse occur opening circuit, and namely electric fuse is programmed.
A typical electric fuse structure comprises as shown in Figure 1 in the prior art: polysilicon layer and stacking thereon metal silicide layer, and negative electrode and anode that external circuit is extended.Wherein the effect of polysilicon layer is, provide silicon atom to finish electromigration with the metallic atom in the help metal silicide, and final the realization is opened circuit.Whole electric fuse structure is positioned at the shallow trench isolation of semiconductor base from (shallow trench isolation, STI) surface, thereby thereby avoiding heat too much in the programming process to be transmitted to semiconductor base affects programing effect.
But, along with further dwindling of dimensions of semiconductor devices, especially arrived 45nm and 32nm technology generation, require the thickness of polysilicon layer in the grid structure more and more thinner, as reach below 500 dusts, and excessively thin polysilicon layer is unfavorable for the electromigration realization, even may cause fusing to realize.On the other hand, along with the introducing of high K medium metal gate process, the programming process of electric fuse may cause forming short circuit at the metal gate layer, thereby affects the normal operation of electric fuse.
Summary of the invention
Purpose of the present invention is intended to one of solve the problems of the technologies described above at least, especially by changing the layout of electric fuse on semiconductor base, and realizing the integrated circuit in 32nm and following technology generation, and the normal operation of the electric fuse in the high K medium metal gate process.
For achieving the above object, one aspect of the present invention proposes a kind of new electric fuse structure, be arranged on the semiconductor base, described semiconductor base comprise at least two shallow trench isolations from, described electric fuse structure comprises: the fusible conductor layer, described semiconductor base cover two described shallow trench isolations from the surface; Negative electrode and anode are positioned on the described fusible conductor layer, described negative electrode and anode lay respectively at two described shallow trench isolations from the top.
In preferred embodiment of the present invention, semiconductor base adopts the body silicon materials, and the fusible conductor layer comprises metal silicide layer, also comprises a polysilicon layer between described fusible conductor layer and the semiconductor base.
In another optional embodiment of the present invention, semiconductor base adopts the body silicon materials, the fusible conductor layer comprises metal silicide layer, comprise as thin as a wafer a polysilicon layer between described fusible conductor layer and the semiconductor base, the formation of described metal silicide layer all exhausts described polysilicon layer as thin as a wafer, thereby after electric fuse structure is formed, no longer include polysilicon layer at semiconductor-based basal surface.
The present invention proposes a kind of method that forms above-mentioned electric fuse structure on the other hand, comprising: semiconductor base is provided; In described semiconductor base, form at least two shallow trench isolations from; Form the fusible conductor layer at described semiconductor base, described fusible conductor layer cover described semiconductor base and two described shallow trench isolations from the surface; Described two shallow trench isolations from above the fusible conductor layer on the negative electrode and the anode that form to be electrically connected respectively.
In preferred embodiment of the present invention, semiconductor substrate adopts the body silicon materials, and the fusible conductor layer comprises metal silicide layer, and by forming polysilicon layer and metal level at described semiconductor-based basal surface successively, the two reaction generates described metal silicide layer.Wherein, if metal level only with part polysilicon layer reaction, and the polysilicon that has neither part nor lot in reaction still original position keep, namely also comprise polysilicon layer between described metal silicide layer and the described semiconductor base; If polysilicon layer thickness is very thin, then may be in the process that forms metal silicide layer, with whole depletion of polysilicon, namely realize another optional embodiment of the present invention: after electric fuse forms, do not comprise polysilicon layer between described metal silicide layer and the semiconductor base.
Method of the present invention and high K medium metal gate process are compatible.Because the semiconductor base surface coverage that adopts the high K medium metal gate process to form has the metal gate layer, its normal operation to electric fuse can have a negative impact, therefore before forming electric fuse structure, further comprising the steps of: at described semiconductor base surface coverage high K medium layer and metal gate layer; Form mask, to expose the zone that forms described electric fuse structure; Remove the described metal gate layer on the described zone.
The present invention is by proposing a kind of contact electrode region division with electric fuse above the STI of semiconductor base, coupling part between the contact electrode (negative electrode and anode) is then directly overlayed the electric fuse structure of semiconductor base material surface, make its integrated circuit that is applicable to smaller szie, and can be compatible with the high K medium metal gate process.
The aspect that the present invention adds and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1 is typical electric fuse structure schematic diagram in the prior art;
Fig. 2 is the electric fuse structure schematic diagram of a preferred embodiment of the present invention;
Fig. 3 is the electric fuse structure schematic diagram of an optional embodiment of the present invention.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein identical or similar label represents identical or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or the setting.In addition, the various specific technique that the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
The present invention proposes a kind of novel electric fuse structure layout, this electric fuse structure is arranged on the semiconductor base, described semiconductor base comprises at least two shallow trench isolation STI, and described electric fuse structure comprises: the fusible conductor layer, on the surface of two described STI of described semiconductor base covering; Negative electrode and anode are positioned at formation electrical connection on the described fusible conductor layer, and described negative electrode and anode lay respectively at the top of two described STI.By this structure as can be known, contact electrode (negative electrode and anode) region division is only arranged above the STI of semiconductor base, the fusible conductor layer of the coupling part between the contact electrode then directly overlays the surface of semiconductor-based bottom material.The advantage of this structure is: on the one hand, semiconductor-based bottom material directly contacts with electric fuse, can provide more silicon atom to help the fusible conductor layer to finish electromigration; On the other hand, the contact electrode zone is positioned at the STI top, can guarantee better thermal insulation effect.Below with reference to specific embodiment this electric fuse structure is described.
Fig. 2 shows the electric fuse structure schematic diagram of a preferred embodiment of the present invention.This electric fuse is arranged on the semiconductor base, and semiconductor base is body silicon base 100 preferably, and body silicon base 100 comprises at least two STI 101.Electric fuse structure comprises: the fusible conductor layer, and preferably metal silicide layer 200, and the thickness of metal silicide layer can be 2-200nm; Comprise polysilicon layer 300 between metal silicide layer 200 and the body silicon base 100, polysilicon layer 300 covers the surface of two STI 101 and the body silicon face between the described STI in body silicon base 100, metal silicide layer 200 then is stacked on the polysilicon layer 300, namely cover equally two STI 101 the surface and between the body silicon face; Negative electrode 400 and anode 500 form electrical connection on metal silicide layer 200, negative electrode 400 and anode 500 lay respectively at the top of two STI 101.It should be noted that, Fig. 2 describes as an example of the body silicon base that only comprises two STI example, electric fuse structure of the present invention only covers two STI in its semiconductor base, thereby guarantee that the coupling part between negative electrode and the anode directly overlays (comprising polysilicon layer 300 and metal silicide layer 200) surface of semiconductor-based bottom material, therefore for the semiconductor base that comprises two above STI, this electric fuse covers is two adjacent STI wherein.
When large electric current continues by this electric fuse structure, electromigration occurs and causes its metallic atom to flow to negative electrode 400 in metal silicide layer 200, because the coupling part between negative electrode and the anode is positioned on the body silicon base 100, so the body silicon base can provide more silicon atom to help metal silicide layer to finish electromigration, therefore the thickness of polysilicon layer 300 can be thinner, especially for the 32nm below polysilicon layer thickness is down to 500 dusts and following technology for generation, the present invention has clear superiority.
Selectively, described electric fuse structure also can comprise very thin polysilicon layer 300, so that metal silicide layer 200 polysilicon layer that this is very thin in forming process all exhausts, thereby after electric fuse structure is formed, no longer include polysilicon layer on body silicon base 100 surfaces, the electric fuse structure of remainder is constant, as shown in Figure 3.As previously mentioned, when electric fuse was programmed, the body silicon base can provide sufficient silicon atom better to finish electromigration with the help metal silicide layer, therefore, even do not comprise polysilicon layer under the metal silicide layer, can realize equally the fusing of electric fuse.
According to an embodiment of the invention electric fuse structure has below been described with reference to the accompanying drawings.It should be noted that; those skilled in the art can select kinds of processes manufacturing according to above-mentioned electric fuse structure; dissimilar product line for example; different technological process etc.; as long as but the electric fuse structure of these different process manufacturings has the essentially identical structure with the present invention; reach essentially identical effect, so also should be included within protection scope of the present invention.In order clearerly to understand the present invention, below will specifically describe the method and the technique that form the above-mentioned electric fuse structure of the present invention, need to prove that also following steps only are schematic, be not limitation of the present invention, those skilled in the art also can realize by other techniques.Following examples are the preferred embodiments of the present invention, can effectively reduce manufacturing cost.
Method according to the above-mentioned electric fuse structure of formation of the embodiment of the invention may further comprise the steps:
Step 1: semiconductor base 100 is provided.Semiconductor-based bottom material preferably comprises body silicon (for example wafer), can also comprise other basic semiconductor or compound semiconductor, such as Ge, GeSi, GaAs, InP, SiC or diamond etc.According to the known designing requirement of prior art (for example p-type substrate or N-shaped substrate), semiconductor base can comprise various doping configurations.Present embodiment is described as an example of the body silicon base example, and electric fuse structure and other cmos device are provided thereon.
Step 2: in described semiconductor base, form at least two shallow trench isolation STI 101.The technique that forms STI can be taked known shallow ditch groove separation process, owing to can comprise any integrated circuit (IC)-components on the described semiconductor base, such as the CMOS transistor, therefore described STI can be compatible mutually with the STI of cmos device, namely directly utilizes the technique of the STI that forms device and need not extra technique.
Selectively, method of the present invention can also be compatible with the high K medium metal gate process, because the metal gate layer under the polysilicon layer in electric fuse zone can cause short circuit, and affects the normal operation of electric fuse, so existing electric fuse structure can not be applicable to the high K medium metal gate process usually.If need in the high K medium metal gate process, use electric fuse structure of the present invention, after step 2, can carry out following steps: at semiconductor base surface coverage high K medium layer and metal gate layer; Then utilize an extra mask to implement photoetching, to expose the zone that will form described electric fuse structure; Then remove the metal gate layer in described zone.Preferably, can remove in the lump the high K medium layer.
Step 3: form the fusible conductor layer at described semiconductor base, described fusible conductor layer covers described semiconductor base 100 and two the described shallow trench isolations surface from 101.Particularly, form a polysilicon layer on body silicon base 100 surfaces, form afterwards a metal level thereon, make metal level and the reaction of the polysilicon under it generate metal silicide layer 200, i.e. fusible conductor layer by heat treatment again.Wherein, metal level only reacts with the part polysilicon layer, and has neither part nor lot in the still original position reservation of polysilicon of reaction, namely also comprises polysilicon layer 300 between described metal silicide layer 200 and the described semiconductor base 100, as shown in Figure 2, namely realized preferred embodiment structure of the present invention; If the initial polysilicon layer that forms as thin as a wafer, then metal level may react with whole polysilicon layers, being about to this polysilicon layer as thin as a wafer exhausts, thereby after electric fuse forms, no longer comprise polysilicon layer between described metal silicide layer and the semiconductor base, as shown in Figure 3, namely realized another optional embodiment structure of the present invention.
Step 4: on the fusible conductor layer of described two shallow trench isolations above from 101, form respectively negative electrode 400 and the anode 500 that is electrically connected.Negative electrode and anode material can be any suitable electrode material, such as the composite multi-layer structure of the electrode material such as aluminium, nickel, titanium nitride, tungsten, alusil alloy or these materials, by electroplating or the mode such as sputter is deposited on the surface of fusible conductor layer such as metal silicide layer 200.Final structure as shown in Figures 2 and 3, wherein, Fig. 2 is the electric fuse structure of the preferred embodiment of the invention, Figure 3 shows that the electric fuse structure of another optional embodiment.
The present invention is by proposing a kind of contact electrode region division with electric fuse above the STI of semiconductor base, and the coupling part between the contact electrode (negative electrode and anode) is directly overlayed the electric fuse structure of semiconductor base material surface, make its integrated circuit such as 32nm and following technology generation that is applicable to smaller szie, and can be compatible with the high K medium metal gate process.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment that scope of the present invention is by claims and be equal to and limit.
Claims (10)
1. an electric fuse structure is characterized in that, described electric fuse structure is arranged on the semiconductor base, described semiconductor base comprise at least two shallow trench isolations from, described electric fuse structure comprises:
The fusible conductor layer, described semiconductor base cover two described shallow trench isolations from the surface and the surface of the semiconductor base between the described trench isolations;
Negative electrode and anode are positioned on the described fusible conductor layer, described negative electrode and anode lay respectively at two described shallow trench isolations from the top; Wherein, the fusible conductor layer of coupling part directly overlays the surface of described semiconductor base between negative electrode and the anode.
2. electric fuse structure as claimed in claim 1 is characterized in that, described semiconductor base comprises body silicon.
3. electric fuse structure as claimed in claim 1 or 2 is characterized in that, described fusible conductor layer comprises metal silicide layer.
4. electric fuse structure as claimed in claim 3 is characterized in that, described fusible conductor layer also comprises polysilicon layer, and described polysilicon layer is between semiconductor base and metal silicide layer.
5. the formation method of an electric fuse structure is characterized in that, comprises the steps:
Semiconductor base is provided;
In described semiconductor base, form at least two shallow trench isolations from;
Form the fusible conductor layer at described semiconductor base, described fusible conductor layer cover described semiconductor-based basal surface and two described shallow trench isolations from the surface;
Described two shallow trench isolations from above the fusible conductor layer on the negative electrode and the anode that form to be electrically connected respectively; Wherein, the fusible conductor layer of coupling part directly overlays the surface of described semiconductor base between negative electrode and the anode.
6. formation method as claimed in claim 5 is characterized in that, described semiconductor base comprises body silicon.
7. such as claim 5 or 6 described formation methods, it is characterized in that described fusible conductor layer comprises metal silicide layer.
8. formation method as claimed in claim 7 is characterized in that, the formation step of described fusible conductor layer comprises: described semiconductor-based basal surface and two described shallow trench isolations from the surface on form polysilicon layer, and form metal level at polysilicon layer;
Generate described metal silicide layer by metal level and polysilicon layer reaction, wherein,
If described metal level only reacts with the described polysilicon layer of part, then comprise polysilicon layer between described metal silicide layer and the described semiconductor base.
9. formation method as claimed in claim 5 is characterized in that, described method and high K medium metal gate process are compatible.
10. formation method as claimed in claim 9 is characterized in that, forms described fusible conductor layer and also comprises before:
At described semiconductor base surface coverage high K medium layer and metal gate layer;
Form mask, to expose the zone that forms described electric fuse structure;
Remove the described metal gate layer on the described zone.
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| CN 201010246391 CN102347309B (en) | 2010-08-05 | 2010-08-05 | Electric fuse structure and forming method thereof |
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| CN 201010246391 CN102347309B (en) | 2010-08-05 | 2010-08-05 | Electric fuse structure and forming method thereof |
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| CN104701295B (en) * | 2013-12-05 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and forming method thereof |
| CN106449594B (en) * | 2016-12-02 | 2018-10-02 | 乐清市风杰电子科技有限公司 | a kind of manufacturing method of programmable fuse structure |
| WO2020037669A1 (en) * | 2018-08-24 | 2020-02-27 | 深圳市为通博科技有限责任公司 | Electrically programmable fuse, manufacturing method therefor, and storage unit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420217B1 (en) * | 1999-08-17 | 2002-07-16 | National Semiconductor Corporation | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology |
| CN101599479A (en) * | 2008-06-03 | 2009-12-09 | 恩益禧电子股份有限公司 | The method of electric fuse, semiconductor device and disconnecting electrical fuse |
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| US7109564B2 (en) * | 2004-03-22 | 2006-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low power fuse structure and method of making the same |
| US8564023B2 (en) * | 2008-03-06 | 2013-10-22 | Xilinx, Inc. | Integrated circuit with MOSFET fuse element |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420217B1 (en) * | 1999-08-17 | 2002-07-16 | National Semiconductor Corporation | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology |
| CN101599479A (en) * | 2008-06-03 | 2009-12-09 | 恩益禧电子股份有限公司 | The method of electric fuse, semiconductor device and disconnecting electrical fuse |
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