CN102347309A - Electric fuse structure and formation method thereof - Google Patents
Electric fuse structure and formation method thereof Download PDFInfo
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- CN102347309A CN102347309A CN2010102463917A CN201010246391A CN102347309A CN 102347309 A CN102347309 A CN 102347309A CN 2010102463917 A CN2010102463917 A CN 2010102463917A CN 201010246391 A CN201010246391 A CN 201010246391A CN 102347309 A CN102347309 A CN 102347309A
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Abstract
The invention provides an electric fuse structure and a formation method thereof. The electric fuse structure is arranged on a semiconductor substrate; the semiconductor substrate comprises at least two shallow trench isolations; the electric fuse structure comprises a fusible conductor layer, a cathode and an anode, wherein on the semiconductor substrate, the fusible conductor layer covers the surfaces of the two shallow trench isolations; the cathode and the anode are positioned on the fusible conductor layer; and the cathode and the anode are positioned above the two shallow trench isolations respectively. The electric fuse structure is applicable to integrated circuits with smaller sizes and can be compatible with a high-k-medium metal gate process.
Description
Technical field
The present invention relates to semiconductor design and technology field, particularly a kind of electric fuse structure and forming method thereof.
Background technology
Along with the microminiaturization of semiconductor technology and the raising of complicated degree, semiconductor element is easy to be subjected to various defectives or impurity to influence, and single or number of metal interconnection, diode or transistorized inefficacy tend to cause the inefficacy of entire chip.Be head it off, be provided with the connecting line (fuse links) of fusible in the integrated circuit usually, promptly fuse (fuse) is used to repair defective circuit, to improve the rate of finished products of integrated circuit (IC) chip.Fuse can be divided into two kinds of thermo-fuse and electric fuses (eFuse) on the mode of operation.Wherein, electric fuse is to utilize electromigration (electro-migration) principle to make fuse occur opening circuit, and promptly electric fuse is programmed.
A typical electric fuse structure comprises as shown in Figure 1 in the prior art: polysilicon layer with pile up metal silicide layer thereon, and negative electrode and anode that external circuit is extended.Wherein the effect of polysilicon layer is, provide silicon atom to accomplish electromigration to help the metallic atom in the metal silicide, and final the realization is opened circuit.The shallow trench isolation that whole electric fuse structure is positioned at the semiconductor-based end from (shallow trench isolation, STI) surface, thereby thereby avoid heat conduction too much in the programming process to influence programing effect to the semiconductor-based end.
But,, especially arrived 45nm and 32nm technology generation along with further dwindling of dimensions of semiconductor devices; Require the thickness of polysilicon layer in the grid structure more and more thinner; As reach below 500 dusts, and thin excessively polysilicon layer is unfavorable for the electromigration realization, even possibly cause fusing to realize.On the other hand, along with the introducing of high K medium metal gate process, the programming process of electric fuse possibly cause forming short circuit at the metal gate layer, thereby influences the operate as normal of electric fuse.
Summary of the invention
The object of the invention is intended to one of solve the problems of the technologies described above at least, especially through changing electric fuse in the suprabasil layout of semiconductor, and with the integrated circuit of realization 32nm and following technology generation, and the operate as normal of the electric fuse in the high K medium metal gate process.
For achieving the above object; One aspect of the present invention proposes a kind of new electric fuse structure; Be arranged at at semiconductor-based the end; The said semiconductor-based end, comprise that at least two shallow trench isolations leave; Said electric fuse structure comprises: the fusible conductor layer covers two surfaces that said shallow trench isolation leaves on the said semiconductor-based end; Negative electrode and anode are positioned on the said fusible conductor layer, and said negative electrode and anode lay respectively at the top that two said shallow trench isolations leave.
In preferred embodiment of the present invention, the body silicon materials are adopted at the semiconductor-based end, and the fusible conductor layer comprises metal silicide layer, said fusible conductor layer and also comprise a polysilicon layer at semiconductor-based the end.
In another optional embodiment of the present invention; The body silicon materials are adopted at the semiconductor-based end; The fusible conductor layer comprises metal silicide layer; Said fusible conductor layer and comprise as thin as a wafer a polysilicon layer at semiconductor-based the end; The formation of said metal silicide layer all exhausts said polysilicon layer as thin as a wafer; Thereby after electric fuse structure is formed, on semiconductor-based basal surface, no longer include polysilicon layer.
The present invention proposes a kind of method that forms above-mentioned electric fuse structure on the other hand, comprising: the semiconductor-based end is provided; In the said semiconductor-based end, forming at least two shallow trench isolations leaves; On the said semiconductor-based end, form the fusible conductor layer, said fusible conductor layer covers the said semiconductor-based end and two surfaces that said shallow trench isolation leaves; Form negative electrode and the anode that is electrically connected on the fusible conductor layer above said two shallow trench isolations leave respectively.
In preferred embodiment of the present invention, semiconductor substrate adopts the body silicon materials, and the fusible conductor layer comprises metal silicide layer, and through forming polysilicon layer and metal level at said semiconductor-based basal surface successively, the two reaction generates said metal silicide layer.Wherein, if metal level only with part polysilicon layer reaction, and the polysilicon that has neither part nor lot in reaction still original position keep promptly said metal silicide layer and also comprise polysilicon layer at said the semiconductor-based end; If polysilicon layer thickness is extremely thin; Then maybe be in the process that forms metal silicide layer; With whole depletion of polysilicon, promptly realize another optional embodiment of the present invention: after electric fuse forms, said metal silicide layer and do not comprise polysilicon layer at semiconductor-based the end.
Method of the present invention and high K medium metal gate process are compatible.Because the semiconductor-based basal surface that adopts the high K medium metal gate process to form is coated with the metal gate layer; Its operate as normal to electric fuse can have a negative impact; Therefore before forming electric fuse structure, further comprising the steps of: as to cover high K medium layer and metal gate layer at said semiconductor-based basal surface; Form mask, to expose the zone that forms said electric fuse structure; Remove the said metal gate layer on the said zone.
The present invention is through proposing a kind of top that the contact electrode zone of electric fuse is arranged on the STI at the semiconductor-based end; Coupling part between the contact electrode (negative electrode and anode) is then directly overlayed the electric fuse structure of semiconductor substrate material surface; Make its integrated circuit that is applicable to smaller szie, and can be compatible with the high K medium metal gate process.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1 is typical electric fuse structure sketch map in the prior art;
Fig. 2 is the electric fuse structure sketch map of a preferred embodiment of the present invention;
Fig. 3 is the electric fuse structure sketch map of an optional embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; Below first characteristic of Miao Shuing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
The present invention proposes a kind of novel electric fuse structure layout; This electric fuse structure is arranged at at semiconductor-based the end; The said semiconductor-based end, comprise at least two shallow trench isolation STI, and said electric fuse structure comprises: fusible conductor layer, the surface of two said STI of covering on the said semiconductor-based end; Negative electrode and anode are positioned at formation electrical connection on the said fusible conductor layer, and said negative electrode and anode lay respectively at the top of two said STI.Can be known only have contact electrode (negative electrode and anode) zone to be arranged on the STI top at the semiconductor-based end by this structure, the fusible conductor layer of the coupling part between the contact electrode then directly overlays the surface of semiconductor-based bottom material.The advantage of this structure is: on the one hand, semiconductor-based bottom material directly contacts with electric fuse, can provide more silicon atom to accomplish electromigration to help the fusible conductor layer; On the other hand, the contact electrode zone is positioned at the STI top, can guarantee better thermal insulation effect.Below will combine concrete embodiment to describe this electric fuse structure.
Fig. 2 shows the electric fuse structure sketch map of a preferred embodiment of the present invention.This electric fuse is arranged at at semiconductor-based the end, and the semiconductor-based end is body silicon base 100 preferably, and body silicon base 100 comprises at least two STI 101.Electric fuse structure comprises: the fusible conductor layer, and preferably metal silicide layer 200, and the thickness of metal silicide layer can be 2-200nm; Comprise polysilicon layer 300 between metal silicide layer 200 and the body silicon base 100; The body silicon face of polysilicon layer 300 between surface that covers two STI 101 on the body silicon base 100 and said STI; Metal silicide layer 200 then is stacked on the polysilicon layer 300, promptly cover equally two STI 101 the surface and between the body silicon face; Negative electrode 400 and anode 500 form electrical connection on metal silicide layer 200, negative electrode 400 and anode 500 lay respectively at the top of two STI 101.What need explanation is; Fig. 2 is that example is described with the body silicon base that only comprises two STI; Electric fuse structure according to the invention only covers two STI in its semiconductor-based end; Thereby guarantee that the coupling part between negative electrode and the anode directly overlays (comprising polysilicon layer 300 and metal silicide layer 200) surface of semiconductor-based bottom material; Therefore for the semiconductor-based end that comprises two above STI, this electric fuse covers is two adjacent STI wherein.
When big electric current continues through this electric fuse structure; Electromigration takes place and causes its metallic atom to flow to negative electrode 400 in metal silicide layer 200; Because the coupling part between negative electrode and the anode is positioned on the body silicon base 100; So the body silicon base can provide more silicon atom to accomplish electromigration to help metal silicide layer; Therefore the thickness of polysilicon layer 300 can be thinner; Especially for 32nm below polysilicon layer thickness is reduced to 500 dusts and following technology generation, the present invention has clear superiority.
Selectively; Said electric fuse structure also can comprise extremely thin polysilicon layer 300; So that metal silicide layer 200 polysilicon layer that this is extremely thin in forming process all exhausts; Thereby after electric fuse structure is formed; On body silicon base 100 surfaces, no longer include polysilicon layer; The electric fuse structure of remainder is constant, as shown in Figure 3.As previously mentioned, when electric fuse was programmed, the body silicon base can provide sufficient silicon atom better to accomplish electromigration to help metal silicide layer, therefore, even do not comprise polysilicon layer under the metal silicide layer, can realize the fusing of electric fuse equally.
Electric fuse structure has according to an embodiment of the invention below been described with reference to the accompanying drawings.It should be noted that; Those skilled in the art can select kinds of processes manufacturing according to above-mentioned electric fuse structure; For example dissimilar product lines; Different processes flow process or the like; As long as but the electric fuse structure of these different process manufacturings has the essentially identical structure with the present invention; Reach essentially identical effect, so also should be included within protection scope of the present invention.In order clearerly to understand the present invention; Below will specifically describe the method and the technology that form the above-mentioned electric fuse structure of the present invention, need to prove that also following steps only are schematic; Be not limitation of the present invention, those skilled in the art also can realize through other technologies.Following examples are the preferred embodiments of the present invention, can effectively reduce manufacturing cost.
Method according to the above-mentioned electric fuse structure of formation of the embodiment of the invention may further comprise the steps:
Step 1: the semiconductor-based end 100 is provided.Semiconductor-based bottom material preferably comprises body silicon (for example wafer), can also comprise other basic semiconductor or compound semiconductor, for example Ge, GeSi, GaAs, InP, SiC or diamond etc.According to the known designing requirement of prior art (for example p type substrate or n type substrate), the semiconductor-based end, can comprise various doping configurations.Present embodiment is that example is described with the body silicon base, and electric fuse structure and other cmos device are provided thereon.
Step 2: in the said semiconductor-based end, form at least two shallow trench isolation STI 101.The technology that forms STI can be taked known shallow ditch groove separation process; Owing to can comprise any integrated circuit (IC)-components at said the semiconductor-based end; Like the CMOS transistor; Therefore said STI can be compatible mutually with the STI of cmos device, promptly directly utilizes the technology of the STI that forms device and need not extra technology.
Selectively; Method of the present invention can also be compatible with the high K medium metal gate process; Because the metal gate layer under the polysilicon layer in electric fuse zone can cause short circuit, and influences the operate as normal of electric fuse, so existing electric fuse structure can not be applicable to the high K medium metal gate process usually.Utilization electric fuse structure of the present invention in the high K medium metal gate process can carry out following steps: cover high K medium layer and metal gate layer at semiconductor-based basal surface after step 2 if desired; Utilize an extra mask to implement photoetching then, to expose the zone that will form said electric fuse structure; Then remove the metal gate layer in said zone.Preferably, can remove the high K medium layer in the lump.
Step 3: on the said semiconductor-based end, form the fusible conductor layer, said fusible conductor layer covers the said semiconductor-based end 100 and two said shallow trench isolations from 101 surface.Particularly, form a polysilicon layer, form a metal level afterwards thereon, make metal level and the reaction of the polysilicon under it generate metal silicide layer 200, promptly fusible conductor layer through heat treatment again on body silicon base 100 surfaces.Wherein, Metal level only with part polysilicon layer reaction, and the polysilicon that has neither part nor lot in reaction still original position keep promptly said metal silicide layer 200 and also comprise polysilicon layer 300 at said the semiconductor-based end 100; As shown in Figure 2, promptly realized preferred embodiment structure of the present invention; If the initial polysilicon layer that forms as thin as a wafer; Then metal level possibly react with whole polysilicon layers; Being about to this polysilicon layer as thin as a wafer exhausts; Thereby after electric fuse forms; Said metal silicide layer and no longer comprise polysilicon layer at semiconductor-based the end; As shown in Figure 3, promptly realized another optional example structure of the present invention.
Step 4: on the fusible conductor layer above in the of 101, form the negative electrode 400 and anode 500 that is electrically connected respectively at said two shallow trench isolations.Negative electrode and anode material can be any suitable electrode material; Like the composite multi-layer structure of electrode materials such as aluminium, nickel, titanium nitride, tungsten, alusil alloy or these materials, be deposited on the surface of fusible conductor layer such as metal silicide layer 200 through modes such as plating or sputters.Final structure as shown in Figures 2 and 3, wherein, Fig. 2 is the electric fuse structure of the preferred embodiment of the invention, shown in Figure 3 is the electric fuse structure of another optional embodiment.
The present invention is through proposing a kind of top that the contact electrode zone of electric fuse is arranged on the STI at the semiconductor-based end; And the coupling part between the contact electrode (negative electrode and anode) directly overlayed the electric fuse structure of semiconductor substrate material surface; Make its integrated circuit that is applicable to smaller szie like 32nm and following technology generation, and can be compatible with the high K medium metal gate process.
Although illustrated and described embodiments of the invention; For the ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (10)
1. an electric fuse structure is characterized in that, said electric fuse structure is arranged at at semiconductor-based the end, and the said semiconductor-based end comprises that at least two shallow trench isolations leave, and said electric fuse structure comprises:
The fusible conductor layer covers two surfaces that said shallow trench isolation leaves on the said semiconductor-based end;
Negative electrode and anode are positioned on the said fusible conductor layer, and said negative electrode and anode lay respectively at the top that two said shallow trench isolations leave.
2. electric fuse structure as claimed in claim 1 is characterized in that, the said semiconductor-based end comprises body silicon.
3. electric fuse structure as claimed in claim 1 or 2 is characterized in that, said fusible conductor layer comprises metal silicide layer.
4. electric fuse structure as claimed in claim 1 or 2 is characterized in that, said fusible conductor layer and comprise polysilicon layer at said the semiconductor-based end.
5. the formation method of an electric fuse structure is characterized in that, comprises the steps:
The semiconductor-based end, be provided;
In the said semiconductor-based end, forming at least two shallow trench isolations leaves;
On the said semiconductor-based end, form the fusible conductor layer, said fusible conductor layer covers the said semiconductor-based end and two surfaces that said shallow trench isolation leaves;
Form negative electrode and the anode that is electrically connected on the fusible conductor layer above said two shallow trench isolations leave respectively.
6. formation method as claimed in claim 5 is characterized in that, the said semiconductor-based end comprises body silicon.
7. like claim 5 or 6 described formation methods, it is characterized in that said fusible conductor layer comprises metal silicide layer.
8. formation method as claimed in claim 7 is characterized in that, said metal silicide layer generates through metal and polysilicon reaction, wherein,
If said metal only with the reaction of the said polysilicon of part, then said metal silicide layer and comprise polysilicon layer at said the semiconductor-based end.
9. formation method as claimed in claim 5 is characterized in that, said method and high K medium metal gate process are compatible.
10. formation method as claimed in claim 9 is characterized in that, forms said fusible conductor layer and also comprises before:
Cover high K medium layer and metal gate layer at said semiconductor-based basal surface;
Form mask, to expose the zone that forms said electric fuse structure;
Remove the said metal gate layer on the said zone.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010246391 CN102347309B (en) | 2010-08-05 | 2010-08-05 | Electric fuse structure and formation method thereof |
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| CN 201010246391 CN102347309B (en) | 2010-08-05 | 2010-08-05 | Electric fuse structure and formation method thereof |
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| CN102347309B CN102347309B (en) | 2013-04-10 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701295A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and production method thereof |
| CN109390275A (en) * | 2016-12-02 | 2019-02-26 | 乐清市风杰电子科技有限公司 | The manufacturing method of polysilicon fuse structure |
| WO2020037669A1 (en) * | 2018-08-24 | 2020-02-27 | 深圳市为通博科技有限责任公司 | Electrically programmable fuse, manufacturing method therefor, and storage unit |
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| US20050218475A1 (en) * | 2004-03-22 | 2005-10-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low power fuse structure and method for making the same |
| US20090224323A1 (en) * | 2008-03-06 | 2009-09-10 | Xilinx, Inc. | Integrated circuit with mosfet fuse element |
| CN101599479A (en) * | 2008-06-03 | 2009-12-09 | 恩益禧电子股份有限公司 | The method of electric fuse, semiconductor device and disconnecting electrical fuse |
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| US6420217B1 (en) * | 1999-08-17 | 2002-07-16 | National Semiconductor Corporation | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701295A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and production method thereof |
| CN104701295B (en) * | 2013-12-05 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and forming method thereof |
| CN109390275A (en) * | 2016-12-02 | 2019-02-26 | 乐清市风杰电子科技有限公司 | The manufacturing method of polysilicon fuse structure |
| CN109390275B (en) * | 2016-12-02 | 2024-01-09 | 乐清市风杰电子科技有限公司 | Manufacturing method of polycrystalline silicon fuse structure |
| WO2020037669A1 (en) * | 2018-08-24 | 2020-02-27 | 深圳市为通博科技有限责任公司 | Electrically programmable fuse, manufacturing method therefor, and storage unit |
| CN111095546A (en) * | 2018-08-24 | 2020-05-01 | 深圳市为通博科技有限责任公司 | Electric fuse, manufacturing method thereof and memory unit |
| US10991655B2 (en) | 2018-08-24 | 2021-04-27 | Shenzhen Weitongbo Technology Co., Ltd. | E-fuse and manufacturing method thereof, and memory cell |
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| CN102347309B (en) | 2013-04-10 |
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