CN102347265B - Method for preventing punch through voltage reduction of memory and memory thereof - Google Patents
Method for preventing punch through voltage reduction of memory and memory thereof Download PDFInfo
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- CN102347265B CN102347265B CN201010245598.2A CN201010245598A CN102347265B CN 102347265 B CN102347265 B CN 102347265B CN 201010245598 A CN201010245598 A CN 201010245598A CN 102347265 B CN102347265 B CN 102347265B
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Abstract
The invention provides a method for preventing punch through voltage reduction of a memory. The method is characterized by: providing a semiconductor substrate on which a plurality of word lines and a plurality of bit lines are formed; forming a mask layer which exposes the semiconductor substrate between the adjacent word lines and the adjacent bit lines on the word lines and the bit lines; taking the mask layer as a mask and performing insulation ion implantation to the semiconductor substrate exposed by the mask layer; annealing the ion implanted in the semiconductor substrate so as to form an anti-punch through zone in the semiconductor substrate. By using the method of the invention, punch through voltage reduction of the memory can be prevented.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly prevent method and the memory of memory punch through voltage reduction.
Background technology
Memory is the semiconductor device for data on file or data.In the storage of data information, represent the capacity of memory with position (Bit).Each unit in order to data on file is called memory cell (Cell).And memory cell mode with array in internal memory is arranged, the combination of each row and row represents a specific memory unit address.Multiple memory cell of wherein, listing in same a line or same row are connected with common wire.Wherein, the wire of the memory cell series connection of identical a line (or mutually same row) is called to word line, and the wire relevant with the transmission of data is called bit line.
Number of patent application is to disclose a kind of memory in 20061014728.4 Chinese patent application, specifically please refer to Fig. 1.Existing memory comprises Semiconductor substrate (not shown).In described Semiconductor substrate, there is multiple row bit line 210 and multirow word line 250.Bit line 210 is by Semiconductor substrate being carried out to the formation of Implantation, and bit line 210 is called again diffusion position line district (or buried regions bitline regions, Buried Bit Line) by those skilled in the art.The direction that described word line 250 follows is by the grid series connection of the memory cell between bit line 210.
Find in practice, the punch through voltage reduction of the memory of said structure, has affected device performance.
Summary of the invention
The problem that the present invention solves is to provide a kind of method and memory that prevents memory punch through voltage reduction, prevents the punch through voltage reduction between word line that memory is adjacent and between adjacent bit line.
For addressing the above problem, the invention provides a kind of method that prevents memory punch through voltage reduction, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with many word lines and multiple bit lines;
On described word line and bit line, form mask layer, described mask layer exposes the Semiconductor substrate between adjacent word line and adjacent bit lines;
Taking described mask layer as mask, the Semiconductor substrate that described mask layer the is exposed Implantation that insulate;
The ion injecting in described Semiconductor substrate is annealed, in described Semiconductor substrate, form anti-reach through region.
Alternatively, the material of described anti-reach through region is electrical insulation material, and described electrical insulation material is silica, silicon nitride, carborundum, silicon oxynitride.
Alternatively, the ion of described insulation Implantation is oxonium ion, nitrogen ion, carbon ion or nitrogen oxide ion.
Alternatively, the ion energy scope of described insulation Implantation is 10～80Kev, and dosage range is 5E14～1E16cm
-2.
Alternatively, described mask layer is photoresist layer, silicon nitride layer or silicon oxide layer.
Alternatively, before the ion injecting in described Semiconductor substrate is annealed, also comprise:
Carry out etching technics, remove described mask layer.
Alternatively, described in be annealed into rapid thermal anneal process, annealing region is 400～1050 degrees Celsius, annealing time is 10～120 seconds, N
2range of flow is 200～1500sccm.
Correspondingly, the present invention also provides a kind of memory, comprising:
Semiconductor substrate, has many word lines and multiple bit lines in described Semiconductor substrate, it is characterized in that,
Semiconductor substrate between adjacent word line and adjacent bit line is anti-reach through region, and the material of described anti-reach through region is electrical insulation material, described anti-reach through region by injection insulate ion form.
Alternatively, described electrical insulation material is silica, silicon nitride, carborundum, silicon oxynitride.
Alternatively, described insulation ion is oxonium ion, nitrogen ion, carbon ion or nitrogen oxide ion.
Alternatively, the Implantation Energy scope of described insulation ion is 10～80Kev, and implantation dosage scope is 5E14～1E16cm
-2.
Compared with prior art, technical scheme of the present invention has the following advantages: by the Implantation that insulate of the Semiconductor substrate between adjacent word line and adjacent bit lines, the ion injecting is annealed, Semiconductor substrate between described adjacent word line and adjacent bit lines forms anti-reach through region, the material of described anti-reach through region is electrical insulation material, by adjacent word line and adjacent bit line mutually insulated, thereby avoid the doping ion in diffusion position line district to move by anti-reach through region, form along the leakage current of word-line direction or along the leakage current of bit line direction, prevent the punch through voltage reduction between punch through voltage between adjacent word line and adjacent bit line.
Brief description of the drawings
Fig. 1 is the vertical view of existing memory construction.
Fig. 2 is the manufacture method schematic flow sheet of the punch through voltage reduction that prevents memory of the present invention.
Fig. 3 is to the plan structure schematic diagram of memory of the present invention.
Fig. 4 is the cross-sectional view of memory of the present invention along AA direction.
Fig. 5 is the cross-sectional view of memory of the present invention along BB direction.
Fig. 6 is that memory of the present invention is along CC directional profile structural representation.
Embodiment
Inventor's discovery, the reason of the punch through voltage reduction of the memory of prior art is that the semiconductor substrate region between adjacent word line and the adjacent bit lines of memory exists leakage current.Particularly, because the doping ion of diffusion position line district (being bit line) is by the Semiconductor substrate between adjacent word line and adjacent bit lines, in Semiconductor substrate between adjacent word line and adjacent bit lines, form leakage current, cause the punch through voltage reduction between punch through voltage reduction between adjacent word line and adjacent bit line.
Inventor considers that the Semiconductor substrate between adjacent word line and adjacent bit lines carries out transoid Implantation, dopant implant ion in described Semiconductor substrate, form barrier region, to stop the doping ion in described diffusion position line district by described Semiconductor substrate, thereby reduce leakage current.Particularly, the conductivity type opposite of the conduction type of the doping ion of described transoid Implantation and the doping ion in diffusion position line district.For example, taking Semiconductor substrate as P type is as example, the conduction type of the doping ion in diffusion position line district is N-type, and the doping ion of transoid Implantation should be P type.But inventor considers again the feature size downsizing along with semiconductor device, distance between distance between adjacent word line and adjacent bit line is dwindled, thereby reduce along word-line direction with along the distance between the diffusion position line district of bit line direction, doping ion between diffusion position line district is more prone to by the Semiconductor substrate between adjacent word line and adjacent bit lines, if only adopt transoid Implantation, cannot effectively stop the doping ion in diffusion position line district by described Semiconductor substrate, leakage current still exists, this still can cause the punch through voltage reduction of adjacent word line and adjacent bit lines.
Therefore, inventor proposes the Implantation that insulate of the Semiconductor substrate between adjacent word line and adjacent bit lines, the ion injecting is annealed, form anti-reach through region in the Semiconductor substrate of described adjacent word line and adjacent bit lines, the material of described anti-reach through region is electrical insulation material.
Particularly, the invention provides a kind of method of the punch through voltage reduction that prevents memory, please refer to Fig. 2, is the manufacture method schematic flow sheet of the punch through voltage reduction that prevents memory of the present invention.Described method comprises:
Step S1, provides Semiconductor substrate, is formed with many word lines and multiple bit lines in described Semiconductor substrate;
Step S2 forms mask layer on described word line and bit line, and described mask layer exposes the Semiconductor substrate between adjacent word line and adjacent bit lines;
Step S3, taking described mask layer as mask, the Semiconductor substrate that described mask layer the is exposed Implantation that insulate;
Step S4, anneals to the ion injecting in described Semiconductor substrate, forms anti-reach through region in described Semiconductor substrate.
Below in conjunction with specific embodiment, technical scheme of the present invention is elaborated.
Please refer to Fig. 3, is the plan structure schematic diagram of memory of the present invention.First Semiconductor substrate 300 is provided, in described Semiconductor substrate 300, is formed with multiple bit lines 310 and many word lines 350.For convenience of explanation, in figure, illustrate as an example of 310 and 4 word lines 350 of 5 bit lines example.In the present embodiment, the direction of described bit line 310 is parallel with the direction of row, and described word line 350 is parallel with the direction of row.In figure, AA direction is parallel with the direction of word line 350 with BB direction, and CC direction is parallel with the direction of bit line 310.
Semiconductor substrate between adjacent word line 350 and adjacent bit lines 310 Implantation that can insulate in subsequent process steps, forms anti-reach through region, in figure, represents with 370.
With reference to figure 3, described bit line 310 is by the source electrode of the memory cell between word line 350 or drain electrode series connection.Described bit line 310 is by carrying out Implantation formation to Semiconductor substrate.Bit line 310 is called again diffusion position line district (or buried regions bitline regions, Buried Bit Line) by those skilled in the art.The direction that described word line 350 follows is by the grid series connection of the memory cell between bit line 310.
In practice, the material of described Semiconductor substrate 300 can be silicon, germanium or other semi-conducting materials.As one embodiment of the present of invention, described Semiconductor substrate 300 is P type substrate.
For the structure of word line is described.With reference to figure 4, for Fig. 3 is along the cross-sectional view of AA direction.Along forming multiple memory cell in the Semiconductor substrate 300 of word-line direction, each memory cell comprises the bit line 310 in the Semiconductor substrate of grid 340 and grid 340 both sides.Described bit line 310 is called again diffusion position line district.The conductivity type opposite of described diffusion position line district's conduction type and Semiconductor substrate 300.If Semiconductor substrate 300 is P type substrate, the conduction type in described diffusion position line district is N-type conduction type.
Described grid 340 is polysilicon gate.Described grid 340 belows are formed with stacked structure 330, and described stacked structure 330 is sandwich construction, and as an embodiment, described stacked structure 330 is dielectric layer-the catch three level stack structure of charge layer-dielectric layer.Between described grid 340, have dielectric layer (not marking), described grid 340 and dielectric layer top are formed with word line 350.
Incorporated by reference to Fig. 5, for Fig. 3 is along the cross-sectional view of BB direction.Along the multiple bit lines 310 of arranging in the Semiconductor substrate 300 of word-line direction.Semiconductor substrate between adjacent word line 350 is used to form anti-reach through region 370.Because inventor finds through research, it is because the doping ion of diffusion position line district (being bit line 310) passes through Semiconductor substrate between adjacent word line 350 and adjacent bit lines 310 that the Semiconductor substrate between adjacent word line 350 and adjacent bit line 310 exists the reason of leakage current.For stop described bit line 310 doping ion form leakage current by Semiconductor substrate, inventor proposes to form anti-reach through region 370 in the Semiconductor substrate between adjacent word line 350 and adjacent bit line 310.
For the position of anti-reach through region is described, please refer to Fig. 6, for Fig. 3 is along the cross-sectional view of CC direction.Along multiple grids 340 of arranging in the Semiconductor substrate 300 of bit line direction, each grid 340 below has stacked structure 330, and grid 340 tops have word line 350, and the Semiconductor substrate in Fig. 6 between adjacent word line 350 is for the anti-reach through region 370 of follow-up formation.
Particularly, on described adjacent word line 350 and bit line 310, form mask layer (not shown) with reference to figure 3 (simultaneously with reference to figure 5 and Fig. 6), described mask layer exposes the Semiconductor substrate between adjacent word line 350 and bit line 310, Semiconductor substrate between described adjacent word line 350 and bit line 310, for the follow-up Implantation that insulate, forms anti-reach through region 370.
In the present embodiment, described mask layer is photoresist layer, is formed in Semiconductor substrate 300 in the mode of spin coating, is formed in described Semiconductor substrate 300 through the mode of developing, expose.As other embodiment, described mask layer can also be silicon oxide layer or silicon nitride layer, mode with deposition is formed in Semiconductor substrate 300, and described silicon oxide layer or silicon nitride layer, through selective etch, expose the Semiconductor substrate between adjacent word line 350 and bit line 310.
Then, still with reference to figure 3 (simultaneously with reference to figure 5 and Fig. 6), taking described mask layer as mask, the Semiconductor substrate that described mask layer the is exposed Implantation that insulate, the ion of described insulation Implantation is for after annealing, be combined with the silicon of Semiconductor substrate, form anti-reach through region 370, the material of described anti-reach through region 370 is electrical insulation material.
The ion of described insulation Implantation can be oxonium ion, nitrogen ion, carbon ion or nitrogen oxide ion, and the electrical insulation material of corresponding formation can be silica, silicon nitride, carborundum or silicon oxynitride.In practice, the kind of the electrical insulation material that can form as required, the ionic species of selection insulation Implantation.
If the electrical insulation material forming is silica, the ion of the Implantation that insulate is oxonium ion; If the electrical insulation material forming is silicon nitride, the ion of the Implantation that insulate is nitrogen ion; If the electrical insulation material forming is carborundum, the ion of the Implantation that insulate is carbon ion; If the electrical insulation material forming is silicon oxynitride, the ion of the Implantation that insulate is nitrogen oxide ion.
As an embodiment, the ion energy scope of described insulation Implantation is 10～80Kev, and dosage range is 5E14～1E16cm
-2.The thickness of the electrical insulation material of the energy of described insulation Implantation and dosage and follow-up formation has relation.Conventionally, in the case of the insulation ionic species of Implantation and dosage certain, the energy of insulation Implantation is larger, the thickness of the electrical insulation material forming after annealing is larger; In the case of the ionic species of insulation Implantation is certain, the dosage of insulation Implantation is larger, and the thickness of electrical insulation material forming after annealing is larger.
As the preferred embodiments of the present invention, after insulation Implantation, carry out etching technics, remove described mask layer.Described etching can be dry etching or wet etching.As those skilled in the art's known technology, be not described in detail here.
Then, with reference to figure 3 (simultaneously with reference to figure 5 and Fig. 6), carry out annealing process, the insulation ion injecting is annealed, in the Semiconductor substrate between adjacent word line 350 and bit line 310, form anti-reach through region 370.The material of described anti-reach through region 370 is electrical insulation material.
Described annealing can be boiler tube annealing or rapid thermal annealing.As preferred embodiment, the present invention utilizes rapid thermal annealing, activates on the one hand the ion injecting, and on the other hand, eliminates the implant damage to Semiconductor substrate.The process conditions of described rapid thermal annealing are: temperature range is 400～1050 degrees Celsius, and time range is 10～120 seconds, N
2range of flow is 200～1500sccm.
Electrical insulation material of the present invention can be silica, silicon nitride, carborundum or silicon oxynitride.Taking described electrical insulation material as silica is as example, insulation Implantation oxonium ion enters Semiconductor substrate.The degree of depth of described oxonium ion in Semiconductor substrate and concentration have determined the thickness (i.e. the degree of depth of anti-reach through region 370) of silica.Described silica is as anti-reach through region 370, can effectively stop the movement of the Semiconductor substrate between adjacent word line 350 and adjacent bit line 310 of the doping ion in adjacent diffusion position line district (being bit line 310), reduce the leakage current of anti-reach through region 370, stop the decline of punch through voltage between punch through voltage between adjacent word line 350 and adjacent bit line 310.
Described electrical insulation material has certain degree of depth in Semiconductor substrate 300, and the described degree of depth should arrange according to the degree of depth of adjacent diffusion position line district (or bit line 310).Conventionally, the described electrical insulation material degree of depth should be identical with the degree of depth of described bit line 310 or be slightly larger than the degree of depth of described bit line 310.
Based on said method, the present invention also provides a kind of memory, with reference to figure 3, is formed with multiple bit lines 310 and many word lines 350 in Semiconductor substrate 300, and the Semiconductor substrate between described adjacent bit line 310 and adjacent word line 350 is anti-reach through region 370.The material of described anti-reach through region 370 is electrical insulation material.
As an embodiment, there is shown 310 and 4 word lines 350 of 5 bit lines.In the present embodiment, described bit line 310 parallel arrangements, and the direction of bit line 310 and the direction of row consistent; Described word line 350 parallel arrangements, and the direction of word line 350 is consistent with the direction of row.
Wherein, the material of described Semiconductor substrate 300 can be silicon, germanium or other semi-conducting materials.In the present embodiment, the material of described Semiconductor substrate 300 is silicon.Described Semiconductor substrate 300 is P type silicon substrate.
As shown in Figure 4, described bit line 310 is as source electrode or the drain electrode of memory cell.The grid that grid 340 between adjacent bit lines 310 is memory cell.Between described grid 340 and Semiconductor substrate 300, also there is stacked structure 330.In the present embodiment, described stacked structure 330 is dielectric layer-the catch three level stack structure of charge layer-dielectric layer.Described word line 350 is connected the grid of memory cell 340.Described bit line 310 normally forms by the method for Implantation, and therefore, described bit line 310 is called diffusion position line district by those skilled in the art.Described diffusion position line district has contrary conduction type with Semiconductor substrate 300.If Semiconductor substrate 300 is P type substrate, the conduction type in described diffusion position line district is N-type conduction type.
With reference to figure 5, for Fig. 3 is along the cross-sectional view of BB direction.Multiple bit lines 310 is arranged in Semiconductor substrate 300 along the direction that is parallel to word line.Semiconductor substrate between adjacent bit lines 310 forms anti-reach through region 370.The material of described anti-reach through region 370 is electrical insulation material, and described electrical insulation material can be silica, silicon nitride, carborundum or silicon oxynitride.
Described anti-reach through region 370 by injection insulate ion form, the material of described insulation ion can be oxonium ion, nitrogen ion, carbon ion, nitrogen oxide ion.The material difference of described anti-reach through region 370, the ionic species difference of corresponding Implantation.In the time that the material of anti-reach through region 370 is silica, the ion of insulation Implantation is oxonium ion; In the time that the material of anti-reach through region 370 is silicon nitride, the ion of insulation Implantation is nitrogen ion; In the time that the material of anti-reach through region 370 is carborundum, the ion of insulation Implantation is carbon ion; In the time that the material of anti-reach through region 370 is silicon oxynitride, the ion of insulation Implantation is nitrogen oxide ion.As an embodiment, the energy range of described Implantation is 10～80Kev, and dosage range is 5E14～1E16cm
-2.
Please refer to Fig. 6, for Fig. 3 is along the cross-sectional view of CC direction.Many word line 350 is formed on grid 340, and grid 340 belows are stacked structure 310.Semiconductor substrate between adjacent word line 350 is anti-reach through region 370.The degree of depth of described anti-reach through region 370 should be according to the degree of depth setting of bit line 310, and preferably, the thickness of described anti-reach through region 370 should be more than or equal to the degree of depth of described bit line 310.
The material of described anti-reach through region 370 is electrical insulation material.Conventionally in order to ensure the compact structure of the electrical insulation material forming, after insulation Implantation, need to carry out rapid thermal anneal process to the ion injecting, to activate the ion injecting, and promote described ion to be combined with the silicon of Semiconductor substrate, form fine and close electrical insulation material at anti-reach through region, effectively stop the doping ion in diffusion position line district (being bit line) by anti-reach through region, form leakage current.
It should be noted that, the present invention is by the Implantation that insulate of the Semiconductor substrate between word line and adjacent bit lines adjacent, ion to described injection is annealed, and forms anti-reach through region at adjacent word line and adjacent bit line, and the material of described anti-reach through region is electrical insulation material.Described electrical insulation material can stop the doping ion in diffusion position line district by anti-reach through region, instead of stop the doping ion diffusion in diffusing, doping district by forming groove isolation construction in the Semiconductor substrate between described adjacent word line and adjacent bit line, be due to the complex process that forms groove isolation construction, increase process costs.The electrical insulation material of described anti-reach through region can not utilize existing oxidation technology to form, because the electrical insulation material that the present invention forms need to form in Semiconductor substrate, and described electrical insulation material need to meet certain thickness, utilize existing oxidation technology, only can form electrical insulation material at semiconductor substrate surface, cannot in Semiconductor substrate, form electrical insulation material, thus cannot stop adjacent diffusion position line district doping ion pass through Semiconductor substrate.Therefore, the present invention comparatively preferably adopts the method for Implantation to form electrical insulation material at anti-reach through region.
To sum up, the invention provides the method and the memory thereof that prevent memory punch through voltage reduction, utilize the Semiconductor substrate of insulation Implantation between adjacent word line and bit line to form anti-reach through region, stop the doping ion in diffusion position line district by anti-reach through region, effectively adjacent diffusion position line is separated from, reduce the leakage current forming due to the doping ionic transfer in diffusion position line district, thereby prevented the reduction of punch through voltage between adjacent word line and adjacent bit lines.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. a method that prevents memory punch through voltage reduction, is characterized in that, comprising:
Semiconductor substrate is provided, is formed with many word lines and multiple bit lines in described Semiconductor substrate, described Semiconductor substrate and bit line have contrary conduction type;
On described word line and bit line, form mask layer, described mask layer exposes the Semiconductor substrate between adjacent word line and adjacent bit lines;
Taking described mask layer as mask, the Semiconductor substrate that described mask layer the is exposed Implantation that insulate;
The ion injecting in described Semiconductor substrate is annealed, in described Semiconductor substrate, form anti-reach through region.
2. the method that prevents memory punch through voltage reduction as claimed in claim 1, is characterized in that, the material of described anti-reach through region is electrical insulation material, and described electrical insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
3. the method that prevents memory punch through voltage reduction as claimed in claim 1, is characterized in that, the ion of described insulation Implantation is oxonium ion, nitrogen ion, carbon ion or nitrogen oxide ion.
4. the method that prevents memory punch through voltage reduction as claimed in claim 1, is characterized in that, the ion energy scope of described insulation Implantation is 10～80Kev, and dosage range is 5E14～1E16cm
-2.
5. the method that prevents memory punch through voltage reduction as claimed in claim 1, is characterized in that, described mask layer is photoresist layer, silicon nitride layer or silicon oxide layer.
6. the method that prevents memory punch through voltage reduction as claimed in claim 1, is characterized in that, before the ion injecting is annealed, also comprises in described Semiconductor substrate:
Carry out etching technics, remove described mask layer.
7. the method that prevents memory punch through voltage reduction as claimed in claim 1, is characterized in that, described in be annealed into rapid thermal anneal process, annealing region is 400～1050 degrees Celsius, annealing time is 10～120 seconds, N
2range of flow is 200～1500sccm.
8. a memory, is characterized in that, comprising:
Semiconductor substrate, has many word lines and multiple bit lines in described Semiconductor substrate, it is characterized in that, described Semiconductor substrate and bit line have contrary conduction type;
Semiconductor substrate between adjacent word line and adjacent bit line is anti-reach through region, and the material of described anti-reach through region is electrical insulation material, described anti-reach through region by injection insulate ion form.
9. memory as claimed in claim 8, is characterized in that, described electrical insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
10. memory as claimed in claim 8, is characterized in that, described insulation ion is oxonium ion, nitrogen ion, carbon ion or nitrogen oxide ion.
11. memories as claimed in claim 8, is characterized in that, the Implantation Energy scope of described insulation ion is 10～80Kev, and implantation dosage scope is 5E14～1E16cm
-2.
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| CN1434484A (en) * | 2002-01-23 | 2003-08-06 | 旺宏电子股份有限公司 | Method for removing residual polycrystalline silicon |
| US6855591B2 (en) * | 2001-06-01 | 2005-02-15 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having STI structure and method of fabricating the same |
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| US6855591B2 (en) * | 2001-06-01 | 2005-02-15 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having STI structure and method of fabricating the same |
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