CN102333212A - Bilinear two-fold upsampling method and system thereof - Google Patents
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Abstract
The invention, which belongs to the technology fields including image processing as well as video coding and decoding and the like, discloses a bilinear two-fold upsampling method and a system thereof. In the prior art, a bilinear upsampling mode has a low efficiency. According to the method, four buffer areas are applied, wherein the four buffer areas include a first buffer area, a second buffer area, a third buffer area, and a forth buffer area; a to-be-sampled image is input into the first buffer area; traversal is carried out on the to-be-sampled image as well as transverse pixel sampling, vertical pixel sampling and adjacent tetra-pixel sampling are respectively carried out on the to-be-sampled image; a transverse pixel sampling result is stored into the second buffer area, a vertical pixel sampling result is stored into the third buffer area and an adjacent tetra-pixel sampling result is stored into the fourth buffer area; and pixels in the four buffer areas are arranged interlacedly and then an image after the sampling is output. According to the invention, the method and the system are mainly utilized for carrying out bilinear two-fold upsampling processing on an image.
Description
Technical field
The invention belongs to technical fields such as image processing, coding and decoding video, be specifically related to a kind of bilinearity twice top sampling method and system.
Background technology
In recent years, along with the continuous development of image processing, video coding and decoding technology, people require increasingly high to the flexibility that appears of image and video.For example, the amplification of image is dwindled, and the Compression and Expansion of video wherein all relates to Sampling techniques up and down.Especially in scalable video, down-sampling all need be gone up in codec inside, to support the spatial domain characteristic of telescopic.
Picture up-sampling is the process that from lower resolution image, produces high-resolution, just increases image resolution ratio.The up-sampling technology has a variety of, from the simplest nearest-neighbor sampling, arrives comparatively complicated Lanczos sampling etc.Minimum and the realization easily of the operand of nearest-neighbor sampling, but effect is the poorest.The Lanczos method of sampling is the replacer of BicubicResize, can provide more precisely, sharper keen image quality, but its program is complicated, elapsed time is long.For image processing, adopting in order to improve image quality, complicacy, the method for sampling more consuming time are rational.Yet for Video Applications, the requirement of real-time, synchronism is primary.The bilinearity up-sampling is comparatively simply a kind of in the up-sampling algorithm, because its rapid speed, sample effect is better, thereby is widely used.
The output pixel value of bilinearity sampling method is the mean value of its 2 * 2 field sampled point in input picture, exactly according to around the pixel value of immediate four points through the weighted average calculation pixel value that makes new advances.The gray value of 4 pixels is at level and the enterprising row interpolation of vertical both direction around its basis.The comparison typical application occasion of bilinearity up-sampling is to carry out the twice up-sampling.Existing bilinearity top sampling method is the universal method to many times of up-samplings, adopts multiplication calculating sampling result and since multiplication calculate consuming time more, speed is slower, so sampling efficiency is lower.
Summary of the invention
To the defective that exists in the prior art, technical problem to be solved by this invention provides a kind of efficient high bilinearity twice top sampling method and system.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is following:
A kind of bilinearity twice top sampling method may further comprise the steps:
(1) four buffering areas of application are respectively first buffering area, second buffering area, the 3rd buffering area and the 4th buffering area;
(2) will treat that sampled images is input to first buffering area;
(3) traversal is treated sampled images, treats sampled images respectively and carries out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling; Deposit the pixels across sampled result in second buffering area, deposit vertical pixel sampling result in the 3rd buffering area, deposit the adjacent four pixels sampled result in the 4th buffering area;
(4) pixel in four buffering areas is interlocked arrange, output sampling back image.
A kind of bilinearity twice up-sampling system comprises
Be used to apply for the buffer storage of buffering area, four buffering areas of said buffer storage application are respectively first buffering area, second buffering area, the 3rd buffering area and the 4th buffering area; Said first buffering area is used for buffer memory and treats sampled images; Said second buffering area is used for buffer memory pixels across sampling gained pixel; Said the 3rd buffering area is used for the vertical pixel sampling gained of buffer memory pixel, and said the 4th buffering area is used for buffer memory adjacent four pixels sampling gained pixel;
Be used for to treat that sampled images is input to the input unit of first buffering area;
Be used to treat sampled images and carry out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling; And deposit the pixels across sampled result in second buffering area; Deposit vertical pixel sampling result in the 3rd buffering area, the adjacent four pixels sampled result is deposited in the sampling apparatus of the 4th buffering area;
Be used for four buffering area pixels are interlocked and arrange, the output device of output sampling back image.
The method of the invention and system; Through treating that sampled images carries out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling; And sampled result deposited in the different buffering areas; The mode of pixel in staggered again four buffering areas of arranging has improved the efficient of image bilinearity twice up-sampling greatly.And, in sampling process,, replaced multiplication calculating, thereby reduced computing time through calculating the mode of neighbor mean value, accelerated sample rate.
Description of drawings
Fig. 1 is the structured flowchart of the twice of bilinearity described in embodiment up-sampling system;
Fig. 2 is the flow chart of the twice of bilinearity described in embodiment top sampling method;
Fig. 3 is buffering area initial address 16 byte-aligned sketch mapes in the embodiment;
Fig. 4 treats sampled images pixel distribution sketch map in the embodiment;
Fig. 5 is the staggered sketch map of arranging of pixel in four buffering areas in the embodiment.
Embodiment
Describe the present invention below in conjunction with embodiment and accompanying drawing.
Fig. 1 has shown the structured flowchart of the twice of bilinearity described in this execution mode up-sampling system.This system comprises buffer storage 12, the input unit 11 and the sampling apparatus 13 that are connected with buffer storage 12, and the output device 14 that is connected with sampling apparatus 13.
Buffer storage 12 is used to apply for buffering area, applies for four buffering areas in this execution mode altogether, respectively called after first buffering area (O buffering area), second buffering area (H buffering area), the 3rd buffering area (V buffering area) and the 4th buffering area (HV buffering area).The O buffering area is used for buffer memory and treats sampled images, and the H buffering area is used for buffer memory pixels across sampling gained pixel, and the V buffering area is used for the vertical pixel sampling gained of buffer memory pixel, and the HV buffering area is used for buffer memory adjacent four pixels sampling gained pixel.
Input unit 11 is used for treating that sampled images is input to the O buffering area.
Sampling apparatus 13 is used to treat sampled images and carries out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling; And deposit the pixels across sampled result in the H buffering area; Deposit vertical pixel sampling result in the V buffering area, deposit the adjacent four pixels sampled result in the HV buffering area.
Output device 14 is used for four buffering area pixels are interlocked and arranges, output sampling back image.
Fig. 2 has shown and adopts system shown in Figure 1 to carry out the method flow diagram of bilinearity twice up-sampling.This method may further comprise the steps:
(1) buffer storage 12 is at first applied for four buffering areas, respectively called after O buffering area, H buffering area, V buffering area and HV buffering area.The size of each buffering area all is not less than the size of treating sampled images, and is 16 multiple.
After applying for four buffering areas, also comprise the operation of the initial address of each buffering area being carried out 16 byte-aligned.In this execution mode, 16 byte alignment operation adopt following mode:
For 32 application programs, at first in application during each buffering area, extra application 19 byte spaces; The initial address P of log buffer with carrying out the upwards alignment of 16 bytes after the P+4 byte, obtains Q then.For 64 application programs, when each buffering area of application, extra application 23 byte spaces; The initial address P of log buffer with carrying out the upwards alignment of 16 bytes after the P+8 byte, obtains Q.Wherein 4 bytes and 8 bytes are the size of pointer.Prolong after the end address of buffering area is corresponding, guarantee the big or small constant of buffering area.16 byte-aligned for 32 application programs, write P in the place ahead 4 bytes of Q after handling; For 64 application programs, P is write in the place ahead 8 bytes of Q.
For example, as shown in Figure 3, the original position P that establishes certain buffering area is 10, and P is moved right arrives the R position after 4 bytes, and R is 14; With 16 2 bytes of ratio mutually, arrive the Q position after 2 bytes that move right again, this moment, the current original position Q of buffering area was 16, had reached the alignment purpose.Owing to applied for 19 or 23 bytes, so the size of buffering area can remain unchanged more.
When the buffer release district, Q is deducted 4 bytes (64 application programs are 8 bytes) obtain P, discharge P and get final product.
(2) input unit 11 will treat that sampled images (original image) is input to the O buffering area, as the up-sampling source data.
(3) sampling apparatus 13 traversals are treated sampled images, treat sampled images respectively and carry out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling.Deposit the pixels across sampled result in the H buffering area, deposit vertical pixel sampling result in the V buffering area, deposit the adjacent four pixels sampled result in the HV buffering area.
With original image shown in Figure 4 is example, and its pixel is 10 * 10 matrixes, the crosspoint remarked pixel of row and column.The process of pixels across sampling is following: traversal is treated sampled images, and at first the mean value of calculating pixel 00 (the 0th row the 0th row pixel, the implication of the expression mode that other pixels are identical by that analogy) and pixel 01 deposits the 0th row the 0th column position in the H buffering area in; The mean value of calculating pixel 01 and pixel 02 deposits the 0th row the 1st column position in the H buffering area in then; The mean value of calculating pixel 02 and pixel 03 deposits the 0th row the 2nd column position in the H buffering area in again; By that analogy.After handling first row, handle second row with handling the identical mode of first row again, up to handling all row, the pixels across sampling finishes.The sampled result of storing in the H buffering area is as shown in the table:
| ?A(00，01) | ?A(01，02) | ?A(02，03) | ?A(03，04) | ?A(04，05) | ?A(05，06) | ?A(06，07) | ?A(07，08) | ?A(08，09) |
| A(10，11) | A(11，12) | ?A(12，13) | ?A(13，14) | ?A(14，15) | A(15，16) | ?A(16，17) | A(17，18) | ?A(18，19) |
| A(20，21) | A(21，22) | ?A(22，23) | ?A(23，24) | ?A(24，25) | A(25，26) | ?A(26，27) | A(27，28) | ?A(28，29) |
| A(30，31) | A(31，32) | ?A(32，33) | ?A(33，34) | ?A(34，35) | A(35，36) | ?A(36，37) | A(37，38) | ?A(38，39) |
| A(40，41) | A(41，42) | ?A(42，43) | ?A(43，44) | ?A(44，45) | A(45，46) | ?A(46，47) | A(47，48) | ?A(48，49) |
| A(50，51) | A(51，52) | ?A(52，53) | ?A(53，54) | ?A(54，55) | A(55，56) | ?A(56，57) | A(57，58) | ?A(58，59) |
| A(60，61) | A(61，62) | ?A(62，63) | ?A(63，64) | ?A(64，65) | A(65，66) | ?A(66，67) | A(67，68) | ?A(68，69) |
| A(70，71) | A(71，72) | ?A(72，73) | ?A(73，74) | ?A(74，75) | A(75，76) | ?A(76，77) | A(77，78) | ?A(78，79) |
| A(80，81) | A(81，82) | ?A(82，83) | ?A(83，84) | ?A(84，85) | A(85，86) | ?A(86，87) | A(87，88) | ?A(88，89) |
| A(90，91) | A(91，92) | ?A(92，93) | ?A(93，94) | ?A(94，95) | A(95，96) | ?A(96，97) | A(97，98) | ?A(98，99) |
Wherein, A representes mean value, the mean value of A (00,01) remarked pixel 00 and pixel 01, and the mean value of A (01,02) remarked pixel 01 and pixel 02, by that analogy.
Vertically the process of pixel sampling is following: traversal is treated sampled images, and at first the mean value of calculating pixel 00 and pixel 10 deposits the 0th row the 0th column position in the V buffering area in; The mean value of calculating pixel 10 and pixel 20 deposits the 1st row the 0th column position in the V buffering area in then; The mean value of calculating pixel 20 and pixel 30 deposits the 2nd row the 0th column position in the V buffering area in again; By that analogy.After handling first row, handling secondary series with handling the identical mode of first row, up to handling all row, vertically pixel sampling finishes.The sampled result of storing in the V buffering area is as shown in the table:
Wherein, A representes mean value, the mean value of A (00,10) remarked pixel 00 and pixel 10, and the mean value of A (10,20) remarked pixel 10 and pixel 20, by that analogy.
When vertical pixel sampling calculating pixel mean value, can adopt parallel averaging instruction to carry out parallel computation, can improve computational efficiency like this.For example adopt the PAVGB instruction in SSE (Streaming SIMD Extensions, single-instruction multiple-data stream (SIMD) expansion) instruction set or the SSE2 instruction set.If adopt the parallel averaging instruction of PAVGB in the SSE instruction set, then instruction can 8 pixels of Synchronous Processing; If adopt the parallel averaging instruction of PAVGB in the SSE2 instruction set, then an instruction can 16 pixels of Synchronous Processing.
The process of adjacent four pixels sampling is following: traversal is treated sampled images, and at first the mean value of calculating pixel 00, pixel 01, pixel 10 and pixel 11 deposits the 0th row the 0th column position in the HV buffering area in.So-called adjacent four pixels is meant adjacent four pixels that can constitute four summits of a square, like the pixel among Fig. 4 00, pixel 01, pixel 10 and pixel 11.The mean value of calculating pixel 01, pixel 02, pixel 11 and pixel 12 deposits the 0th row the 1st column position in the HV buffering area in then.The mean value of calculating pixel 02, pixel 03, pixel 12 and pixel 13 deposits the 0th row the 2nd column position in the HV buffering area in again.By that analogy.After handling first row and second row, handling second row and the third line with processing first row and the identical mode of second row.By that analogy, up to disposing.
Owing to carrying out pixels across when sampling, calculated the mean value of horizontal adjacent two pixels, therefore when calculating the mean value of adjacent four pixels, can utilize the result of horizontal sampling.For example, the mean value of calculating pixel 00, pixel 01, pixel 10 and pixel 11 can take out the mean value of pixel 00 and pixel 01 earlier from the H buffering area, represent with A; Take out the mean value of pixel 10 and pixel 11 again, represent with B; Then the mean value of pixel 00, pixel 01, pixel 10 and pixel 11 promptly can obtain through the mean value that calculates A and B.Like this, can accelerate computational speed.The sampled result of storing in the HV buffering area is as shown in the table:
Wherein, A representes mean value, the mean value of A (00,01,10,11) remarked pixel 00, pixel 01, pixel 10 and pixel 11, and the mean value of A (01,02,11,12) remarked pixel 01, pixel 02, pixel 11 and pixel 12, by that analogy.
When adjacent four pixels sampling calculating pixel mean value, also can adopt parallel averaging instruction to carry out parallel computation, for example adopt the parallel averaging instruction in SSE instruction set or the SSE2 instruction set.If adopt the parallel averaging instruction in the SSE instruction set, then instruction can 8 pixels of Synchronous Processing; If adopt the parallel averaging instruction in the SSE2 instruction set, then an instruction can 16 pixels of Synchronous Processing.
(4) output device 14 interlocks pixel in four buffering areas and arranges, output sampling back image.
Insert the mean value of these two pixels in the H buffering area between two neighbors of the every row of image in the O buffering area; Between two neighbors of every row, insert the mean value of these two pixels in the V buffering area, the mean value of these four pixels in the center position insertion HV of adjacent four pixels buffering area.After all arranging, the image output after obtaining to sample.
For example; As shown in Figure 5, A, B, C, D, E, F, G, H, I are original image pixels in the O buffering area, between pixel A and B, insert the mean value of pixel A and B in the H buffering area; Between pixel B and C, insert the mean value of pixel B and C in the H buffering area, by that analogy.Between pixel A and D, insert the mean value of pixel A and D in the V buffering area, the mean value of pixel D and G in the insertion V buffering area between pixel D and G, by that analogy.Enter the mean value of pixel A, B, D and E in the HV buffering area at the center position of pixel A, B, D and E, enter the mean value of pixel B, C, E and F in the HV buffering area at the center position of pixel B, C, E and F, by that analogy.
Arrange pixel in four buffering areas; Can utilize MMX (Multi Media eXtension; Multimedia extension) PUNPCKHBW in instruction set or the SSE2 instruction set, the staggered instruction of the parallel integer of PUNPCKLBW walk abreast and arrange, and can improve the efficient of pixel arrangement like this.If adopt the staggered instruction of parallel integer in the MMX instruction set, then instruction can 8 pixels of Synchronous Processing; If adopt the staggered instruction of parallel integer in the SSE2 instruction set, then an instruction can 16 pixels of Synchronous Processing.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technology thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (14)
1. bilinearity twice top sampling method may further comprise the steps:
(1) four buffering areas of application are respectively first buffering area, second buffering area, the 3rd buffering area and the 4th buffering area;
(2) will treat that sampled images is input to first buffering area;
(3) traversal is treated sampled images, treats sampled images respectively and carries out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling; Deposit the pixels across sampled result in second buffering area, deposit vertical pixel sampling result in the 3rd buffering area, deposit the adjacent four pixels sampled result in the 4th buffering area;
(4) pixel in four buffering areas is interlocked arrange, output sampling back image.
2. the method for claim 1 is characterized in that: in four buffering areas described in the step (1), the size of each buffering area is not less than the size of treating sampled images, and is 16 multiple.
3. method as claimed in claim 2 is characterized in that: step also comprises the operation of the initial address of four buffering areas being carried out 16 byte-aligned in (1).
4. method as claimed in claim 3 is characterized in that: the method for the address of each buffering area being carried out 16 byte alignment operation is following:
For 32 application programs, when each buffering area of application, extra application 19 byte spaces;
The initial address p of log buffer is with carrying out the upwards alignment of 16 bytes after p+4 the byte;
Prolong after the end address of buffering area is corresponding, guarantee the big or small constant of buffering area.
5. method as claimed in claim 3 is characterized in that: the method for the address of each buffering area being carried out 16 byte alignment operation is following:
For 64 application programs, when each buffering area of application, extra application 23 byte spaces;
The initial address p of log buffer is with carrying out the upwards alignment of 16 bytes after the P+8 byte;
Prolong after the end address of buffering area is corresponding, guarantee the big or small constant of buffering area.
6. the method for claim 1 is characterized in that: the method that the sampling of pixels across described in the step (3) is adopted is following:
Traversal is treated sampled images, treats each row pixel of sampled images, calculates the mean value of adjacent two pixels, as the pixels across sampled result.
7. the method for claim 1 is characterized in that: vertically the method that adopts of pixel sampling is following described in the step (3):
Traversal is treated sampled images, treats each row pixel of sampled images, calculates the mean value of adjacent two pixels, as vertical pixel sampling result.
8. method as claimed in claim 7 is characterized in that: the mean value of adjacent two pixels of said calculating adopts parallel averaging instruction carrying out parallel computation.
9. the method for claim 1 is characterized in that: the method that the sampling of adjacent four pixels described in the step (3) is adopted is following:
Traversal is treated sampled images, treats four adjacent pixels of sampled images, and calculating mean value is as the adjacent four pixels sampled result.
10. method as claimed in claim 6 is characterized in that: the method that the sampling of adjacent four pixels described in the step (3) is adopted is following:
Obtain the mean value A of top two pixels in the adjacent four pixels and the mean value B of following two pixels, calculate the mean value of A and B, as the mean value of adjacent four pixels.
11. method as claimed in claim 10 is characterized in that: the mean value of said adjacent four pixels adopts parallel averaging instruction carrying out parallel computation.
12., it is characterized in that: described in the step (4) that the interlock method of arranging of pixel in four buffering areas is following like the described method of one of claim 6 to 11:
Insert the mean value of these two pixels in second buffering area between two neighbors of the every row of image in first buffering area; Between two neighbors of every row, insert the mean value of these two pixels in the 3rd buffering area, insert the mean value of these four pixels in the 4th buffering area at the center position of adjacent four pixels.
13. method as claimed in claim 12 is characterized in that: saidly be: adopt the staggered instruction of parallel integer that pixel in four buffering areas walk abreast to interlock and arrange with the method for arranging of interlocking of pixel in four buffering areas.
14. a bilinearity twice up-sampling system comprises
Be used to apply for the buffer storage (12) of buffering area, four buffering areas of said buffer storage (12) application are respectively first buffering area, second buffering area, the 3rd buffering area and the 4th buffering area; Said first buffering area is used for buffer memory and treats sampled images; Said second buffering area is used for buffer memory pixels across sampling gained pixel; Said the 3rd buffering area is used for the vertical pixel sampling gained of buffer memory pixel, and said the 4th buffering area is used for buffer memory adjacent four pixels sampling gained pixel;
Be used for to treat that sampled images is input to the input unit of first buffering area (11);
Be used to treat sampled images and carry out pixels across sampling, vertically pixel sampling and adjacent four pixels sampling; And deposit the pixels across sampled result in second buffering area; Deposit vertical pixel sampling result in the 3rd buffering area, the adjacent four pixels sampled result is deposited in the sampling apparatus (13) of the 4th buffering area;
And be used for four buffering area pixels are interlocked and arrange the output device (14) of output sampling back image.
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