CN102331584A - Fast Fourier transform (FFT) processor module of acquisition equipment used for global navigation satellite system (GNSS) - Google Patents
Fast Fourier transform (FFT) processor module of acquisition equipment used for global navigation satellite system (GNSS) Download PDFInfo
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Abstract
The invention relates to an FFT processor module of acquisition equipment used for a GNSS. The FFT processor module comprises a control unit, a read only memory unit, a random access memory unit and a multi-channel selector unit, and is characterized by further comprising an input preprocessing unit, a butterfly operation unit based on CORDIC arithmetic, an output processing unit and a reverse order output unit; the control unit is respectively connected with the read only memory unit, the random access memory unit, the input preprocessing unit, the output processing unit and the reverse order output unit, and is used for controlling working sequence of the above-mentioned units. The beneficial effect of the invention is as follows the FFT processor module enables usage amount of system storage resources to be effectively reduced.
Description
Technical field
The invention belongs to the satellite navigation field, specifically, relate to the technical field of the acquisition equipment that is used for GPS.
Background technology
GPS is a kind of round-the-clock navigational system, and its guarantee aspect availability, continuity and integrity will be good more than the navigational system of single-mode.Its adopts DSSS (DSSS) technology, and data bit stream and a PRN sign indicating number that every satellite will send carry out spread spectrum coding and adopt BPSK (Binary Phase Shift Keying, binary phase shift keying) mode to be modulated to analog waveform.The PRN sign indicating number is the PN sequence of one-period property, has the auto-correlation and the their cross correlation of PN sequence.
Acquisition equipment is one of nucleus module of global navigation satellite receiver baseband system.It mainly accomplishes the correlation function of local PRN sign indicating number and satellite baseband signal.The catching method of acquisition equipment mainly contains two kinds of methods, and a kind of is serial search, and another kind is to use FFT to carry out parallel search.Because parallel search can search the Doppler shift of code phase and carrier wave simultaneously, so be widely used in digital receiver.(Fast Fourier Transform is a kind of highly effective algorithm of realizing DFT FFT), and it utilizes the symmetry principle of twiddle factor, can reduce the operand of DFT greatly in FFT in the parallel search.
Fft processor module in the existing acquisition equipment is mainly used in the computing of carrying out FFT,
Its structural principle is as shown in Figure 1, and it is mainly by base-4 butterfly processing elements, control module, and ROM unit, random-access memory unit and MUX are formed.Wherein ROM unit is used for storing the numerical value of twiddle factor; Base-4 butterfly processing elements are core components of fft processor; The structure of the base of traditional fft processor-4 butterfly processing element is as shown in Figure 2, and it is mainly by hardware multiplier, and shunt and totalizer are formed.A, B, C, D represent four data of carrying out base-4 butterfly computation respectively among the figure; And
expression is the twiddle factor that carries out base-4 butterfly computation, and A ', B ', C ', D ' are for through the data after base-4 computings.Tradition base-4 butterfly processing elements adopt hardware multiplier to realize the multiply operation of plural number, so need the real part and the imaginary part of storage twiddle factor in its corresponding ROM unit, this has increased the consumption of system to storage resources greatly.
In the global navigation satellite receiver; The existing FFT processor module is when handling, because dipper system, GPS is different with the code length of GLONASS system; Therefore need the corresponding fft processor module of configuration respectively, this has just further increased the storage resource consumption of receiver.
Summary of the invention
The objective of the invention is to take the too much deficiency of storage resources, proposed to be used for the fft processor module of the acquisition equipment of GPS in order to overcome the existing fft processor module that is used for the acquisition equipment of GPS.
To achieve these goals; Technical scheme of the present invention is: the fft processor module that is used for the acquisition equipment of GPS; Comprise control module, ROM unit, random-access memory unit, MUX unit; It is characterized in that, also comprise input pretreatment unit, butterfly processing element, output processing unit and inverted order output unit based on cordic algorithm;
Said control module is connected with the inverted order output unit with ROM unit, random-access memory unit, input pretreatment unit, output processing unit respectively, is used to control the work schedule of said units;
Said ROM unit comprises a ROM address generator and a ROM storer; The input end of said ROM address generator is connected with control module and is used to receive the control signal that control module transmits; The output terminal of said ROM address generator is connected the address of reading that is used to produce the ROM storer with the ROM storer, said ROM storer is connected with the input pretreatment unit and is used for exporting the data that the ROM storer is stored;
Said random-access memory unit comprises the address ram generator; The one RAM storer (RAM-1) and; The 2nd RAM storer (RAM-2) and a selector switch, the input end of address ram generator are connected with control module and are used to receive the control signal that control module produces, and the output terminal of said address ram generator links to each other with the input end of selector switch; The output terminal of selector switch is connected with the 2nd RAM storer with a RAM storer; In once-through operation, selector switch will select any RAM storer to carry out work, and it passes to the RAM storer in the selecteed work with the address of reading of the RAM storer that the address ram generator produces; Another input end of selector switch is connected with the output terminal of output processing unit, is used for receiving the intermediate data exported after each grade computing and it is deposited in that RAM storer in the work going.The output terminal of the one RAM storer and the 2nd RAM storer links to each other with the input end of MUX; The input data of that block RAM storer during MUX only will be worked in once-through operation are exported; The output terminal of said MUX is connected to the input pretreatment unit; The data that read out are sent into input go in the pretreatment unit, another output terminal is connected to the inverted order processing unit;
RAM-1 in the input end connection random-access memory unit of said MUX unit and the output of RAM-2 are used for receiving the data that RAM reads, and the output terminal of MUX is connected to input pretreatment unit and inverted order output unit respectively;
The input end of said input pretreatment unit receives the control signal of control module generation and the data of MUX unit and ROM unit output; Its output terminal connects the butterfly processing element based on CORDIC, pretreated data is sent in the butterfly processing element based on CORDIC gone;
The input end of said butterfly processing element based on cordic algorithm receives the related data of input pretreatment unit output; It comprises produce in the ROM unit based on the angle value of the needed twiddle factor of butterfly processing element of cordic algorithm and the time domain data exclusive disjunction intermediate data in the random-access memory unit; Output terminal based on the butterfly processing element of cordic algorithm is connected with the input end of output processing unit, and the data after computing input is sent into the output processing unit;
The input end of said output processing unit links to each other with output terminal based on the butterfly processing element of cordic algorithm; Its intermediate data after with computing is handled; Another input end of output processing unit links to each other with control module; Be used to receive control signal, an output terminal of output processing unit connects the selector switch of random-access memory unit, and it exports the intermediate data of computing to the selector switch of random-access memory unit;
The input end of said inverted order output unit is connected to the MUX unit; After a FFT computing is accomplished; MUX inputs to the inverted order processing unit according to the control signal that control module produces with data, and another input of inverted order output unit is that control module produces; The processing that the control signal that the inverted order processing unit produces according to control module is correlated with is output as the output result after the whole fft processor computing.
The invention has the beneficial effects as follows: adopt fft processor module of the present invention; Can effectively reduce the use amount of the storage resources of system; Because the present invention has adopted cordic algorithm; The angle that only need store twiddle factor so the ROM in the fft processor module need not store twiddle factor can be saved storage resources so greatly.For example use 16 to represent data; Then the traditional FFT processor respectively needs the real part and the imaginary values of 16 storage twiddle factors; But cordic algorithm only needs 16 angle values of storing twiddle factor to get final product; Can save 1/2 storage resources, carry out to save the storage resources of 1024 * 16bit under the situation of 1024 point processings.
Description of drawings
Fig. 1 is the structural representation of the fft processor mould in the existing acquisition equipment.
Fig. 2 is the structural representation of base-4 butterfly processing element of traditional fft processor.
Fig. 3 is the structural representation of the fft processor module of the acquisition equipment that is used for GPS of the present invention.
Fig. 4 is the structural representation of the butterfly processing element based on CORDIC of the present invention.
Fig. 5 is the structural representation based on the multiplier of cordic algorithm of the butterfly processing element based on cordic algorithm of the present invention.
Fig. 6 is the structural representation of device of catching of the present invention.
Embodiment
Below in conjunction with accompanying drawing and concrete embodiment the present invention is done further explanation.
As shown in Figure 3; The fft processor module that is used for the acquisition equipment of GPS; Comprise control module, ROM unit (ROM, ROM address generator), random-access memory unit (RAM1, RAM2, address ram generator; Selector switch), the MUX unit, it is characterized in that, also comprise the input pretreatment unit, based on the butterfly processing element of cordic algorithm, output processing unit and inverted order output unit;
Said control module is connected with the inverted order output unit with ROM unit, random-access memory unit, input pretreatment unit, output processing unit respectively, is used to control the work schedule of said units;
Said ROM unit comprises a ROM address generator and a ROM storer; The input end of said ROM address generator is connected with control module and is used to receive the control signal that control module transmits; The output terminal of said ROM address generator is connected the address of reading that is used to produce the ROM storer with the ROM storer, said ROM storer is connected with the input pretreatment unit and is used for exporting the data that the ROM storer is stored;
Said random-access memory unit comprises the address ram generator; The one RAM storer (RAM-1) and; The 2nd RAM storer (RAM-2) and a selector switch, the input end of address ram generator are connected with control module and are used to receive the control signal that control module produces, and the output terminal of said address ram generator links to each other with the input end of selector switch; The output terminal of selector switch is connected with the 2nd RAM storer with a RAM storer; In once-through operation, selector switch will select any RAM storer to carry out work, and it passes to the RAM storer in the selecteed work with the address of reading of the RAM storer that the address ram generator produces; Another input end of selector switch is connected with the output terminal of output processing unit, is used for receiving the intermediate data exported after each grade computing and it is deposited in that RAM storer in the work going.The output terminal of the one RAM storer and the 2nd RAM storer links to each other with the input end of MUX; The input data of that block RAM storer during MUX only will be worked in once-through operation are exported; The output terminal of said MUX is connected to the input pretreatment unit; The data that read out are sent into input go in the pretreatment unit, another output terminal is connected to the inverted order processing unit;
RAM-1 in the input end connection random-access memory unit of said MUX unit and the output of RAM-2 are used for receiving the data that RAM reads, and the output terminal of MUX is connected to input pretreatment unit and inverted order output unit respectively;
The input end of said input pretreatment unit receives the control signal of control module generation and the data of MUX unit and ROM unit output; Its output terminal connects the butterfly processing element based on CORDIC, pretreated data is sent in the butterfly processing element based on CORDIC gone;
The input end of said butterfly processing element based on cordic algorithm receives the related data of input pretreatment unit output; It comprises produce in the ROM unit based on the angle value of the needed twiddle factor of butterfly processing element of cordic algorithm and the time domain data exclusive disjunction intermediate data in the random-access memory unit; Output terminal based on the butterfly processing element of cordic algorithm is connected with the input end of output processing unit, and the data after computing input is sent into the output processing unit;
The input end of said output processing unit links to each other with output terminal based on the butterfly processing element of cordic algorithm; Its intermediate data after with computing is handled; Another input end of output processing unit links to each other with control module; Be used to receive control signal, an output terminal of output processing unit connects the selector switch of random-access memory unit, and it exports the intermediate data of computing to the selector switch of random-access memory unit;
The input end of said inverted order output unit is connected to the MUX unit; After a FFT computing is accomplished; MUX inputs to the inverted order processing unit according to the control signal that control module produces with data, and another input of inverted order output unit is that control module produces; The processing that the control signal that the inverted order processing unit produces according to control module is correlated with is output as the output result after the whole fft processor computing.
Through a concrete embodiment course of work of such scheme is done detailed description below: control module at first produces initializing signal, need carry out one that the time domain data of FFT computing inputs among RAM-1 or the RAM-2 and carry out initialization; After input is accomplished; The indicator signal that control module produces a first order computing inputs to the address ram generator respectively; The ROM address generator; Input pretreatment unit and output processing unit, the address that address ram generator and ROM address generator will need according to the address rule generation of the first order computing this moment; After first order computing finishes; The fft processor module gets into second level computing; Control module at first produces the indicator signal of second level computing and gives the address ram generator; The ROM address generator, input pretreatment unit and output processing unit, then whole fft processor module will be carried out computing according to the second level; Step according to this, accomplish the computing of level V when the fft processor module after, control module is given the inverted order output unit with the control signal of produce output result, the inverted order output unit will carry out inverted order from the data that random-access memory unit is read and handle back output.
As shown in Figure 4; Above-mentioned butterfly processing element based on CORDIC comprises the multiplier based on cordic algorithm; Totalizer; Subtracter and exchange real part and imaginary part and negate unit have used three multipliers based on cordic algorithm to accomplish the multiplication operations of twiddle factor based on the butterfly processing element of CORDIC, use four totalizers and four subtracters to accomplish the reducing that adds of butterfly computation.The butterfly processing element based on CORDIC that adopts this paper to propose carries out the FFT computing, need not carry out the complex multiplication operation, only need carry out the computing that 3 rotations and 8 complex addition can be accomplished once basic 4FFT unit.C_re among the figure, C_im, B_re, B_im, D_re, D_im represent the real part and the imaginary part of input data respectively, Phase_c, and Phase_b, Phase_d represent the angle value of the twiddle factor that carries out computing respectively, and wherein the data on A road need not carried out the operation of multiplication.
Structure based on the butterfly processing element of CORDIC is as shown in Figure 4, always has four computing paths based on the butterfly processing element of CORDIC: A road, B road, C road, D road.Wherein B road, C road and D road need at first to multiply each other with twiddle factor; Three tunnel data are at first through a multiplier based on cordic algorithm; Wherein the output terminal based on the multiplier of cordic algorithm on B road and D road links to each other with the totalizer on B road and first subtracter on D road respectively, and the output terminal based on the multiplier of cordic algorithm on C road links to each other with the subtracter on A road first adder and C road respectively.The output terminal of A road first adder and B road totalizer is connected to A road second adder and B road subtracter; The output terminal of C road subtracter is connected to C road totalizer and D road second subtracter; The output terminal of D road first subtracter is connected to exchange real part and imaginary part and negate unit; The output terminal of exchange real part and imaginary part and negate unit is connected to C road totalizer and D road second subtracter, and the output of A road and C road totalizer and B road and D road second subtracter is through output A ', B ', C ', D ' behind the one-level butterfly computation.
Mathematic(al) representation based on the butterfly processing element of CORDIC is:
A′＝(A+K
m(Y
Cm-1+δ
m-1X
Cm-12
-(m-1))+jK
m(X
Cm-1-δ
m-1Y
Cm-12
-(m-1)))+(K
m(Y
Bm-1+σ
m-1X
Bm-12
-(m-1))
+jK
m(X
Bm-1-σ
m-1Y
Bm-12
-(m-1))+K
m(Y
Dm-1+λ
m-1X
Dm-12
-(m-1))+jK
m(X
Dm-1-λ
m-1Y
Dm-12
-(m-1)))
B′＝(A-K
m(Y
Cm-1+δ
m-1X
Cm-12
-(m-1))-jK
m(X
Cm-1-δ
m-1Y
Cm-12
-(m-1)))-j(K
m(Y
Bm-1+σ
m-1X
Bm-12
-(m-1))
+jK
m(X
Bm-1-σ
m-1Y
Bm-12
-(m-1))-K
m(Y
Dm-1+λ
m-1X
Dm-12
-(m-1))-jK
m(X
Dm-1-λ
m-1Y
Dm-12
-(m-1)))
C′＝(A+K
m(Y
Cm-1+δ
m-1X
Cm-12
-(m-1))+jK
m(X
Cm-1-δ
m-1Y
Cm-12
-(m-1)))-(K
m(Y
Bm-1+σ
m-1X
Bm-12
-(m-1))
+jK
m(X
Bm-1-σ
m-1Y
Bm-12
-(m-1))+K
m(Y
Dm-1+λ
m-1D
m-12
-(m-1))+jK
m(X
Dm-1-κ
m-1Y
Dm-12
-(m-1)))
D '=(A-K
m(Y
Cm-1+ δ
M-1X
Cm-12
-(m-1))-jK
m(X
Cm-1-δ
M-1Y
Cm-12
-(m-1)))+j (K
m(Y
Bm-1+ σ
M-1X
Bm-12
-(m-1)) δ in the formula
M-1,
+jK
m(X
Bm-1-σ
m-1Y
Bm-12
-(m-1))-K
m(Y
Dm-1+λ
m-1D
m-12
-(m-1))-jK
m(X
Dm-1-λ
m-1Y
Dm-12
-(m-1)))
σ
M-1, λ
M-1Represent three sense of rotation in the different CORDIC rotation respectively, the direction of different input angle rotations is different, and A, B, C, D represent four data and the A ' of input respectively, B ', and C ', D ' is for through the data after the computing.
As shown in Figure 5, the multiplier based on cordic algorithm of above-mentioned butterfly processing element based on cordic algorithm adopts pipeline organization, be divided among the figure x; Y, three arithmetic channels of z; The x arithmetic channel is corresponding to the C_im among Fig. 4, B_im, D_im, and the y arithmetic channel is corresponding to the C_re among Fig. 4, B_re, D_re, and the z arithmetic channel is corresponding to the Phase_c among Fig. 4, Phase_b, Phase_d; Confirm the progression of streamline according to the requirement of data precision; As can be seen from the figure, each grade computing all is made up of three totalizers, two shift units and a decision device, and wherein the carry digit of the shift unit of each grade is equivalent to current progression and subtracts 1; The output that is input as x circuit-switched data at the corresponding levels and x at the corresponding levels road shift unit of each grade x road totalizer; The wherein data that are input as y at the corresponding levels road of x road shift unit, the output that is input as y circuit-switched data at the corresponding levels and y at the corresponding levels road shift unit of each grade y road totalizer, the wherein data that are input as x at the corresponding levels road of y road shift unit equally; The angle value that is input as twiddle factor of z road totalizer and the predetermined little anglec of rotation of each grade; The output terminal of z road totalizer connects decision device at the corresponding levels, and decision device is adjudicated according to the result of z road totalizer output, and the output terminal of decision device connects the totalizer on x at the corresponding levels road and y road and the totalizer on next stage z road; Decision device selects totalizer to carry out addition or subtraction, and the output of each grade x road totalizer is connected to next stage x road totalizer and next stage y road shift unit.
According to above-mentioned rule; The output of first order y road totalizer is connected to second level y road totalizer and x road, second level shift unit; The output terminal of first order z road totalizer is connected to the input end of z road, second level totalizer, and another of z road, second level totalizer is input as the predetermined little anglec of rotation 2 in the second level;
The output of y road, second level totalizer is connected to third level y road totalizer and third level x road shift unit; The output terminal of z road, second level totalizer is connected to the input end of third level z road totalizer, and another of third level z road totalizer is input as the predetermined little anglec of rotation 3 of the third level;
According to above rule; Progression n (n is a natural number) constantly increases; Output until n-1 level y road totalizer is connected to n level y road totalizer and n level x road shift unit; The output terminal of n-1 level z road totalizer is connected to the input end of n level z road totalizer, and another of n level z road totalizer is input as the predetermined little anglec of rotation n of n level.
Apparatus structure of catching as shown in Figure 6; As describing among the figure; The output terminal of AD sampling module is connected to average down sample module, and another input end of average down sample module is connected to sampling module, and its output terminal is connected to storer 1 respectively and based on the fft processor 2 of CORDIC; The output terminal of storer 1 is connected to the fft processor 1 based on CORDIC; Output terminal based on the fft processor 2 of CORDIC is connected to storer 2, and the output terminal of storer 2 is connected to gets conjugate module, and the input end of multiplier is connected to the fft processor 1 and the output terminal of getting conjugate module based on CORDIC; The output terminal of multiplier is connected to the input end of IFFT processor; The output terminal of IFFT processor is connected to the input end of frequency deviation estimating unit, and the output terminal of frequency deviation input block is connected to the input end of asking the mould module, asks the output terminal of mould module to be the output of whole acquisition equipment.
Its workflow is: at first sampling becomes digital signal to intermediate-freuqncy signal through AD; Then through average down sample module with signal down-sampling to 1024 point; Use the fft processor based on cordic algorithm of this patent introduction to carry out FFT then, the input store as a result 1 that obtains is stored, and the local simultaneously PRN sign indicating number that produces also should be through same sampling module and average down sample module; Same through fft processor based on cordic algorithm; The input store as a result 2 that obtains is stored, and the data in the storer 2 are got conjugation and multiplied each other with data in the storer 1, and the product that obtains is done the IFFT computing; The result who calculates imports frequency deviation estimating unit and carries out frequency offset estimating; When the PRN of satellite sign indicating number is identical with local PRN sign indicating number, can obtain a correlation peak, the horizontal ordinate and the ordinate at correlation peak place are code phase and Doppler shift.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these teachings disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (3)
1. the fft processor module that is used for the acquisition equipment of GPS; Comprise control module, ROM unit, random-access memory unit, MUX unit; It is characterized in that, also comprise input pretreatment unit, butterfly processing element, output processing unit and inverted order output unit based on cordic algorithm;
Said control module is connected with the inverted order output unit with ROM unit, random-access memory unit, input pretreatment unit, output processing unit respectively, is used to control the work schedule of said units;
Said ROM unit comprises a ROM address generator and a ROM storer; The input end of said ROM address generator is connected with control module and is used to receive the control signal that control module transmits; The output terminal of said ROM address generator is connected the address of reading that is used to produce the ROM storer with the ROM storer, said ROM storer is connected with the input pretreatment unit and is used for exporting the data that the ROM storer is stored;
Said random-access memory unit comprises the address ram generator; The one RAM storer (RAM-1) and; The 2nd RAM storer (RAM-2) and a selector switch, the input end of address ram generator are connected with control module and are used to receive the control signal that control module produces, and the output terminal of said address ram generator links to each other with the input end of selector switch; The output terminal of selector switch is connected with the 2nd RAM storer with a RAM storer; In once-through operation, selector switch will select any RAM storer to carry out work, and it passes to the RAM storer in the selecteed work with the address of reading of the RAM storer that the address ram generator produces; Another input end of selector switch is connected with the output terminal of output processing unit, is used for receiving the intermediate data exported after each grade computing and it is deposited in that RAM storer in the work going.The output terminal of the one RAM storer and the 2nd RAM storer links to each other with the input end of MUX; The input data of that block RAM storer during MUX only will be worked in once-through operation are exported; The output terminal of said MUX is connected to the input pretreatment unit; The data that read out are sent into input go in the pretreatment unit, another output terminal is connected to the inverted order processing unit;
RAM-1 in the input end connection random-access memory unit of said MUX unit and the output of RAM-2 are used for receiving the data that RAM reads, and the output terminal of MUX is connected to input pretreatment unit and inverted order output unit respectively;
The input end of said input pretreatment unit receives the control signal of control module generation and the data of MUX unit and ROM unit output; Its output terminal connects the butterfly processing element based on CORDIC, pretreated data is sent in the butterfly processing element based on CORDIC gone;
The input end of said butterfly processing element based on cordic algorithm receives the related data of input pretreatment unit output; It comprises produce in the ROM unit based on the angle value of the needed twiddle factor of butterfly processing element of cordic algorithm and the time domain data exclusive disjunction intermediate data in the random-access memory unit; Output terminal based on the butterfly processing element of cordic algorithm is connected with the input end of output processing unit, and the data after computing input is sent into the output processing unit;
The input end of said output processing unit links to each other with output terminal based on the butterfly processing element of cordic algorithm; Its intermediate data after with computing is handled; Another input end of output processing unit links to each other with control module; Be used to receive control signal, an output terminal of output processing unit connects the selector switch of random-access memory unit, and it exports the intermediate data of computing to the selector switch of random-access memory unit;
The input end of said inverted order output unit is connected to the MUX unit; After a FFT computing is accomplished; MUX inputs to the inverted order processing unit according to the control signal that control module produces with data, and another input of inverted order output unit is that control module produces; The processing that the control signal that the inverted order processing unit produces according to control module is correlated with is output as the output result after the whole fft processor computing.
2. the fft processor module that is used for the acquisition equipment of GPS according to claim 1; It is characterized in that; Said butterfly processing element based on CORDIC comprises the multiplier based on cordic algorithm; Totalizer; Subtracter and exchange real part and imaginary part and negate unit have used three multipliers based on cordic algorithm to accomplish the multiplication operations of twiddle factor based on the butterfly processing element of CORDIC, use four totalizers and four subtracters to accomplish the reducing that adds of butterfly computation; Above-mentioned each original paper is formed four computing paths: A road, B road, C road, D road.Wherein B road, C road and D road need at first to multiply each other with twiddle factor; Three tunnel data are at first through a multiplier based on cordic algorithm; Wherein the output terminal based on the multiplier of cordic algorithm on B road and D road links to each other with the totalizer on B road and first subtracter on D road respectively, and the output terminal based on the multiplier of cordic algorithm on C road links to each other with the subtracter on A road first adder and C road respectively.The output terminal of A road first adder and B road totalizer is connected to A road second adder and B road subtracter; The output terminal of C road subtracter is connected to C road totalizer and D road second subtracter; The output terminal of D road first subtracter is connected to exchange real part and imaginary part and negate unit; The output terminal of exchange real part and imaginary part and negate unit is connected to C road totalizer and D road second subtracter, and the output of A road and C road totalizer and B road and D road second subtracter is through output A ', B ', C ', D ' behind the one-level butterfly computation.
3. the fft processor module that is used for the acquisition equipment of GPS according to claim 2 is characterized in that, the multiplier based on cordic algorithm of above-mentioned butterfly processing element based on cordic algorithm adopts pipeline organization; Be divided into x; Y, three arithmetic channels of z, the x arithmetic channel is corresponding to C_im, B_im, D_im, and the y arithmetic channel is corresponding to C_re, B_re, D_re; The z arithmetic channel is corresponding to Phase_c, Phase_b, Phase_d; Confirm the progression of streamline according to the requirement of data precision, each grade computing all is made up of three totalizers, two shift units and a decision device, and wherein the carry digit of the shift unit of each grade is equivalent to current progression and subtracts 1; The output that is input as x circuit-switched data at the corresponding levels and x at the corresponding levels road shift unit of each grade x road totalizer; The wherein data that are input as y at the corresponding levels road of x road shift unit, the output that is input as y circuit-switched data at the corresponding levels and y at the corresponding levels road shift unit of each grade y road totalizer, the wherein data that are input as x at the corresponding levels road of y road shift unit equally; The angle value that is input as twiddle factor of z road totalizer and the predetermined little anglec of rotation of each grade; The output terminal of z road totalizer connects decision device at the corresponding levels, and decision device is adjudicated according to the result of z road totalizer output, and the output terminal of decision device connects the totalizer on x at the corresponding levels road and y road and the totalizer on next stage z road; Decision device selects totalizer to carry out addition or subtraction, and the output of each grade x road totalizer is connected to next stage x road totalizer and next stage y road shift unit.
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| CN109358349A (en) * | 2018-09-17 | 2019-02-19 | 西安开阳微电子有限公司 | A kind of satellite signal tracking method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109358349A (en) * | 2018-09-17 | 2019-02-19 | 西安开阳微电子有限公司 | A kind of satellite signal tracking method and device |
| CN109358349B (en) * | 2018-09-17 | 2023-05-09 | 西安开阳微电子有限公司 | Satellite signal capturing method and device |
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