CN102324925B - Level switching circuit for high-voltage integrated circuit - Google Patents
Level switching circuit for high-voltage integrated circuit Download PDFInfo
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Abstract
The invention relates to a level switching circuit for a high-voltage integrated circuit, which comprises a pulse generating circuit 601, a high-voltage DMOS (double-diffusion metal oxide semiconductor) transistor 602, a high-voltage DMOS transistor 603, a lower bridge arm control circuit 618, a high-voltage region 604, a quick charge level switching circuit 611 positioned in a low-voltage region and a quick charge level switching circuit 606 positioned in the high-voltage region, wherein a capacitor 622 is a parasitic capacitor of the high-voltage DMOS transistor 602, a capacitor 623 is a parasitic capacitor of the high-voltage DMOS transistor 603, an input signal 625 enters the pulse generating circuit 601 and the lower bridge control circuit 618 from an IN end of the high-voltage integrated circuit 600, and the first output end A of the pulse generating circuit 601 is connected with a grid electrode of the high-voltage DMOS transistor 602 and the input end of the rapid quick level switching circuit 611. The level switching circuit for the high-voltage integrated circuit has the characteristics that the operation is flexible, and the situation that the output pulse width is changeless when the input pulse width is little is avoided.
Description
Technical field
The present invention relates in a kind of level shifting circuit for high voltage integrated circuit, particularly high voltage integrated circuit HVIC, signal be passed to the circuit design of higher-pressure region from low-pressure area, this level shifting circuit also relates to the high pressure DMOS technology in high voltage integrated circuit.
Background technology
High voltage integrated circuit is a kind of gate driver circuit with functions such as under-voltage protection, logic controls; it is combined power electronics with semiconductor technology; replace gradually traditional discrete component, be used in more and more the driving field of IGBT, high-power MOSFET.
High voltage integrated circuit has low-pressure area and higher-pressure region, and in the high voltage integrated circuit course of work, the minimum level of its higher-pressure region need to be carried out high speed and be switched between 0～600V or 0～1200V, due to parasitic capacitance C
MExistence, the voltage of parasitic capacitance needs one period charging interval following when switching, this charging process can cause the output abnormality of high voltage integrated circuit.
Referring to Fig. 1, be existing internal structure and the peripheral cell connection figure that is applied to high voltage integrated circuit.
High voltage integrated circuit 100 is comprised of pulse generating circuit 101, high pressure DMOS pipe 102, high pressure DMOS pipe 103, lower brachium pontis control circuit 118, higher-pressure region 104, give the drain-source parasitic capacitance 122 of high pressure DMOS pipe 102 in Fig. 1, the drain-source parasitic capacitance 123 of high pressure DMOS pipe 103.
The signal input 125 input IN by high voltage integrated circuit 100 enter respectively pulse generating circuit 101 and lower brachium pontis control circuit 118,
The first output terminals A of pulse generating circuit 101 connects the grid of high pressure DMOS pipe 102,
The second output B of pulse generating circuit 101 connects the grid of high pressure DMOS pipe 103;
Pulse generating circuit 101 and lower brachium pontis control circuit 118 are powered by low-pressure area power supply 124,
The anode of low-pressure area power supply 124 is designated as VCC, and the negative terminal of low-pressure area power supply 124 is designated as GND;
The substrate of high pressure DMOS pipe 102 is connected with source electrode and receives GND, and the drain electrode of high pressure DMOS pipe 102 enters higher-pressure region 104;
The substrate of high pressure DMOS pipe 103 is connected with source electrode and meets GND, and the drain electrode of high pressure DMOS pipe 103 enters higher-pressure region 104;
One end, the negative electrode of diode 105 and the input of not gate 107 of drain electrode 104 interior contact resistances 106 in the higher-pressure region of high pressure DMOS pipe 102;
One end, the negative electrode of diode 108 and the input of not gate 110 of drain electrode 104 interior contact resistances 109 in the higher-pressure region of high pressure DMOS pipe 103;
The anode of the anode of diode 105 and diode 108 meets respectively the potential minimum VS of higher-pressure region 104;
The other end of resistance 106 and resistance 109 meets respectively the maximum potential VB of higher-pressure region 104;
The output of the output of not gate 107 and not gate 110 enters respectively first input end and second input of brachium pontis control circuit 116;
Upper brachium pontis control circuit 116 is powered by higher-pressure region 104 power supplies 119,
The anode of higher-pressure region 104 power supplies 119 is designated as VB, and the negative terminal of higher-pressure region 104 power supplies 119 is designated as VS;
The output LO of lower brachium pontis control circuit 118 connects the grid of high pressure IGBT pipe 121,
The output HO of upper brachium pontis control circuit connects the grid of high pressure IGBT pipe 120;
The emitter-base bandgap grading of high pressure IGBT pipe 121 is connected with GND,
The collector electrode of high pressure IGBT pipe 121 is connected and is connected to VS with the emitter-base bandgap grading of high pressure IGBT pipe 120;
The collector electrode of high pressure IGBT pipe 120 meets 600V or 1200V high-voltage power supply P.
The effect of described pulse generating circuit 101 is:
(1) rising edge of inputting at signal:
The first output terminals A of pulse generating circuit 101 produces a burst pulse, and the second output B of pulse generating circuit 101 keeps low level;
(2) trailing edge of inputting at signal:
The first output terminals A of pulse generating circuit 101 keeps low level; The second output B of pulse generating circuit 101 produces a burst pulse;
(3) the signal input remains on high level or low level:
The first output terminals A of pulse generating circuit 101 and the second output B keep low level.
The effect of described lower brachium pontis control circuit 118 is: at the signal of its output LO generation with the signal input inversion.
The effect of described upper brachium pontis control circuit 116 is:
(1) rising edge that is output as low level, not gate 107 when not gate 110 can make HO become high level;
(2) rising edge that is output as low level, not gate 110 when not gate 107 can make HO become low level;
(3) output when not gate 107 and not gate 110 remains on low level or high level, and HO keeps original state constant.
The operation principle of high voltage integrated circuit shown in Figure 1 is as follows:
Operating state (1): high voltage integrated circuit initially works on power, and when signal input 125 was initiated with low level, the output LO of described lower brachium pontis control circuit 118 was high level, described high pressure IGBT pipe 121 conductings; VS current potential and GND are almost identical; The first output terminals A of described pulse generating circuit 101 and the second output B are low level, high pressure DMOS pipe 102 and high pressure DMOS pipe 103 cut-off simultaneously, described high pressure DMOS pipe 102 is almost consistent with VB with the current potential of the drain electrode of high pressure DMOS pipe 103, the input that is the interior not gate 107 in higher-pressure region 104 and not gate 110 is high level simultaneously, and the output of described not gate 107 and not gate 110 is low level simultaneously; The output of described upper brachium pontis control circuit 116 keeps original state constant, when initially powering on, high voltage integrated circuit generally can first HO set be become low level, therefore upper brachium pontis control circuit is output as low level 116 this moments, and namely its voltage is almost consistent with VS, so 120 cut-offs of high pressure IGBT pipe.
Operating state (2): when signal input 125 became high level from low level, the output LO of described lower brachium pontis control circuit 118 became low level from high level, and high pressure IGBT pipe 121 becomes cut-off from conducting; The first output terminals A of described pulse generating circuit 101 produces a narrow pulse signal at the rising edge of signal input, the second output B of pulse generating circuit 101 keeps low level, and the signal of the first output terminals A makes high pressure DMOS pipe 102 conductings and high pressure DMOS pipe 103 remain offs; Due to the clamping action of diode 105, drain voltage and the VS of described high pressure DMOS pipe 102 are almost identical, namely described not gate 107 be input as low level, not gate 107 is output as high level; And the voltage of the drain electrode of high pressure DMOS pipe 103 still keeps almost consistent with VB, described not gate 110 be input as high level, not gate 110 is output as low level; Described upper brachium pontis control circuit 116 is output as high level, and namely HO voltage is almost identical with VB, and described high pressure IGBT pipe 120 becomes conducting from cut-off; The current potential of VS is varied to rapidly P from GND.
Operating state (3): when signal input 125 kept high level, the output LO of described lower brachium pontis control circuit 118 kept low level, high pressure IGBT pipe 121 remain offs; The first output terminals A of described pulse generating circuit 101 and the second output B are all low level, described high pressure DMOS pipe 102 and high pressure DMOS pipe 103 remain offs; Being input as high level, being output as low level of described not gate 107 and not gate 110; Described upper brachium pontis control circuit 116 outputs keep high level, and HO voltage is still almost identical with VB, and described high pressure IGBT pipe 120 keeps conducting; The current potential of VS remains P.
Operating state (4): when signal input 125 became low level from high level, the output LO of described lower brachium pontis control circuit 118 became high level from low level, and high pressure IGBT pipe 121 becomes conducting from cut-off; The first output terminals A of described pulse generating circuit 101 is that the second output B of low level, pulse generating circuit 101 produces a narrow pulse signal at the trailing edge of signal input, high pressure DMOS manages 102 remain offs, and the signal of the second output B makes 103 conductings of high pressure DMOS pipe; The voltage of the drain electrode of described high pressure DMOS pipe 102 still keeps almost consistent with VB, being input as high level, being output as low level of described not gate 107, and due to the clamping action of diode 108, drain voltage and the VS of described high pressure DMOS pipe 103 are almost identical, and namely described not gate 110 is input as low level, is output as high level; Thereby described upper brachium pontis control circuit 116 is output as level, and HO voltage is almost identical with VS, and described high pressure IGBT pipe 120 becomes cut-off from conducting; The current potential of VS is varied to rapidly GND from P.
The waveform of the key point of above each operating state as shown in Figure 2.
Due to high pressure DMOS pipe parasitic capacitance C
MExistence, during the conducting of high pressure DMOS pipe, drain electrode exists one to fall soon the process that rises slowly with respect to the current potential of VS, the resistance of establishing the resistance that is connected with the drain electrode of high pressure DMOS pipe is R, the timeconstantτ that charges for VS is:
τ=R×C
M，
The setting of R prevents that with characteristic and the dV/dt of high pressure DMOS pipe ability is relevant, more than being generally 10k Ω, and C
MValue determined by the characteristic of high pressure DMOS.If managing the threshold voltage of the not gate of drain electrode with high pressure DMOS is Vth, the sequential time of pulse signal, be that the ON time of high pressure DMOS pipe is T4, during the conducting of high pressure DMOS pipe drain voltage from the time that VB drops to Vth be T1, high pressure DMOS pipe when turn-offing drain voltage be T3 from the time that VS is raised to Vth, and note T3+T4=T2.:
(1) when the pulse width T 5 of signal input during greater than T2-T1, the each point waveform as shown in Figure 3, the pulse width T 6 of output signal HO is:
T6=T5-T1+T1=T5，
Namely the pulse duration of output signal is consistent with the pulse duration of signal input at this moment.
(2) when the pulse width T 5 of signal input during less than T2-T1, the each point waveform as shown in Figure 4, although the trailing edge in the signal input, the high level of B makes D become low level, and still the C of this moment is still less than Vth, i.e. the output of not gate 107 and not gate 110 is high level simultaneously, the level of output signal HO does not reverse yet, until C rises over after Vth, output signal HO just reverses, and namely the pulse width T 6 of the output signal of this moment is:
T6=T2-T1>T5，
In general, the effective pulse width T5 of signal input can not be less than the ON time T4 of high pressure DMOS pipe, the relation of T5 and T6 as shown in Figure 5, zone beyond dash area in Fig. 5, output pulse width T6 is consistent with input pulse width T5, with interior zone, output pulse width T6 remains on T2-T1 and does not change with input pulse width T5 at dash area.
Design needs according to high voltage integrated circuit, difference between T4 and T2-T1 reaches 200ns sometimes, for the high speed and high pressure integrated circuit, the uncontrollable zone of this output pulse width is harmful to, particularly in the occasion of CD-ROM drive motor, and the process of opening at motor, being generally motor applies from T4, step-length is the gradually long pulse of 20ns, if apply at the very start the pulse of T4+200ns for motor, can affect undoubtedly motor starting-up process smoothly property and can have influence on useful life of motor.
Summary of the invention
Purpose of the present invention aims to provide a kind of simple and reasonable, flexible operation, avoids the level shifting circuit that is used for high voltage integrated circuit that the changeless situation of output pulse width occurs occurring when input pulse width is very little, to overcome weak point of the prior art.
a kind of level shifting circuit for high voltage integrated circuit by this purpose design, comprise the first pulse generating circuit 601, the first high pressure DMOS pipe 602, the second high pressure DMOS pipe 603, lower brachium pontis control circuit 618, higher-pressure region 604, wherein, the first electric capacity 622 is the parasitic capacitance of the first high pressure DMOS pipe 602, the second electric capacity 623 is the parasitic capacitance of the second high pressure DMOS pipe 603, it is characterized in that also comprising the first quick charge level shifting circuit 611 that is positioned at low-pressure area and the second quick charge level shifting circuit 606 that is positioned at the higher-pressure region, input signal 625 enters the first pulse generating circuit 601 and lower brachium pontis control circuit 618 by the IN end of high voltage integrated circuit 600, the first output terminals A of the first pulse generating circuit 601 connects the grid of the first high pressure DMOS pipe 602 and the input of the first quick charge level shifting circuit 611, the second output B of the first pulse generating circuit 601 connects the grid of the second high pressure DMOS pipe 603, the first pulse generating circuit 601, lower brachium pontis control circuit 618 and the first quick charge level shifting circuit 611 are by 624 power supplies of low-pressure area power supply, and the anode of low-pressure area power supply 624 is designated as VCC, and the negative terminal of low-pressure area power supply 624 is designated as GND, the output of the first quick charge level shifting circuit 611 connects the input of the second quick charge level shifting circuit 606, the substrate of the first high pressure DMOS pipe 602 is connected with source electrode and meets GND, and the drain electrode of the first high pressure DMOS pipe 602 enters higher-pressure region 604, the drain electrode of the first high pressure DMOS pipe 602 is connected with the input of the first not gate 607, the negative electrode of the first diode 605, the output of the second quick charge level shifting circuit 606 in higher-pressure region 604, the substrate of the second high pressure DMOS pipe 603 is connected with source electrode and meets GND, and the drain electrode of the second high pressure DMOS pipe 603 enters higher-pressure region 604, the drain electrode of the second high pressure DMOS pipe 603 is connected with the input of the second not gate 610, the negative electrode of diode 608, an end of the first resistance 609 in higher-pressure region 604, the anode of the first diode 605 and diode 608 meets the potential minimum VS of higher-pressure region, the maximum potential VB of another termination higher-pressure region of the first resistance 609, the output of the first not gate 607 and the second not gate 610 enters respectively first input end and second input of brachium pontis control circuit 616, the second quick charge level shifting circuit 606 and upper brachium pontis control circuit 616 are by 619 power supplies of higher-pressure region power supply, and the anode of higher-pressure region power supply 619 is designated as VB, and the negative terminal of higher-pressure region power supply 619 is designated as VS, the output LO of lower brachium pontis control circuit connects the grid of the first high pressure IGBT pipe 621, and the output HO of upper brachium pontis control circuit connects the grid of the second high pressure IGBT pipe 620, the emitter-base bandgap grading of the first high pressure IGBT pipe 621 is connected with GND, the collector electrode of the first high pressure IGBT pipe 621 is connected and is connected to VS with the emitter-base bandgap grading of the second high pressure IGBT pipe 620, the collector electrode of the second high pressure IGBT pipe 620 meets the high-voltage power supply P of 600V or 1200V.
The first output terminals A of described the first pulse generating circuit 601 enters the input of the second pulse generating circuit 626 in the first quick charge level shifting circuit 611, and the second pulse generating circuit 626 is by 624 power supplies of low-pressure area power supply; The second output E of the second pulse generating circuit 626 connects the grid that third high is pressed DMOS pipe 627, third high presses the emitter-base bandgap grading of DMOS pipe 627 be connected with substrate and meet GND, third high is pressed the drain electrode of DMOS pipe 627 to enter the second quick charge level shifting circuit 606 and is connected the grid of PMOS pipe 630 and the negative electrode of the 3rd diode 629, the drain electrode of PMOS pipe 630 is connected with an end of the second resistance 631, and the grid of PMOS pipe 630 is connected with emitter-base bandgap grading and meets higher-pressure region maximum potential VB; The anode of the 3rd diode 629 meets higher-pressure region potential minimum VS; The other end of the second resistance 631 is connected with the drain electrode of PMOS pipe 630 and is the output of the second quick charge level shifting circuit 606.
After the present invention adopts above-mentioned technical scheme, when the first high pressure DMOS pipe 602 turn-offs, parasitic the first electric capacity 622 can be made the input of the first not gate 607 reach rapidly high level by quick charge, thereby make the current potential of the first high pressure DMOS pipe 602 fall soon fast liter, avoided in the input signal pulse duration than hour constant phenomenon of output signal width of appearance, make the output signal width fully controlled, can effectively improve stability and the useful life of institute's CD-ROM drive motor.
That the present invention has is simple and reasonable, flexible operation, avoid occurring the characteristics that the changeless situation of output pulse width occurs when input pulse width is very little.
Description of drawings
Existing internal structure and the peripheral cell connection figure that is applied to high voltage integrated circuit of Fig. 1.
The key point oscillogram of the existing high voltage integrated circuit of Fig. 2.
The existing high voltage integrated circuit of Fig. 3 is each key point oscillogram when pulse duration is wider.
The existing high voltage integrated circuit of Fig. 4 is each key point oscillogram when pulse duration is narrower.
The input of the existing high voltage integrated circuit of Fig. 5 and the graph of a relation of output pulse width.
Fig. 6 level shifting circuit figure for high voltage integrated circuit of the present invention.
Fig. 7 level shifting circuit specific embodiment for high voltage integrated circuit of the present invention
Fig. 8 high voltage integrated circuit of the present invention is each key point oscillogram when pulse duration is narrower.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
Referring to Fig. 6, a kind of level shifting circuit for high voltage integrated circuit, comprise the first pulse generating circuit 601, first high pressure DMOS pipe the 602, second high pressure DMOS pipe 603, lower brachium pontis control circuit 618, higher-pressure region 604, and the first quick charge level shifting circuit 611 and the second quick charge level shifting circuit 606 that is positioned at the higher-pressure region that are positioned at low-pressure area, wherein, the first electric capacity 622 is the parasitic capacitance of the first high pressure DMOS pipe 602, and the second electric capacity 623 is the parasitic capacitance of the second high pressure DMOS pipe 603.
Input signal 625 enters the first pulse generating circuit 601 and lower brachium pontis control circuit 618 by the IN end of high voltage integrated circuit 600, the first output terminals A of the first pulse generating circuit 601 connects the grid of the first high pressure DMOS pipe 602 and the input of the first quick charge level shifting circuit 611, and the second output B of the first pulse generating circuit 601 connects the grid of the second high pressure DMOS pipe 603; The first pulse generating circuit 601, lower brachium pontis control circuit 618 and the first quick charge level shifting circuit 611 are by 624 power supplies of low-pressure area power supply, and the anode of low-pressure area power supply 624 is designated as VCC, and the negative terminal of low-pressure area power supply 624 is designated as GND; The output of the first quick charge level shifting circuit 611 connects the input of the second quick charge level shifting circuit 606; The substrate of the first high pressure DMOS pipe 602 is connected with source electrode and meets GND, and the drain electrode of the first high pressure DMOS pipe 602 enters higher-pressure region 604; The drain electrode of the first high pressure DMOS pipe 602 is connected with the input of the first not gate 607, the negative electrode of the first diode 605, the output of the second quick charge level shifting circuit 606 in higher-pressure region 604; The substrate of the second high pressure DMOS pipe 603 is connected with source electrode and meets GND, and the drain electrode of the second high pressure DMOS pipe 603 enters higher-pressure region 604; The drain electrode of the second high pressure DMOS pipe 603 is connected with the input of the second not gate 610, the negative electrode of diode 608, an end of the first resistance 609 in higher-pressure region 604; The anode of the first diode 605 and diode 608 meets the potential minimum VS of higher-pressure region; The maximum potential VB of another termination higher-pressure region of the first resistance 609; The output of the first not gate 607 and the second not gate 610 enters respectively first input end and second input of brachium pontis control circuit 616; The second quick charge level shifting circuit 606 and upper brachium pontis control circuit 616 are by 619 power supplies of higher-pressure region power supply, and the anode of higher-pressure region power supply 619 is designated as VB, and the negative terminal of higher-pressure region power supply 619 is designated as VS; The output LO of lower brachium pontis control circuit connects the grid of the first high pressure IGBT pipe 621, and the output HO of upper brachium pontis control circuit connects the grid of the second high pressure IGBT pipe 620; The emitter-base bandgap grading of the first high pressure IGBT pipe 621 is connected with GND, the collector electrode of the first high pressure IGBT pipe 621 is connected and is connected to VS with the emitter-base bandgap grading of the second high pressure IGBT pipe 620; The collector electrode of the second high pressure IGBT pipe 620 meets the high-voltage power supply P of 600V or 1200V.
Wherein, the effect of the first pulse generating circuit 601 is:
(1) at the rising edge of input signal: the first output terminals A of the first pulse generating circuit 601 produces a burst pulse, and the second output B of the first pulse generating circuit 601 keeps low level;
(2) at the trailing edge of input signal: the first output terminals A of the first pulse generating circuit 601 keeps low level; The second output B of the first pulse generating circuit 601 produces a burst pulse;
(3) input signal remains on high level or low level: the first output terminals A of the first pulse generating circuit 601 and the second output B keep low level.
The effect of lower brachium pontis control circuit 618 is: produce the signal anti-phase with input signal at its output LO.
The effect of upper brachium pontis control circuit 616 is:
(1) rising edge that is output as low level, the first not gate 607 when the second not gate 610 can make HO become high level;
(2) rising edge that is output as low level, the second not gate 610 when the first not gate 607 can make HO become low level;
(3) output when the first not gate 607 and 610 remains on low level or high level, and HO keeps original state constant.
The function of quick charge level shifting circuit is:
(1) at the trailing edge of input signal, when namely the first high pressure DMOS pipe 602 turn-offed, the quick charge level shifting circuit showed as 0 resistance within a short time;
(2) under other states of input signal, the quick charge level shifting circuit shows as a constant resistance value.
Referring to Fig. 7, for with the first quick charge level shifting circuit 611 that is positioned at low-pressure area part in Fig. 6 be positioned at circuit diagram after quick charge level shifting circuit (higher-pressure region part) 606 is specialized, wherein, the first output terminals A of the first pulse generating circuit 601 enters the input of the second pulse generating circuit 626 in the first quick charge level shifting circuit 611, and the second pulse generating circuit 626 is by 624 power supplies of low-pressure area power supply; The second output E of the second pulse generating circuit 626 connects the grid that third high is pressed DMOS pipe 627, third high presses the emitter-base bandgap grading of DMOS pipe 627 be connected with substrate and meet GND, third high is pressed the drain electrode of DMOS pipe 627 to enter the second quick charge level shifting circuit 606 and is connected the grid of PMOS pipe 630 and the negative electrode of the 3rd diode 629, the drain electrode of PMOS pipe 630 is connected with an end of the second resistance 631, and the grid of PMOS pipe 630 is connected with emitter-base bandgap grading and meets higher-pressure region maximum potential VB; The anode of the 3rd diode 629 meets higher-pressure region potential minimum VS; The other end of the second resistance 631 is connected with the drain electrode of PMOS pipe 630 and is the output of the second quick charge level shifting circuit 606.
Wherein, electric capacity 628 is pressed the parasitic capacitance of DMOS pipe 627 for third high, and the second pulse generating circuit 626 and the first pulse generating circuit 601 functions are in full accord; The effect of quick charge level shifting circuit is as follows:
Trailing edge in the first output terminals A, the second output E of the second pulse generating circuit 626 produces a pulse signal, this signal makes third high press 627 conductings of DMOS pipe, third high is pressed the drain voltage of DMOS pipe 627 to reduce rapidly and is clamped at VS-0.7V, thereby 630 conductings of PMOS pipe make VB through rapid parasitism the first electric capacity 622 chargings to the first high pressure DMOS pipe 602 of PMOS pipe 630, be the PMOS pipe 630 suitable breadth length ratios of design, can make the conducting resistance R of PMOS pipe 630
MBe low to moderate about 10 Ω, be the timeconstantτ of parasitic the first electric capacity 622 chargings this moment
MFor:
τ
M＝R
M×C
M，
Comparable τ is little more than 1000 times, thereby accomplishes quick charge.At this moment, the waveform of each key point as shown in Figure 8, the time T 7 that rise to surpass Vth from the A trailing edge to C can be controlled at below 1ns, the output signal width can not ignored with the zone that the input signal width changes.
Claims (2)
1. level shifting circuit that is used for high voltage integrated circuit, comprise the first pulse generating circuit (601), the first high pressure DMOS pipe (602), the second high pressure DMOS pipe (603), lower brachium pontis control circuit (618), higher-pressure region (604), wherein, the first electric capacity (622) is the parasitic capacitance of the first high pressure DMOS pipe (602), the second electric capacity (623) is the parasitic capacitance of the second high pressure DMOS pipe (603), it is characterized in that also comprising the first quick charge level shifting circuit (611) that is positioned at low-pressure area and the second quick charge level shifting circuit (606) that is positioned at the higher-pressure region,
Input signal (625) enters the first pulse generating circuit (601) and lower brachium pontis control circuit (618) by the IN end of high voltage integrated circuit (600),
The first output terminals A of the first pulse generating circuit (601) connects the grid of the first high pressure DMOS pipe (602) and the input of the first quick charge level shifting circuit (611),
The second output B of the first pulse generating circuit (601) connects the grid of the second high pressure DMOS pipe (603);
The first pulse generating circuit (601), lower brachium pontis control circuit (618) and the first quick charge level shifting circuit (611) are powered by low-pressure area power supply (624),
The anode of low-pressure area power supply (624) is designated as VCC, and the negative terminal of low-pressure area power supply (624) is designated as GND;
The output of the first quick charge level shifting circuit (611) connects the input of the second quick charge level shifting circuit (606);
The substrate of the first high pressure DMOS pipe (602) is connected with source electrode and meets GND, and the drain electrode of the first high pressure DMOS pipe (602) enters higher-pressure region (604);
The drain electrode of the first high pressure DMOS pipe (602) is connected with the input of the first not gate (607), the negative electrode of the first diode (605), the output of the second quick charge level shifting circuit (606) in higher-pressure region (604);
The substrate of the second high pressure DMOS pipe (603) is connected with source electrode and meets GND, and the drain electrode of the second high pressure DMOS pipe (603) enters higher-pressure region (604);
The drain electrode of the second high pressure DMOS pipe (603) is connected with the input of the second not gate (610), the negative electrode of the second diode (608), an end of the first resistance (609) in higher-pressure region (604);
The anode of the first diode (605) and the second diode (608) meets the potential minimum VS of higher-pressure region;
The maximum potential VB of another termination higher-pressure region of the first resistance (609);
The output of the first not gate (607) and the second not gate (610) enters respectively first input end and second input of brachium pontis control circuit (616);
The second quick charge level shifting circuit (606) and upper brachium pontis control circuit (616) are powered by higher-pressure region power supply (619),
The anode of higher-pressure region power supply (619) is designated as VB, and the negative terminal of higher-pressure region power supply (619) is designated as VS;
The output LO of lower brachium pontis control circuit connects the grid of the first high pressure IGBT pipe (621), and the output HO of upper brachium pontis control circuit connects the grid of the second high pressure IGBT pipe (620);
The emitter-base bandgap grading of the first high pressure IGBT pipe (621) is connected with GND, the collector electrode of the first high pressure IGBT pipe (621) is connected and is connected to VS with the emitter-base bandgap grading of the second high pressure IGBT pipe (620);
The collector electrode of the second high pressure IGBT pipe (620) meets the high-voltage power supply P of 600V or 1200V.
2. the level shifting circuit for high voltage integrated circuit according to claim 1, it is characterized in that the first output terminals A of described the first pulse generating circuit (601) enters the input of the second pulse generating circuit (626) in the first quick charge level shifting circuit (611)
The second pulse generating circuit (626) is powered by low-pressure area power supply (624);
The second output E of the second pulse generating circuit (626) connects the grid that third high is pressed DMOS pipe (627),
Third high is pressed the emitter-base bandgap grading of DMOS pipe (627) to be connected with substrate and is met GND, and third high is pressed the drain electrode of DMOS pipe (627) to enter the second quick charge level shifting circuit (606) and connected the grid of PMOS pipe (630) and the negative electrode of the 3rd diode (629),
The drain electrode of PMOS pipe (630) is connected with an end of the second resistance (631), and the grid of PMOS pipe (630) is connected with emitter-base bandgap grading and meets higher-pressure region maximum potential VB;
The anode of the 3rd diode (629) meets higher-pressure region potential minimum VS;
The other end of the second resistance (631) is connected with the drain electrode of PMOS pipe (630) and is the output of the second quick charge level shifting circuit (606).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110177599 CN102324925B (en) | 2011-06-28 | 2011-06-28 | Level switching circuit for high-voltage integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201110177599 CN102324925B (en) | 2011-06-28 | 2011-06-28 | Level switching circuit for high-voltage integrated circuit |
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| CN102324925A CN102324925A (en) | 2012-01-18 |
| CN102324925B true CN102324925B (en) | 2013-06-26 |
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| CN 201110177599 Expired - Fee Related CN102324925B (en) | 2011-06-28 | 2011-06-28 | Level switching circuit for high-voltage integrated circuit |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105006989B (en) * | 2015-07-31 | 2017-06-23 | 广东美的制冷设备有限公司 | Intelligent power module circuit |
| CN112117999B (en) * | 2020-08-25 | 2024-07-26 | 广东美的白色家电技术创新中心有限公司 | Driving circuit and household appliance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4758726B2 (en) * | 2005-10-19 | 2011-08-31 | パナソニック株式会社 | Level shift circuit |
| JP4946572B2 (en) * | 2007-03-30 | 2012-06-06 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| JP5475970B2 (en) * | 2008-08-05 | 2014-04-16 | 株式会社日立製作所 | Level shift circuit, switching element drive circuit, and inverter device |
| CN101719764A (en) * | 2009-09-24 | 2010-06-02 | 杭州士兰微电子股份有限公司 | Level switching circuit realized based on high-voltage double-diffused metal oxide semiconductor (DMOS) |
| CN102035511B (en) * | 2010-11-02 | 2013-04-24 | 杭州士兰微电子股份有限公司 | Time-delay circuit for high-voltage integrated circuit |
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| CN102324925A (en) | 2012-01-18 |
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