CN102315836B - Clock integrated circuit - Google Patents
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- CN102315836B CN102315836B CN201010222440.3A CN201010222440A CN102315836B CN 102315836 B CN102315836 B CN 102315836B CN 201010222440 A CN201010222440 A CN 201010222440A CN 102315836 B CN102315836 B CN 102315836B
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Abstract
The invention discloses a clock circuit of an integrated circuit. The clock circuit can operate under the bearing of power variation. A supply voltage supplies power to a compensation circuit; the compensation circuit generates a compensation reference voltage; the compensation reference voltage compensates the variation of the supply voltage; and a comparison circuit compares an output of a time sequence circuit with the compensation reference voltage to determine the time sequence of a clock signal.
Description
Technical field
The invention relates to the integrated circuit with clock circuit, the variations such as its tolerable such as temperature, ground noise, power supply noise.
Background technology
The running meeting of the clock circuit of integrated circuit has variation with factors such as temperature, ground noise, power supply noises.Because these make a variation, can affect the final sequential of clock signal, the existing multinomial research phase of carrying out can, for this problem, in the situation that above-mentioned variation exists, produce more uniform clock signal.
For example, the United States Patent (USP) of Gaboury the 7th, utilizes for 142, No. 005 to increase to have the initiatively mode of buffer circuit, independent bias circuit system and the bias circuit system of load, carrys out the impact that insulating power supply fluctuates on clock signal.The impact of fluctuating on clock signal in order to reach insulating power supply, the buffer circuit of these relative complex causes the significantly increase of chip area and cost.
In another example, high voltage and both comprehensive reference voltages that produce of a voltage regulator that the running meeting of the clock circuit of integrated circuit is supplied voltage along with exceeding of being produced by a booster circuit affect.So circuit can consume a large amount of layout areas and electric current.
Therefore cause the demand, hope can solve these variation problems, but adopts more uncomplicated structure and less cost.
Summary of the invention
The present invention is to provide a kind of technology of the device with integrated circuit of clock.This integrated circuit of clock has a compensating circuit, sequence circuit and comparison circuit.This sequence circuit and this comparison circuit determine the sequential of this clock signal.
This compensating circuit provides power supply by a supply voltage.This compensating circuit produces a compensate for reference voltage, and this compensate for reference voltage is the variation of this supply voltage of compensation.This sequence circuit, it has an output of switching between reference signal, and a speed of this switching is to be decided by a time constant.This comparison circuit is an output and this compensate for reference voltage of this sequence circuit relatively.
In many different embodiment, this technology that produces compensate for reference voltage allows the omission of other circuit to save area, power supply and cost.In one embodiment, this supply voltage is not adjusted, and can in this produces the technology of compensate for reference voltage, allow the omission of voltage regulator circuit, with to comparison circuit generation reference voltage.In one embodiment, this supply voltage does not boost, and can in this produces the technology of compensate for reference voltage, allow the omission of voltage booster, so that comparison circuit is produced to reference voltage.
In one embodiment, for one first voltage that responds this supply voltage changes, this compensate for reference voltage has a second voltage and changes, and it is also little that this second voltage changes the size that this first voltage changes.It is so the example that compensate for reference voltage is used for compensating supply variation in voltage.
In one embodiment, compensate for reference voltage is the variation for compensation supply voltage and temperature.
In one embodiment, this compensating circuit comprises a current source, and it has along with this supply voltage changes and an output current of variation.In an example, this current source has along with a positive voltage of this supply voltage changes and an output current of increase.And in another example, this current source has along with a positive voltage of this supply voltage changes and an output current of minimizing.
In another embodiment, this compensating circuit comprises multiple current sources.For example, it has one first current source, along with this supply voltage changes and an output current of variation, and one second current source, the output current changing along with temperature change.
In certain embodiments, this integrated circuit of clock has more a latch circuit and produces this clock signal of this integrated circuit of clock.This latch circuit comprises the logic gate coupling alternately, the input of another logic gate coupling alternately in output and this this latch circuit of the logic gate coupling alternately in this latch circuit is coupled, and the output that this latch circuit has an input and this comparison circuit couples.
Another object of the present invention is for providing a kind of method that produces a clock signal from an integrated circuit of clock.
Produce a compensate for reference voltage, this compensate for reference voltage is the variation of this supply voltage of compensation.One sequence circuit output is switched between reference signal, and a speed of this switching is to be decided by a time constant; And a relatively output and this compensate for reference voltage of this sequence circuit, wherein this switching and this relatively determine the sequential of this clock signal.
The present invention discloses many different embodiment.
Accompanying drawing explanation
The present invention is defined by claim scope.These and other objects, feature, and embodiment, graphic being described of can arranging in pairs or groups in the chapters and sections of following execution mode, wherein:
Fig. 1 shows that one has the block schematic diagram of the integrated circuit clock circuit that is for example temperature, earthed voltage or power supply voltage variation ability to bear.
Fig. 2 A and Fig. 2 B show that one has the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, it comprises the output of a negative circuit with assessment sequence circuit, wherein Fig. 2 A have capacitive character sequence circuit with couple and Fig. 2 B has capacitive character sequence circuit and supply coupling.
Fig. 2 C shows to have the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, its and Fig. 2 category-A seemingly, but from a PTAT power supply reception power supply rather than from CTAT power supply.
Fig. 2 D shows that one has the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, and it comprises a Schmidt trigger circuit to assess the output of this sequence circuit.
Fig. 2 E shows the schematic diagram of a Schmidt trigger circuit, for example, in Fig. 2 D.
Fig. 3 A and Fig. 3 B show that one has the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, it comprises an operation amplifier circuit to carry out the level detection of sequence circuit output by output relatively and a reference value, wherein Fig. 3 A have capacitive character sequence circuit with couple and Fig. 3 B has capacitive character sequence circuit and supply coupling.
Fig. 4 A shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the PTAT current source that reduces electric current output along with the increase of temperature.
Fig. 4 B shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the CTAT current source that increases electric current output along with the increase of temperature.
Fig. 4 C shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the PTAT current source that reduces electric current output along with the increase of temperature, and it is in parallel with the load resistance of a current mirror to have more a capacitor.
Fig. 4 D is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from PMOS device.
Fig. 4 E is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from NMOS device.
Fig. 4 F is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from PMOS device.
Fig. 4 G is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from NMOS device.
Fig. 5 A shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the current source that reduces electric current output along with the increase of temperature, and the output reducing along with the increase of temperature.
Fig. 5 B shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the current source that increases electric current output along with the increase of temperature, and the output increasing along with the increase of temperature.
Fig. 5 C shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the current source that reduces electric current output along with the increase of temperature, and the output increasing along with the increase of temperature.
Fig. 5 D shows the circuit diagram as the reference signal of the level sensitive circuit of Fig. 5 C, but comprise one, has the current source that increases electric current output along with the increase of temperature.
Fig. 5 E is a variation of Fig. 5 C circuit, and wherein CTAT_I constant current source 526 is replaced by resistance R ES 524.
Fig. 6 A shows the geometric locus of one group of time and rising magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, and it produces clock sequential and can change significantly along with the change of temperature.
Fig. 6 B shows the geometric locus of one group of time and rising magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces clock sequential and substantially along with the change of temperature, does not change.
Fig. 7 A shows the geometric locus of one group of time and decline magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, and it produces clock sequential and can change significantly along with the change of temperature.
Fig. 7 B shows the geometric locus of one group of time and decline magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces clock sequential and substantially along with the change of temperature, does not change.
Fig. 8 A and Fig. 8 B show that one has the circuit diagram of the integrated circuit clock circuit to ground noise variation ability to bear, it comprises a transistor and optionally couples with ground noise, using a part for the reference signal of the level detection as the output of this sequence circuit, wherein Fig. 8 A have capacitive character sequence circuit with couple and Fig. 8 B has capacitive character sequence circuit and supply coupling.
Fig. 9 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise variation, and it produces clock sequential and can change significantly the ground noise changing along with the time.
Figure 10 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise variation, and it can produce metastable clock sequential because of the circuit in Fig. 8 in to the ground noise changing along with the time.
Figure 11 A and Figure 11 B show that one has the circuit diagram of the integrated circuit clock circuit to power supply noise variation ability to bear, the noise phase of the power supply noise shared in common of the reference signal of the level detection of the power supply noise that it comprises a transistor AND gate sequence circuit power supply and sequence circuit output, wherein Figure 11 A have capacitive character sequence circuit with couple and Figure 11 B has capacitive character sequence circuit and supply coupling.
Figure 12 shows the circuit diagram of a power circuit, and it shares identical noise phase with the power supply noise of the reference signal of the power supply noise of sequence circuit power supply and the level detection of sequence circuit output.
Figure 13 is one group of voltage and the graph of a relation of time, and it shows because as the circuit relationships in Figure 11 or Figure 12, how at sequence circuit power supply, has identical noise phase with being used between the reference signal of the level detection that sequence circuit exports.
Figure 14 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having power supply noise variation, and it can produce clock sequential in to the power supply noise significantly changing along with the time.
Figure 15 is one group of voltage and the graph of a relation of time, it shows that this clock circuit is the ability to bear how having power supply noise variation, and it can produce metastable clock sequential because of the circuit in Figure 11 and Figure 12 in to the power supply noise significantly changing along with the time.
Figure 16 A and Figure 16 B show that one has the circuit diagram of the integrated circuit clock circuit to power supply noise variation ability to bear, the noise phase of the power supply noise shared in common of the reference signal of the level detection of the power supply noise that it comprises a transistor AND gate sequence circuit power supply and sequence circuit output, similar with Figure 11, and increased commutation circuit, for example, when electric power starting, optionally to walk around this noise, tolerated circuit.
Figure 17 is the block schematic diagram that can apply the present invention and have a memory circuit of improvement integrated circuit clock circuit.
Figure 18 is a circuit diagram, and it is similar to Figure 16, shows that one has the circuit diagram of the integrated circuit clock circuit to power supply noise variation ability to bear, and more comprises commutation circuit between with reference to generator and operational amplifier.
Figure 19 A shows a circuit diagram for an illustration power circuit of clock circuit generation reference voltage for this reason, for example, be the comparison circuit of latch circuit prime.
Figure 19 B shows an icon of the reference voltage being produced by Figure 19 a-power supply circuit, demonstrates it and has strong dependence relation with supply voltage VDD.
Figure 20 A shows a circuit diagram with an illustration sequence circuit of time constant, for example, be the clock sequential that determines a clock circuit.
Figure 20 B shows an icon of the sequence circuit output being produced by Figure 20 A sequence circuit, demonstrates reference voltage and the dependence relation of supplying voltage VDD, and wherein this dependence relation is compared with a little less than coming shown in Figure 19 B.
Figure 21 is the circuit diagram of an example power circuit, and it relies on the high voltage that a voltage booster produces from a low supply voltage, and a voltage regulator circuit, thinks that clock circuit produces a reference voltage, for example, be the comparison circuit of latch circuit prime.
Figure 22 is the circuit diagram of an example improved power circuit, and it produces a reference voltage for clock circuit, wherein reference voltage variation with compensation supply voltage via a current source, and the variation with compensation temperature via another current source of this reference voltage.
Figure 23 shows that an example current source thinks the circuit diagram of reference voltage compensation supply variation in voltage.
Figure 24 shows the clock cycle and the graph of a relation of supplying voltage that change temperature, the validity of compensate for reference voltage while showing the technology of the present invention for supply variation in voltage.
Figure 25 shows that one is similar to the circuit diagram with the integrated circuit clock circuit to power supply noise variation ability to bear of Figure 16.
[main element symbol description]
102 sequence circuits
104 level switching circuits
106 latch circuits
108 feedback signals
110 clock signals
112 level switch reference value
114 sequence circuit reference values
116 produce the circuit of the noisy temperature-compensating level switching reference value of tool and sequence circuit reference value
118 circuit that optionally couple with noise
202A, 202B, 302A, 302B, 802A, 802B sequence circuit
1102A, 1102B, 1602A, 1602B sequence circuit
204A, 204B negative circuit
206,306,806,1106A, 1106B latch circuit
210A and 210B Schmidt trigger circuit
304A, 304B, 804A, 804B level switching circuit
1104A, 1104B, 1604A, 1604B level switching circuit
422,522,2122 power regulators
526,2124,2224PTAT_I current source
430,530 CTAT_I current sources
816A, 816B level switch reference circuit
1116A, 1116B sequential power supply and level switch reference value generator
1234 reference signal REF_OP
1236 power supplys
1238 metal oxide semiconductcor field effect transistors
1246,1301 sequential power supplys
1248,1302 level switch reference value
1303 power supplys and reference value
1616A, 1616B sequential power supply and level switch reference value generator
1620A, 1620B, 1620C, 1620D diverter switch
1700 integrated circuits
1712 memory arrays
1714 word line/blocks are chosen decoder and driver
1716 word lines
1718 bit line decoders
1720 bit lines
1722,1726 buses
1724 induction amplifiers and data input structure
1728 Data In-Lines
1732 DOL Data Output Line
1736 bias voltage adjustment supply electric current and voltage sources
1734 state machines and clock circuit
1902 current sources
1904,2304 current mirrors
1906,2006,2206,2306 supply voltages
1908,2012,2108,2208,2308 resistance
1910,2110,2210 reference voltages
2014 electric capacity
2016 outputs
2118 stepup transformers
2226 PTSV_I current sources
2328 operational amplifiers
Embodiment
Fig. 1 shows that one has the block schematic diagram of the integrated circuit clock circuit that is for example temperature, earthed voltage or power supply voltage variation ability to bear.
A normally loop structure of this integrated circuit clock circuit, has sequence circuit 102, level switching circuit 104 and latch circuit 106.This latch circuit 106 produce one from latch circuit 106 feedback signal to sequence circuit 102, an and clock output signal 110.This sequence circuit 102 switches between two reference signals according to a time constant.Therefore this time constant has determined the sequential of this integrated circuit clock circuit.A typical time constant example is an exponential time constant, and it is by a RC circuit or the rising of RL circuit and characterization fall time.The output of this level switching circuit monitoring sequence circuit 102, and change its output according to this sequence circuit 102 is whether enough high or low.The example of latch circuit 106 is SR bolt lock device, SRNAND bolt lock device, JK bolt lock device, lock formula SR bolt lock device, lock formula D bolt lock device, lock formula triggering bolt lock device etc.This latch circuit 106 has two stable states and switches to produce a clock output signal 110 between these two stable states.
Two reference signals that sequence circuit 102 relies on are produced by circuit 116, and it also can produce the level switching reference signal that level switching circuit 104 relies on.By simultaneously, for sequence circuit 102 produces relied on reference signal and switch reference signal for level switching circuit 104 produces relied on level, circuit 116 can be reduced to reference signal that sequence circuit 102 relies on and the noise phase of the noise signal that the level switching reference signal that relies on for level switching circuit 104 is shared.Because any noise phase is very little, the peak value of this sequence circuit 102 noise signal in reference signal that relies on and valley are that the peak value and the valley that switch the noise signal in reference signal with level switching circuit 104 level that relies on are synchronizeed.Except noise, this circuit also can compensate the variation of supply voltage substrate value.
The level that level switching circuit 104 relies on switches reference signal 112, by circuit 118, is chosen itself and level switching circuit 104 are coupled.In certain embodiments, this can maintain ground noise as a sampling, so identical ground noise can be maintained by sequence circuit 102, and the level that can be relied on by level switching circuit 104 switches reference circuit and maintained.
Although calcspar shown here can solve the variation problem of temperature, earthed voltage or supply voltage, but one in different embodiments of the invention improvement clock circuit only solve these variable parameters one of them only (for example: only for temperature noise, only for earthed voltage noise or only for supply voltage noise), or these variable parameters wherein two only (for example: only for temperature and supply voltage noise, only for temperature and earthed voltage noise or only for supply voltage and earthed voltage noise).
Fig. 2 A and Fig. 2 B show that one has the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, and it comprises the output of a negative circuit with assessment sequence circuit.
Fig. 2 A shows an embodiment, and wherein capacitor C X or CY couple with a common ground.Although do not express all possible variation in graphic, technology of the present invention comprises the sequence circuit in all embodiment with capacitor C X or CY, wherein sequence circuit can be revised as capacitor C X or CY are coupled with a common ground.
In one embodiment, capacitor C X or CY be actually a PMOS transistor have contrary end points and inverter common ground end remove couple.
Fig. 2 B shows an embodiment, and wherein capacitor C X or CY are and a common supply coupling.Although do not express all possible variation in graphic, technology of the present invention comprises the sequence circuit in all embodiment with capacitor C X or CY, wherein sequence circuit can be revised as and by capacitor C X or CY be and a common supply coupling.
In one embodiment, capacitor C X or CY are actually common power end that a PMOS transistor has contrary end points and inverter and remove and couple.
This negative circuit 204A and 204B are by a CTAT power supply or one and the power supply that is inversely proportional to of temperature, and it can reduce along with the increase of temperature, drives.
This inverter is very different from operational amplifier version.In operational amplifier version, the output of a Vref and sequence circuit (as the rise/fall of RC circuit) compares.And in inverter version, the power supply of this inverter is controlled, to change the stroke of this inverter and therefore to detect the output (as the rise/fall of RC circuit) of sequence circuit.In this inverter version, one additionally comes into one's own about the temperature relation of power supply and inverter stroke.
This inverter has advantages of following compared to operational amplifier version: the operating voltage VDD that (1) is lower; (2) less circuit size (inverter only has two metal oxide semiconductor transistors and operational amplifier has five or above metal oxide semiconductor transistor); (3) better simply design; (4) lower active electric current (inverter has a current path, and operational amplifier has two or three current paths and comprise an extra current mirror); And (5) higher operating rate (inverter has the delay in a stage, and operational amplifier has the delay in two or three stages).
This latch circuit 206 couples alternately, and the output of a logic gate like this and the input of another logic gate couple.One input of one logic gate is directly to couple with the output of another logic gate, another input of this logic gate be directly and the output of another logic gate pass through sequence circuit and level sensitive circuit and couple.
Another embodiment of Fig. 2 C display timing generator circuit.Although major part and Fig. 2 category-A are seemingly, the sequence circuit 202A of parallel placement in Fig. 2 C and 202B are by a PTAT power supply or a power supply being directly proportional to temperature, and it can increase along with the increase of temperature, drives.Although do not express all possible variation in graphic, technology of the present invention comprises the sequence circuit in all embodiment with CTAT power supply, wherein CTAT power supply can be replaced by PTAT power supply.
Similarly, although do not express all possible variation in graphic, technology of the present invention comprises the sequence circuit in all embodiment with PTAT power supply, and wherein PTAT power supply can be replaced by CTAT power supply.
Fig. 2 D shows that one has the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, and it comprises a Schmidt trigger circuit to assess the output of this sequence circuit.
Although Fig. 2 category-B seemingly, the level switching circuit 210A in Fig. 2 D and the Schmidt trigger circuit of 210B are to be driven by a CTAT power supply, and comprise the operational amplifier having by the loop positive feedback of resistance.
Fig. 2 E shows the schematic diagram of a Schmidt trigger circuit.
Fig. 3 shows that one has the circuit diagram of the integrated circuit clock circuit to temperature change ability to bear, and it comprises an operation amplifier circuit to carry out by relatively exporting with a reference value level detection that sequence circuit is exported.
Fig. 4 A shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the current source that increases electric current output along with the increase of temperature.
How the CTAT power supply signal that Fig. 4 A demonstrates dependence level sensitive circuit produces, and is shown as CTAT_REF 428 in this figure.A PTAT_I current source 426 of quantitatively exporting, can produce through resistance R ES 424 electric current being directly proportional to temperature from power regulator 422, along with the increase of temperature, increases.This power regulator 422 can be exported the temperature independent voltage of determining.This regulates power supply that certain power supply and can be along with VDD and temperature change is provided.For example, the output of this adjuster has one and can be with reference value.This Output rusults and temperature are inversely proportional to, because the pressure drop that temperature is crossed over this resistance while increasing is also to increase, and the skew of the exit point of this pressure drop lower end is to reduce.An example of this current source is shown in Fig. 4 E.
Fig. 4 B is a variation of Fig. 4 A circuit, wherein PTAT_I constant current source 426 is replaced by CTAT_I constant current source 430, and the CTAT_REF428 of the CTAT power supply signal of dependence level sensitive circuit is replaced by the PTAT_REF 432 of the PTAT power supply signal that relies on level sensitive circuit.An example of this current source is shown in Fig. 4 G.
Fig. 4 C is a variation of Fig. 4 A circuit, has a by-pass capacitor 434 in parallel with resistance R ES 424, to reduce noise.In addition, this current source comprises a current mirror.An example of this current source is shown in Fig. 4 D.
Fig. 4 D is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from PMOS device.
Fig. 4 E is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from NMOS device.
In Fig. 4 D and Fig. 4 E, this circuit is used the delta_Vg that has a same current nmos pass transistor of the temperature of being proportional between two.So delta_Vg/ resistance=PTAT_I.In Fig. 4 D and Fig. 4 E, two transistors with circle are identical.
Fig. 4 F is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from PMOS device.
Fig. 4 G is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from NMOS device.
A current feedback circuit according to reference circuit described herein is preferably because in many examples, singlely can be controlled with parameter temperature correlation, rather than two with the material relevant parameter of temperature correlation, it has different temperature associations.
Fig. 5 A shows the circuit diagram of the reference signal of level sensitive circuit, and it comprises one and has the current source that reduces electric current output along with the increase of temperature.
How the CTAT power supply signal that Fig. 5 A demonstrates dependence level sensitive circuit produces, and is shown as CTAT_REF 528 in this figure.A PTAT_I current source 526 of quantitatively exporting, can produce through resistance R ES 524 electric current being inversely proportional to temperature from power regulator 522, along with the increase of temperature, reduces.This Output rusults and temperature are inversely proportional to, because the pressure drop that temperature is crossed over this resistance while increasing is also to reduce, and the skew of the exit point of this pressure drop upper end is also to reduce.
Shown in of current source be illustrated as one and repeatedly connect current source.
Fig. 5 B, Fig. 5 C, Fig. 5 D and Fig. 5 E are other examples that produces reference voltage signal.
Fig. 5 B is a variation of Fig. 5 A circuit, wherein CTAT_I constant current source 526 is replaced by PTAT_I constant current source 530, and the CTAT_REF528 of the CTAT power supply signal of dependence level sensitive circuit is replaced by the PTAT_REF 532 of the PTAT power supply signal that relies on level sensitive circuit.
Fig. 5 C is a variation of Fig. 5 A circuit, and wherein resistance R ES 524 is replaced by diode DI0 530.An example of this current source is shown in Fig. 4 F.
Fig. 5 D is a variation of Fig. 5 A circuit, and wherein CTAT_I constant current source 526 is replaced by PTAT_I constant current source 530, and the skew of exit point moves to the pressure drop of crossing over this constant current source lower end from the pressure drop of crossing over this constant current source upper end.
Fig. 5 E is a variation of Fig. 5 C circuit, and wherein CTAT_I constant current source 526 is replaced by resistance R ES 524.
Fig. 6 A shows the geometric locus of one group of time and magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, and it produces clock sequential and can change significantly along with the change of temperature.
Fig. 6 A shows between the track region of a high temperature, a low temperature and a moderate temperature.Temperature is lower, and this sequence circuit becomes faster, and temperature is higher, and this sequence circuit becomes slower.Because the common reference signal of sequence circuit, this sequence circuit can arrive at sooner reference value when low temperature when high temperature.Therefore, the sequential of this clock circuit can be faster when high temperature when low temperature.
Fig. 6 B shows the geometric locus of one group of time and magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces clock sequential and substantially along with the change of temperature, does not change.
Fig. 6 B shows between the track region of a high temperature, a low temperature and a moderate temperature.As shown in Figure 6A, temperature is lower, and this sequence circuit becomes faster, and temperature is higher, and this sequence circuit becomes slower.But, because use different sequence circuits in Fig. 6 B, be different from the sequence circuit using in Fig. 6 A.Although sequence circuit can arrive at sooner reference value when low temperature when high temperature, the reference value of this sequence circuit is also relative higher.Therefore, the sequential of this clock circuit demonstrates very little temperature change, but causes the speed fluctuation of this clock circuit.
Fig. 7 A and Fig. 7 B are other embodiment, and it shows the rising signals in dropping signal rather than Fig. 6 A and Fig. 6 B, but still show identical time constant.
One clock signal is the dropping signal in rising signals or Fig. 7 A and Fig. 7 B in dependency graph 6A and Fig. 6 B, be according to capacitor C X or CY be with Fig. 2 A in ground couple or determine with the supply coupling in Fig. 2 B.
Fig. 8 A and Fig. 8 B show that one has the circuit diagram of the integrated circuit clock circuit to ground noise variation ability to bear, it comprises a transistor and optionally couples with ground noise, using a part for the reference signal of the level detection as this sequence circuit output.
In one embodiment, capacitor C X or CY are actually a PMOS transistor to be had contrary end points and removes and couple with common power end, and this common power supply is connected with RX or RY.
When ENX is high level, OX keeps ground connection.Afterwards, ENX becomes low level and closes NMOS; Ground noise is maintained at OX at this moment.If it is very fast that noise is precharge speed of high level; If it is very slow that noise is precharge speed of low level.This circuit makes REFX or REFY keep identical ground noise at same time.
In Fig. 8 A, this switches reference circuit reference node REFX or REFY, comprise condenser network with couple.In Fig. 8 B, this switches reference circuit reference node REFX or REFY, comprises condenser network and supply coupling.
In different embodiment, level switches reference circuit 816A and can be two groups of different circuit with 816B or be shared with 804B by sequence circuit and the multiple level switching circuit 804A of parallel placement with set of circuits.
Fig. 9 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise variation, and it produces clock sequential and can change significantly the ground noise changing along with the time.
Fig. 9 shows that locus O X and OY are how by ground noise, in this figure for REF_LO signal affects.When ground noise has a peak value, this sequence circuit can start to charge to from REF_LO the program of REF_HI, causes sequence circuit only to need the less time just can charge to REF_HI from REF_LO.Therefore, this clock signal output 910 has a wider variation in this clock cycle.
When ENX is high level, OX keeps ground connection and voltage to change along with ground noise.When ENX is low level, and close NMOS, ground noise is maintained at OX.But reference level still changes along with ground noise.The worst situation be OX keep the ground noise of a high level and between charge period this reference circuit bear a negative earth level; This reference value can be low far beyond being contemplated to.Therefore a similar sampling and holding structure keep identical ground noise at REFX or REFY.
Figure 10 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise variation, and it can produce metastable clock sequential because of the circuit in Fig. 8 in to the ground noise changing along with the time.
Figure 10 shows that locus O X and OY are how by ground noise, in this figure for REF LO signal affects.When ground noise has a peak value or other change, this peak value or other change can be stored in the capacitive node REF X in Fig. 8 or REF is Y.Because ground noise is followed the trail of by sampling rear maintenance reference circuit the impact of REF_LO signal, this level sensitive circuit is the ground noise more identical with sequence circuit from level detection reference circuit.In ground noise, with this, sampled after the mode of rear maintenance, ground noise, it can continue to change, and removes and couples since then in sample circuit.Therefore, this sequence circuit from REF_LO charge in the program of REF_HI not one in advance, although there is ground noise, this sequence circuit still needs the identical time to charge to REF_HI from REF_LO.Therefore, cause this clock signal output 910 still to there is the identical clock cycle under a ground noise extensively changing.
In another embodiment, be after ground noise sampling, when discharging, this ground noise and sample circuit releasing to be coupled again, rather than when charging, this ground noise and sample circuit releasing are coupled as shown in Fig. 9 and Figure 10.This embodiment can cause extra problem because must solve the power supply noise problem that self noise power regulator produces.
(similar Fig. 2 C) in another embodiment, this sampling and holding circuit can keep power supply noise rather than ground noise.
Figure 11 A and Figure 11 B show that one has the circuit diagram of the integrated circuit clock circuit to power supply noise variation ability to bear, the noise phase of the power supply noise shared in common of the reference signal of the level detection of the power supply noise that it comprises a transistor AND gate sequence circuit power supply and sequence circuit output.
In Figure 11 A, this condenser network CX or CY and couple.In Figure 11 B, this condenser network CX or CY and power supply 1116A or 1116B couple.
Figure 12 shows the circuit diagram of a power circuit, and it shares identical noise phase with the power supply noise of the reference signal of the power supply noise of sequence circuit power supply and the level detection of sequence circuit output.
Figure 12 shows that a power supply 1236 drives an operational amplifier 1232.This operational amplifier has a reference signal REF_OP 1234 in its noninverting input.One of this REF_OP 1234 is illustrated as an energy-gap reference circuit in 1.3V.The output that one metal oxide semiconductcor field effect transistor 1238 has a logic gate and operational amplifier 1232 couples, and a drain electrode couples with power supply 1236, and one source pole is exported 1246 with sequential power supply and coupled.The output 1246 of sequential power supply is separated by resistance R 11240 with level switching reference value 1248.Level switches reference value 1248 to be separated by resistance R 21242 with the negative feedback point of operational amplifier 1232.Finally, resistance R 3 by this negative feedback point with couple.
Another embodiment is used the capacitive coupling of suspension joint node to switch noise phase identical between reference value 1248 to maintain the output 1246 of sequential power supply and level, and wherein the output 1246 of sequential power supply is suspension joint with one of level switching reference value 1248.
Although the above embodiments are especially designed in order to maintain noise phase identical between the output 1246 of sequential power supply and level switching reference value 1248, are not like this in other design.In other design, sequential power supply output 1246 and level switch between reference value 1248 for one of following reason or many persons and have different noise phase: (1) is because the configuration of crystal grain makes the close sequence circuit of reference circuit; (2) to have compared with VDD power supply be good power supply supply refusal ratio (PSRR) to the reference circuit in adjuster; And (3) even RC power supply has power regulator, because different output loadings and transformation, a noise phase difference still can maintain, and this power regulator must support larger electric current and larger output to change.
Figure 13 is one group of voltage and the graph of a relation of time, and it shows because as the circuit relationships in Figure 11 or Figure 12, how at sequence circuit power supply, has identical noise phase with being used between the reference signal of the level detection that sequence circuit exports.
The sequence circuit power supply 1301 that Figure 13 shows and be used in both power supply noises between the reference signal of level detection of sequence circuit output 1302 and there is identical noise phase.Track 1303 is positioned on track 1301 and 1302 and can shows this situation, although the size of power supply noise changes, and the peak value of the power supply noise of track 1301 and 1302 is synchronizeed with valley.
Figure 14 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having power supply noise variation, and it can produce clock sequential in to the power supply noise significantly changing along with the time.
Figure 14 shows how locus O X and OY are affected by power supply noise 1401.When power supply noise has one to decline to a great extent, this sequence circuit can start to charge to from REF_LO the program of REF_HI, causes sequence circuit only to need the less time just can charge to REF_HI from REF_LO.Similarly, when power supply noise has a peak value, the program that this sequence circuit charges to REF_HI from REF_LO can become slower, causes the more time of sequence circuit needs just can charge to REF_HI from REF_LO.These changes are to occur after the level of stable (definite value) switches reference value.Therefore, this clock signal output 1410 has a wider variation in this clock cycle.
Figure 15 is one group of voltage and the graph of a relation of time, it shows that this clock circuit is the ability to bear how having power supply noise variation, and it can produce metastable clock sequential because of the circuit in Figure 11 and Figure 12 in to the power supply noise significantly changing along with the time.
Figure 15 shows how locus O X and OY are affected by ground noise 1401.Different from Figure 14, when power supply noise 1501 has a peak value or other variation, level switches reference value and has a synchronous peak value or other variation.Although this peak value or other variation are switched reference value and power supply noise at this level, compare and have a less size, between the synchronizing characteristics of sequence circuit power supply 1501 and level switching reference value, reduced significantly the variation of clock signal.Therefore, the output 1510 of this clock signal has and still has a common clock cycle moving compared with extent in the situation that at ground noise.
Figure 16 A and Figure 16 B show that one has the circuit diagram of the integrated circuit clock circuit to power supply noise variation ability to bear, to switch the power supply of this clock.When electric power starting, if not yet reach stabilized power supply and need this VDD power supply to produce the clock to logical circuit.Logical circuit can be waited for the setup times of stabilized power supply.When reaching after stabilized power supply, this clock switches to a stabilizing clock.
In Figure 16 A, this condenser network CX or CY and couple.In Figure 16 B, this condenser network CX or CY and power supply 1616A or 1616B couple.
Figure 17 is the block schematic diagram that can apply the present invention and have a memory circuit of improvement integrated circuit clock circuit.
Figure 17 is the concise and to the point block schematic diagram of the integrated circuit 1700 that comprises a memory array 1712.One word line/block chooses decoder and driver 1714 is coupled to, and has electrical communication with it, and many word lines 1716 and character string are selected line, is therebetween to arrange along the column direction of memory cell array 1712.One bit line (OK) decoder and driver 1718 are coupled to many bit lines 1720 of arranging along the row of memory array 1712, and there is electrical communication with it, with from reading out data, or data writing extremely, in the memory cell of memory cell array 1712.Address is to see through bus 1722 to provide to word line and block selection decoder 1714 and bit line decoder 1718.Induction amplifier in square 1724 and data input structure, comprise as reading, the current source of programming and erasing mode, is to see through bus 1726 to be coupled to bit line decoder 1718.Data are the data input structures that are sent to square 1724 by the input/output end port on integrated circuit 1700 through Data In-Line 1728.In this illustrative embodiment, other circuit 1730 is also included within this integrated circuit 1700, for example general object processor or special purpose circuit, or the composite module that storage array is supported is thus to provide system-on-a-chip function.Data are by the induction amplifier in square 1724, see through DOL Data Output Line 1732, are sent to input/output terminal or the inner or outer data destination of other integrated circuit 1700 on integrated circuit 1700.State machine and improvement clock circuit (as discussed here) are in circuit 1734, to control bias voltage adjustment supply electric current and voltage source 1736.
Figure 18 is a circuit diagram, and it is similar to Figure 16, shows that one has the circuit diagram of the integrated circuit clock circuit to power supply noise variation ability to bear, and more comprises commutation circuit between with reference to generator and operational amplifier.As shown in Figure 8, switching transistor 818A is opened by signal ENX and switching transistor 818B is opened by signal ENY.Be similar to Fig. 8, from the ground noise of sequential power supply and level switching generator 1616A and 1616B, be stored among capacitive node REFX or REFY.
Slaughter 19 and Figure 20 together show by supply voltage change the clock problem causing.If a specific supply voltage changes the change quantity of time constant one correspondence that results in a clock, the change of supplying voltage can not be a problem.Unfortunately, a specific supply voltage changes the different change quantity of the time constant that results in a clock.
Figure 19 A shows a circuit diagram for an illustration power circuit of clock circuit generation reference voltage for this reason, for example, be the comparison circuit of latch circuit prime.
One current source 1902 is controlled the electric current of current mirror 1904 left sides, therefore controls the electric current of current mirror 1904 right-hand parts.This electric current causes the pressure drop from supply voltage 1906 by resistance 1908.Because the electric current by resistance 1908 is fixed according to the relation of current mirror 1904 and current source 1902, resistance 1908 is no matter the value tendency of supply voltage 1906 can the identical voltage-drop of experience.
Figure 19 B shows an icon of the reference voltage being produced by Figure 19 a-power supply circuit, demonstrates it and has strong dependence relation with supply voltage VDD.
Because resistance 1908 is no matter the value tendency of supply voltage 1906 can experience identical voltage-drop, reference voltage output V_ref 1910 is inclined to according to the change of supply voltage 1906 and rises or decline.
Figure 20 A shows a circuit diagram with an illustration sequence circuit of time constant, for example, be the clock sequential that determines a clock circuit.
Figure 20 B shows an icon of the sequence circuit output being produced by Figure 20 A sequence circuit, demonstrates reference voltage and the dependence relation of supplying voltage VDD, and wherein this dependence relation is compared with a little less than coming shown in Figure 19 B.
When VDD changes, this sequence circuit can rise towards change after supply voltage VDD, and since then change after supply voltage VDD decline.If when the resistance value of element and capacitance maintain definite value, although time constant remains unchanged, this rise and fall curve can directly be proportional to an equation of the supply voltage VDD of this change.
Relatively Figure 19 and Figure 20 can show, when supply voltage VDD changes, for example, have the VDD of an increase, and reference voltage V_ref and sequence circuit curve all increase.But when the ratio of this supply voltage changes, it is larger that the amplification of reference voltage V_ref is come compared to the amplification on time constant curve difference.This is not both and from reference voltage V_ref, tends to experience and directly follows supply voltage VDD and change, and sequence circuit curve only has its bound to tend to experience directly to follow the result that supply voltage VDD changes.A real non-theoretical physical system can't wait until that sequence circuit curve arrives its bound.Only some can approach its bound to sequence circuit curve, and whole curve in real non-theoretical physical system can change less quantity and changes to supply voltage VDD.
Figure 21 is the circuit diagram of an example power circuit, and it relies on the high voltage that a voltage booster produces from a low supply voltage, and a voltage regulator circuit, thinks that clock circuit produces a reference voltage, for example, be the comparison circuit of latch circuit prime.
In the circuit design of Figure 21, the accurate clock that self-regulation power supply imports compensates because system VDD changes the clock frequency variation causing.One voltage booster 2118 elevator system VDD to high voltages 2120.This adjuster 2122 receives this high voltage 2120 and will change steadily.Integrated circuit has reference voltage V_ref output, and it is to deduct by the pressure drop of resistance 2108 according to the output of adjuster 2122.By the pressure drop of resistance 2108, be by current source I_PTAT 2124, to be determined to produce that reference voltage V_ref compensates because the clock frequency that temperature change causes changes.
Figure 22 is the circuit diagram of an example improved power circuit, and it produces a reference voltage for clock circuit, wherein reference voltage variation with compensation supply voltage via a current source, and the variation with compensation temperature via another current source of this reference voltage.
In the circuit design of Figure 22, what in Figure 21, also have is used for the current source I_PTAT 2224 of compensation temperature variation, and another current source I_PTSV 2226 (being proportional to system VDD) is used for compensation supply variation in voltage.This extra current source I_PTSV helps the variation of compensation supply voltage VDD, and its sequence circuit curve compared to the constant that is on time has larger impact to reference voltage V_ref.The combination compensation supply voltage VDD2206 of current source I_PTAT and current source I_PTSV and the variation of temperature.The combination of current source I_PTAT and current source I_PTSV produces from supply voltage VDD 2206 passes through the pressure drop of resistance 2208, and produces reference voltage V_ref2210.
This reference voltage V_ref 2210 can have nothing to do with temperature change because using the resistance of identical kenel.
Figure 23 shows that an example current source thinks the circuit diagram of reference voltage compensation supply variation in voltage.
Electric current by resistance 2308 is determined by the voltage difference by resistance.This voltage difference is identical with the voltage of the voltage of the reverse input end of operational amplifier 2328 and the non-inverting input of operational amplifier 2328 between supply voltage VDD 2306.Voltage at the non-inverting input of operational amplifier 2328 is bias voltage BIAS 2330, and it is a fixed value voltage, for example, be the output of energy gap circuit.
So are I=(VDD-BIAS)/R by the electric current of resistance 2308.When VDD increases, the output current I_PTCP (being proportional to circuit power) of current source also increases.I_PTCP is an example of I_PTSV.
Figure 24 shows the clock cycle and the graph of a relation of supplying voltage that change temperature, the validity of compensate for reference voltage while showing the technology of the present invention for supply variation in voltage.
These data show that the technology of the present invention still maintains the time cycle between 79 nanosecond～81 nanoseconds in variation and temperature between (2.9V is to 3.6V) at system voltage in the situation that (10 ℃ to 85 ℃) change.
Figure 25 shows that one is similar to the circuit diagram with the integrated circuit clock circuit to power supply noise variation ability to bear of Figure 16.Sequence circuit 1602A and the 1602B of the parallel placement of graphic middle demonstration, level switching circuit 1604A and the 1604B of parallel placement, and a latch circuit 1606.By Vdd, provide the sequence circuit 1602A of power supply and 1602B normally to have the reverser of resistance R X or RY, self-capacitance CX or CY carry out charge or discharge, to change the output voltage at OX or OY.As shown in Figure 8, switching transistor 818A is opened by signal ENX and switching transistor 818B is opened by signal ENY.Reference voltage generator 2516A and 2516B can provide variation compensation supply voltage as Figure 22.The present embodiment comprises the diverter switch 1620C between level switching circuit 1604A (operational amplifier and reverser) and the latch circuit 1606 between different kenels, and the diverter switch 1620D between the level switching circuit 1604B of different kenels (operational amplifier and reverser) and latch circuit 1606.
Although the present invention is described with reference to embodiment, so the present invention's creation is not limited to its detailed description.Substitute mode and revise pattern and advise in previous description, and other substitute mode and modification pattern will be thought by those skilled in the art and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result person in fact with the present invention, neither depart from spiritual category of the present invention.Therefore, all these substitute modes and revise pattern and be intended to drop among the category that the present invention defines in enclose claim scope and equipollent thereof.
Claims (21)
1. an integrated circuit (IC) apparatus, comprises:
One integrated circuit of clock, produces a clock signal, comprises:
One compensating circuit, produces a compensate for reference voltage, and this compensating circuit provides power supply by a supply voltage, and this compensate for reference voltage is the variation of this supply voltage of compensation;
Sequence circuit, it has an output of switching between this compensate for reference voltage and reference level, and a speed of this switching is to be decided by a time constant; And
Comparison circuit, relatively this output of this sequence circuit and this compensate for reference voltage,
Wherein this sequence circuit and this comparison circuit determine the sequential of this clock signal.
2. device according to claim 1, wherein, for one first voltage that responds this supply voltage changes, this compensate for reference voltage has a second voltage and changes, and it is also little that this second voltage changes the size that this first voltage changes.
3. device according to claim 1, wherein this compensate for reference voltage is the compensation variation of this supply voltage and the variation of temperature.
4. device according to claim 1, wherein this compensating circuit comprises a current source, it has along with this supply voltage changes and an output current of variation.
5. device according to claim 1, wherein this compensating circuit comprises:
One first current source, it has along with this supply voltage changes and an output current of variation; And
One second current source, it has the output current changing along with temperature change.
6. device according to claim 1, wherein this compensating circuit comprises a current source, it has along with a positive voltage of this supply voltage changes and an output current of increase.
7. device according to claim 1, wherein this compensating circuit comprises a current source, it has along with a positive voltage of this supply voltage changes and an output current of minimizing.
8. device according to claim 1, wherein this supply voltage is unadjusted.
9. device according to claim 1, wherein this supply voltage does not boost.
10. device according to claim 1, wherein this integrated circuit of clock more comprises:
One latch circuit, produce this clock signal of this integrated circuit of clock, this latch circuit comprises the logic gate coupling alternately, the input of another logic gate coupling alternately in output and this latch circuit of this logic gate coupling alternately in this latch circuit is coupled, and the output that this latch circuit has an input and this comparison circuit couples.
11. 1 kinds produce the method for a clock signal, comprise from an integrated circuit of clock:
Produce a compensate for reference voltage, this compensate for reference voltage is the variation of compensation supply voltage;
One sequence circuit output is switched between this compensate for reference voltage and reference level, and a speed of this switching is to be decided by a time constant; And
Relatively this output of this sequence circuit and this compensate for reference voltage,
Wherein this switching and this relatively determine the sequential of this clock signal.
12. methods according to claim 11, wherein, for one first voltage that responds this supply voltage changes, this compensate for reference voltage has a second voltage and changes, and it is also little that this second voltage changes the size that this first voltage changes.
13. methods according to claim 11, wherein this compensate for reference voltage is the compensation variation of this supply voltage and the variation of temperature.
14. methods according to claim 11, wherein this integrated circuit of clock comprises a current source, it has along with this supply voltage changes and an output current of variation.
15. methods according to claim 11, wherein:
This compensate for reference voltage is the output current changing along with this supply voltage by changing one first current source, and produces by the output current changing along with temperature change that changes one second current source.
16. methods according to claim 11, wherein this compensate for reference voltage is that the positive voltage along with this supply voltage by changing a current source changes the output current increasing and produces.
17. methods according to claim 11, wherein this compensate for reference voltage is that the positive voltage along with this supply voltage by changing a current source changes the output current reducing and produces.
18. methods according to claim 11, wherein this supply voltage is unadjusted.
19. methods according to claim 11, wherein this supply voltage does not boost.
20. methods according to claim 11, more comprise:
From a latch circuit, produce this clock signal of this integrated circuit of clock, this latch circuit comprises the logic gate coupling alternately, the input of another logic gate coupling alternately in output and this latch circuit of the logic gate coupling alternately in this latch circuit is coupled, and this latch circuit is this comparison of response.
21. 1 kinds produce the device of a clock signal, comprise from an integrated circuit of clock:
Produce the function means of a compensate for reference voltage, this compensate for reference voltage is the variation of compensation supply voltage;
One sequence circuit is exported to the function means of switching between this compensate for reference voltage and reference level, a speed of this switching is to be decided by a time constant; And
Relatively this output of this sequence circuit and the function means of this compensate for reference voltage,
Wherein the function means of this switching and the function means of this comparison determine the sequential of this clock signal.
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| CN201010222440.3A CN102315836B (en) | 2010-07-05 | 2010-07-05 | Clock integrated circuit |
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| CN201010222440.3A CN102315836B (en) | 2010-07-05 | 2010-07-05 | Clock integrated circuit |
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| CN100350505C (en) * | 2002-07-12 | 2007-11-21 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
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| JP2005049970A (en) * | 2003-07-30 | 2005-02-24 | Renesas Technology Corp | Semiconductor integrated circuit |
| JP2007280458A (en) * | 2006-04-04 | 2007-10-25 | Toshiba Corp | Reference voltage generation circuit |
| JP4495695B2 (en) * | 2006-06-09 | 2010-07-07 | ザインエレクトロニクス株式会社 | Oscillator circuit |
| DE102007031411A1 (en) * | 2007-07-05 | 2009-01-08 | Qimonda Ag | Integrated circuit and method for reloading a circuit part of the integrated circuit |
| EP2139113A1 (en) * | 2008-06-23 | 2009-12-30 | Dialog Semiconductor GmbH | Glitch-free clock suspend and resume circuit |
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| US4234920A (en) * | 1978-11-24 | 1980-11-18 | Engineered Systems, Inc. | Power failure detection and restart system |
| US5498987A (en) * | 1994-06-20 | 1996-03-12 | Beacon Light Products, Inc. | Integratable solid state reset circuit operable over a wide temperature range |
| US6078168A (en) * | 1996-12-17 | 2000-06-20 | Sgs-Thomson Microelectronics S.A. | Parallel voltage regulator |
| CN100350505C (en) * | 2002-07-12 | 2007-11-21 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
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