CN102290038A - Liquid crystal display device and driving method thereof - Google Patents
Liquid crystal display device and driving method thereof Download PDFInfo
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- CN102290038A CN102290038A CN2011102523857A CN201110252385A CN102290038A CN 102290038 A CN102290038 A CN 102290038A CN 2011102523857 A CN2011102523857 A CN 2011102523857A CN 201110252385 A CN201110252385 A CN 201110252385A CN 102290038 A CN102290038 A CN 102290038A
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Abstract
The invention relates to a liquid crystal display device and a driving method thereof. The liquid crystal display device comprises a liquid crystal panel and a driving circuit. The driving circuit comprises a time sequence controller, a detection unit, a level shift circuit, a gate driving unit and at least one source driving unit. The time sequence controller is used for receiving an input drawing frame rate and providing at least one gate conduction signal and one source data write-in signal of different input drawing frame rates; the detection unit detects the input drawing frame rates; and the time sequence controller adjusts the working period of the source data write-in signal so that gate lines have same charging time at different input drawing frame rates, therefore, the image flicker problem can be avoided.
Description
Technical field
The invention relates to a kind of liquid crystal indicator, particularly relevant a kind of frame rate of avoiding switches liquid crystal indicator and the driving method thereof that causes film flicker.
Background technology
The gapless dynamic refresh switches (Seamless Dynamic Refresh Rate Switching, SDRRS) technology is the power conservation techniques that Intel Company proposes to be used for the liquid crystal indicator of mobile computer, when the liquid crystal indicator of mobile computer is in holding state, its frame rate (frame rate) can be from 60 hertz of (Hertz, Hz) switch to 40 Hz, to reach purpose of power saving.When yet liquid crystal indicator switches to different frame rate, can cause the duration of charging difference of liquid crystal capacitance, therefore can cause the problem of film flicker.
See also Figure 1A, it is when illustrating known liquid crystal indicator and implementing the SDRRS technology, the controlling signal sequential chart of the frame rate of 60Hz.Liquid crystal indicator is by time schedule controller (Timing Controller, T-Con) come control grid drive integrated circult (gate driver integrated circuits) and source electrode driven integrated circuit (source driver integrated circuits), by the conducting of gate drive integrated circuit control sluice polar curve, data are write source electrode line again by source electrode driven integrated circuit.N, N+1, N+2 represent respectively and N bar gate line, N+1 bar gate line, the relevant controlling signal of N+2 bar gate line among the figure.Prepare signal STH and write signal LP to be sent to source electrode driven integrated circuit by time schedule controller, gate controlling signal O is sent to the gate drive integrated circuit by time schedule controller.Represent when preparing signal STH that the time schedule controller preparation transmits data to source electrode driven integrated circuit for high levle.Represent when writing signal LP that time schedule controller is sent to source electrode driven integrated circuit with data, represent when writing signal LP that source electrode driven integrated circuit writes source electrode line with data for low level for high levle.Not conducting gate line when gate controlling signal OE is high levle, the problem that causes to write again when preventing adjacent two gate line overlapping conductings, conducting gate line when gate controlling signal OE is low level.
At first, the preparation signal STH that transmits high levle when time schedule controller is during to source electrode driven integrated circuit, expression notice source electrode driven integrated circuit is prepared and will be sent to source electrode driven integrated circuit with the data of the source electrode line of N bar gate line electric property coupling, then when writing signal LP and be high levle, time schedule controller will be sent to source electrode driven integrated circuit with the data of the source electrode line of N bar gate line electric property coupling, and time schedule controller transmits the gate controlling signal OE of high levle simultaneously to the gate drive integrated circuit, prevents the problem that writes again.Behind the Data Transfer Done, the gate controlling signal OE that time schedule controller transmits low level to the gate drive integrated circuit with conducting N bar gate line, that transmits low level simultaneously writes signal LP to source electrode driven integrated circuit, source electrode driven integrated circuit writes data with the source electrode line of N bar gate line electric property coupling and begins charging to keep data, that is to say, the duration of charging of N bar gate line be gate controlling signal OE be low level during, represent with T1.
The preparation signal STH that transmits high levle once more when time schedule controller is during to source electrode driven integrated circuit, expression notice source electrode driven integrated circuit is prepared and will be sent to source electrode driven integrated circuit with the data of the source electrode line of N+1 bar gate line electric property coupling, then when writing signal LP and be high LJ position, time schedule controller will be sent to source electrode driven integrated circuit with the data of the source electrode line of N+1 bar gate line electric property coupling, and time schedule controller transmits the gate controlling signal OE of high levle simultaneously to the gate drive integrated circuit, prevents the problem that writes again.Behind the Data Transfer Done, the gate controlling signal OE that time schedule controller transmits low level to the gate drive integrated circuit with conducting N+1 bar gate line, that transmits low level simultaneously writes signal LP to source electrode driven integrated circuit, source electrode driven integrated circuit writes data with the source electrode line of N+1 bar gate line electric property coupling and begins charging to keep data, that is to say, the duration of charging of N+1 bar gate line be gate controlling signal OE become low level during, be similarly T1.The rest may be inferred as for follow-up control timing, and this repeats no more.
See also Figure 1B, it is when illustrating known liquid crystal indicator and implementing the SDRRS technology, the controlling signal sequential chart of the frame rate of 40Hz.Prepare signal STH, to write signal LP identical with control timing and Figure 1A of gate pole controlling signal OE.The difference of Figure 1B and Figure 1A is that the frame rate of Figure 1B is reduced to 40Hz, therefore the cycle of gate controlling signal OE increases, since gate controlling signal OE be high levle during constant, represent gate controlling signal OE be low level during increase, promptly represent the duration of charging of the frame rate of 40Hz to increase, the duration of charging of the frame rate of this 40Hz is represented with T2.Because the duration of charging T2 of 40Hz frame rate is different with the duration of charging T1 of 60Hz frame rate, frame rate can cause the problem of film flicker when switching.
Existing solution is the duration of charging T1 based on the 60Hz frame rate, by increase gate controlling signal OE among Figure 1B be high levle during reduce gate controlling signal OE be low level during, make the duration of charging T2 of 40Hz frame rate foreshorten to T1, therefore no matter when frame rate is 60Hz or 40 Hz, all keep the identical duration of charging (being T1), the problem of film flicker when avoiding frame rate to switch.
Recently develop the liquid crystal indicator of GIP (gate in panel) framework, it does not adopt the above-mentioned gate drive integrated circuit that adds, but will directly be made in the circuit of shift register function equivalent in the gate drive integrated circuit on the liquid crystal panel, therefore can save the cost that uses the gate drive integrated circuit, and this circuit can be finished in the processing procedure of making gate line, source electrode line and picture element, need not extra processing procedure.Yet in the liquid crystal indicator that uses the GIP framework, if adopt above-mentioned gate controlling signal OE to do sequential control, this circuit will be very complicated so that on this liquid crystal panel the space be not enough to configuration.
Summary of the invention
A purpose of the present invention is to provide a kind of frame rate of avoiding to switch liquid crystal indicator and the driving method thereof that causes film flicker.
For achieving the above object, characteristics according to the present invention provide a kind of liquid crystal indicator, and it comprises a liquid crystal panel and one drive circuit.This liquid crystal panel comprises a plurality of gate lines and the arrangement interlaced with each other of a plurality of source electrode lines.This driving circuit is in order to drive this liquid crystal panel show image.This driving circuit comprises time schedule controller, a detecting unit, a level shift circuit, a gate drive unit and at least one source drive unit.This time schedule controller is accepted an input frame rate and is provided at least one gate conducting signal and the one source pole data of different input frame rates to write signal.This detecting unit detects this input frame rate and selector writes signal should import this gate conducting signal and this source electrode data of frame rate.This level shift circuit receives this gate conducting signal that meets this input frame rate.This gate drive unit is arranged on this liquid crystal panel, comes these gate lines of this liquid crystal panel of conducting according to this gate conducting signal.This source drive unit writes signal according to these source electrode data data is write each source electrode line.The duration of charging of each brake cable for this gate drive unit according to this gate conducting signal each gate line of conducting and this source drive unit according to these source electrode data write signal with these data write each source electrode line during, this time schedule controller be adjust these source electrode data write signal work period (duty cycle) so that should the duration of charging before this input frame rate switches and identical after the switching.
Another characteristics according to the present invention provide a kind of driving method of liquid crystal indicator, this liquid crystal indicator comprises a liquid crystal panel and one drive circuit, this liquid crystal panel comprises a plurality of gate lines and the arrangement interlaced with each other of a plurality of source electrode lines, this driving circuit comprises time schedule controller, one detecting unit, one level shift circuit, one gate drive unit is arranged on this liquid crystal panel and at least one source drive unit, and this driving method comprises: this time schedule controller is accepted an input frame rate and is provided at least one gate conducting signal and the one source pole data of different frame rates to write signal; This detecting unit detects this input frame rate and selector writes signal should import this gate conducting signal and this source electrode data of frame rate; This level shift circuit receives this gate conducting signal that meets this input frame rate; This gate drive unit comes these gate lines of this liquid crystal panel of conducting according to this gate conducting signal; And this source drive unit writes signal according to these source electrode data data is write each source electrode line, wherein the duration of charging of each brake cable for this gate conducting signal each gate line of conducting and according to these source electrode data write signal with these data write each source electrode line during, this time schedule controller be adjust these source electrode data write signal work period (duty cycle) so that should the duration of charging before this input frame rate switches and identical after the switching.
Liquid crystal indicator of the present invention and driving method thereof are by the controlling signal of this detecting unit detecting input frame rate and the corresponding input of selection frame rate, make gate line have the identical duration of charging, therefore can avoid the problem of figure picture flicker at difference input frame rate.
Description of drawings
[brief description of drawingsfig]
Figure 1A is when illustrating known liquid crystal indicator and implementing the SDRRS technology, the controlling signal sequential chart of the frame rate of 60Hz;
Figure 1B is when illustrating known liquid crystal indicator and implementing the SDRRS technology, the controlling signal sequential chart of the frame rate of 40Hz;
Fig. 2 illustrates according to liquid crystal indicator of the present invention;
Fig. 3 A is when illustrating this liquid crystal indicator enforcement SDRRS technology, the controlling signal sequential chart of 60 hertz frame rate;
Fig. 3 B is when illustrating this liquid crystal indicator enforcement SDRRS technology, the controlling signal sequential chart of 40 hertz frame rate;
Fig. 4 illustrates the embodiment of this detecting unit of Fig. 2 and the principle of detecting input frame rate thereof; And
Fig. 5 is the driving method process flow diagram that illustrates according to liquid crystal indicator of the present invention.
[primary clustering symbol description]
10 liquid crystal panels
200 time schedule controllers
202 detecting units
204 level shift circuits
206 gate drive unit
208,210,212 source drive unit
2020 comparers
2022 multiplexers
2,060 first shift scratch circuits
2,062 second shift scratch circuits
A imports frame rate
B is with reference to frame rate
The C comparative result
CLK1, CLK2, CLK3, CLK4 gate conducting signal
The G1-G2M gate line
LP writes signal
OE gate controlling signal
The S1-SN source electrode line
The S500-S540 step
STH prepares signal
STV1, STV2 gate start signal
TP source electrode data write signal.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is elaborated.
See also Fig. 2, it is to illustrate according to liquid crystal indicator of the present invention.This liquid crystal indicator comprises a liquid crystal panel 10 and an one drive circuit.This liquid crystal panel 10 comprises a plurality of gate lines G1-G2M and a plurality of source electrode lines S1-SN arrangement interlaced with each other.This driving circuit comprises time schedule controller 200, a detecting unit 202, a level shift circuit 204, a gate drive unit 206 and at least one source drive unit (with 208,210,212 expressions of source drive unit).This driving circuit is in order to drive this liquid crystal panel 10 show images.
Liquid crystal indicator of the present invention is to adopt the GIP framework, so use this gate drive unit 206 on this liquid crystal panel 10 replaces the known gate drive integrated circuit that adds.In present embodiment, this gate drive unit 206 comprises that one first shift scratch circuit 2060 and one second shift scratch circuit 2062 are made in the both sides of this liquid crystal panel 10.This first shift scratch circuit 2060 control odd number bar gate line G1, G3 ... G2M-1, this second shift scratch circuit 2062 control even number bar gate line G2, G4 ... G2M.Because adopt the GIP framework and be divided into both sides control, therefore required controlling signal comprises gate start signal STV1, STV2, gate conducting signal CLK1, CLK2, CLK3, CLK4 at least, will explain the function of each signal after a while.This level shift circuit 204 is sent to these shift scratch circuits 2060,2062 with the controlling signal of correspondence, promptly this level shift circuit 204 gate start signal STV1, gate conducting signal CLK1, CLK3 that will control odd number bar gate line is sent to this shift scratch circuit 2060, and gate start signal STV2 signal, gate conducting signal CLK2, CLK4 that this level shift circuit 204 will be controlled even number bar gate line are sent to this shift scratch circuit 2062.In addition, these time schedule controller 200 transfer source numbers of poles are according to writing signal TP to these source drive unit 206,208,210 writing with control data.
Liquid crystal indicator of the present invention does not use the gate drive integrated circuit, so its controlling signal is different with known techniques, sees also Fig. 3 A, and it is when illustrating this liquid crystal indicator enforcement SDRRS technology, the controlling signal sequential chart of 60 hertz frame rate.Represent when the source electrode data write signal TP for high levle that time schedule controller 200 is sent to source electrode driven integrated circuit 208,210,212 with data, the TP signal represents that source electrode driven integrated circuit 208,210,212 writes source electrode line S1-SN with data during for low level.Gate start signal STV1, STV2 are activation (enable) signal, when gate start signal STV1 when high levle becomes low level, activation gate conducting signal CLK1, when gate start signal STV2 when high levle becomes low level, activation gate conducting signal CLK2.Gate conducting signal CLK1-CLK4 represents conducting gate line G1-G4 respectively when being high levle.
The sequential of controlling signal is described as follows.When gate start signal STV1 is high levle, conducting gate line G1 is prepared in expression, gate start signal STV1 signal activation gate conducting signal CLK1 when high levle becomes low level is a high levle, conducting gate line G1, when gate conducting signal CLK1 is high levle, the source electrode data write signal TP process liquid crystal polar switching (being that gate conducting signal CLK1 is that high levle opisthogenesis number of poles is according to writing signal TP high levle for the first time) to prevent that liquid crystal was when a fixed voltage drove long afterwards once more high levle, be that gate conducting signal CLK1 is a high levle opisthogenesis number of poles according to writing signal TP for the second time during high levle, this time schedule controller 200 is sent to these source drive unit 206 with the data of source electrode line S1-SN, 208,210, when gate conducting signal CLK1 conducting gate line G1 (being that gate conducting signal CLK1 is high LJ position) and source electrode data write signal TP and are low level, these source drive unit 206,208,210 data with source electrode line S1-SN write source electrode line S1-SN.Last gate conducting signal CLK1 becomes not conducting gate line G1 behind the low level.In summary, gate conducting signal CLK1 conducting gate line G1 (being that gate conducting signal CLK1 is high LJ position) and according to the source electrode data write signal TP with the data of source electrode line S1-SN write source electrode line S1-SN (be source electrode data write signal TP be low level) during for the duration of charging of gate line G1, represent with T3.
When above-mentioned gate start signal STV1 is high levle, conducting gate line G1 is prepared in expression, gate start signal STV1 is that delay a period of time gate start signal STV2 is a high levle behind the high levle, conducting gate line G2 is prepared in expression, follow-up sequential control is same as described above, being gate start signal STV2 when high levle becomes low level, activation gate conducting signal CLK2 is a high levle, conducting gate line G2, when gate conducting signal CLK2 is high levle, the source electrode data write signal TP process liquid crystal polar switching (being that gate conducting signal CLK2 is that high levle opisthogenesis number of poles is according to writing signal TP high levle for the first time) to prevent that liquid crystal was when fixed voltage drove long afterwards once more high levle, be that gate conducting signal CLK2 is a high levle opisthogenesis number of poles when writing signal TP for the second time for high levle, this time schedule controller 200 is sent to these source drive unit 206 with the data of source electrode line S1-SN, 208,210, when gate conducting signal CLK2 conducting gate line G2 (being that gate conducting signal CLK2 is high LJ position) and source electrode data write signal TP and are low level, these source drive unit 206,208,210 data with source electrode line S1-SN write source electrode line S1-SN.Last gate conducting signal CLK2 becomes not conducting gate line G2 behind the low level.In summary, gate conducting signal CLK2 conducting gate line G2 (being that gate conducting signal CLK2 is a high levle) and according to the source electrode data write signal TP with the data of source electrode line S1-SN write source electrode line S1-SN (be source electrode data write signal TP be low level) during for the duration of charging of gate line G2, be similarly T3.
Then the sequential of conducting gate line G3 is as follows, gate conducting signal CLK1 signal is that to change gate conducting signal CLK3 after high levle finishes be high levle, conducting gate line G3, when gate conducting signal CLK3 is high levle, the source electrode data write signal TP process liquid crystal polar switching (being that gate conducting signal CLK3 is that high levle opisthogenesis number of poles is according to writing signal TP high levle for the first time) to prevent that liquid crystal was when fixed voltage drove long afterwards once more high levle, be that gate conducting signal CLK3 is a high levle opisthogenesis number of poles according to writing signal TP for the second time during high levle, this time schedule controller 200 is sent to these source drive unit 206 with the data of source electrode line S1-SN, 208,210, when gate conducting signal CLK3 conducting gate line G3 (being that gate conducting signal CLK3 is a high levle) and source electrode data write signal TP and are low level, these source drive unit 206,208,210 data with source electrode line S1-SN write source electrode line S1-SN.Last gate conducting signal CLK3 becomes not conducting gate line G3 behind the low level.In summary, gate conducting signal CLK3 conducting gate line G3 (being that gate conducting signal CLK3 is high LJ position) and according to the source electrode data write signal TP with the data of source electrode line S1-SN write source electrode line S1-SN (be source electrode data write signal TP be low level) during for the duration of charging of gate line G3, be similarly T3.
Then the sequential of conducting gate line G4 is as follows, gate conducting signal CLK2 is that to change gate conducting signal CLK4 after high levle finishes be high levle, conducting gate line G4, when gate conducting signal CLK4 is high levle, the source electrode data write signal TP process liquid crystal polar switching (being that gate conducting signal CLK4 is that high levle opisthogenesis number of poles is according to writing signal TP high levle for the first time) to prevent that liquid crystal was when fixed voltage drove long afterwards once more high levle, be that gate conducting signal CLK4 is a high levle opisthogenesis number of poles according to writing signal TP for the second time during high levle, this time schedule controller 200 is sent to these source drive unit 206 with the data of source electrode line S1-SN, 208,210, when gate conducting signal CLK4 conducting gate line G4 (being that gate conducting signal CLK4 is a high levle) and source electrode data write signal TP and are low level, these source drive unit 206,208,210 data with source electrode line S1-SN write source electrode line S1-SN.Last gate conducting signal CLK4 becomes not conducting gate line G4 behind the low level.In summary, gate conducting signal CLK4 conducting gate line G4 (being that gate conducting signal CLK4 is a high levle) and according to the source electrode data write signal TP with the data of source electrode line S1-SN write source electrode line S1-SN (be source electrode data write signal TP be low level) during for the duration of charging of gate line G4, be similarly T3.
Article five to eight, gate line is more in regular turn by gate conducting signal CLK1-CLK4 conducting in regular turn, and the 9th to 12 gate line is more in regular turn by gate conducting signal CLK1-CLK4 conducting in regular turn, and the rest may be inferred, and this repeats no more.
See also Fig. 3 B, it is when illustrating this liquid crystal indicator enforcement SDRRS technology, the controlling signal sequential chart of 40 hertz frame rate.The control timing of Fig. 3 B is identical with Fig. 3 A, both difference is that the frame rate of Fig. 3 B is reduced to 40Hz, therefore the source electrode data write the cycle increase of signal TP, since the source electrode data write signal TP be high levle during constant, represent the source electrode data write signal TP be low level during increase, and the source electrode data to write signal TP be low level to gate conducting signal CLK1 become low level during be duration of charging of the frame rate of 40Hz, during T4 among the figure, therefore duration of charging T4 is different with duration of charging T3, and frame rate can cause the problem of film flicker when switching.Solution of the present invention is that the duration of charging T3 of 60Hz frame rate is the basis, write the work period (duty cycle) of signal TP by source electrode data among increase Fig. 3 B, promptly increase the source electrode data write signal TP be high levle during reduce the source electrode data write signal TP be low level during, hatched example areas shown in the figure be increase high LJ position during, and with the source electrode data write signal TP be high levle and low level during deposit this time schedule controller 200 in, make the duration of charging T4 of 40Hz frame rate foreshorten to T3, therefore no matter when frame rate is 60Hz or 40 Hz, all keep the identical duration of charging (being T3), the problem of film flicker when avoiding frame rate to switch.
Please consult Fig. 2 again, because the present invention adopts the GIP framework, so this liquid crystal indicator must comprise that this detecting unit 202 detects frame rate and whether switch.In present embodiment, this detecting unit 202 is to be arranged in this time schedule controller 200.In another embodiment, this detecting unit 202 can be independent of this time schedule controller 200 and be provided with.As an input frame rate A (60Hz or 40Hz) when being input to this time schedule controller 200, this detecting unit 202 is selected this time schedule controller 200 gate start signal STV1 that meets this input frame rate A that exports according to this input frame rate A, STV2, gate conducting signal CLK1, CLK2, CLK3, CLK4 and source electrode data write signal TP, again with gate start signal STV1, STV2, gate conducting signal CLK1, CLK2, CLK3, CLK4 and source electrode data write signal TP and are sent to this level shift circuit 204 and these source drive unit 208,210,212, again by this level shift circuit 204 and these source drive unit 206,208,210 according to the sequential chart of above-mentioned Fig. 3 A and Fig. 3 B control liquid crystal panel with show image.
See also Fig. 4, its be illustrate Fig. 2 this detecting unit 202 an embodiment and detect the principle of this input frame rate A.This detecting unit 202 comprises a comparer 2020 and a multiplexer 2022.This comparer 2020 relatively should be imported frame rate A and with reference to frame rate B.This is as with reference to benchmark with reference to frame rate B, and it can be 60Hz or 40Hz, and present embodiment is example with 60Hz.After this input frame rate A inputs to this time schedule controller 200, this time schedule controller 200 produces this input frame rate A and is somebody's turn to do with reference to frame rate B (60Hz) to this comparer 2020, if this input frame rate A is 60Hz, then a comparative result C of this comparer 2020 is 1, and this multiplexer 2022 is selected to meet the controlling signal of 60Hz frame rate to this level shift circuit 204.If this input frame rate A switches to 40Hz, then a comparative result C of this comparer 2020 is 0, and this multiplexer 2022 is selected to meet the controlling signal of 40Hz frame rate to this level shift circuit 204.
See also Fig. 5, it is the driving method process flow diagram that illustrates according to liquid crystal indicator of the present invention.This liquid crystal indicator comprises a liquid crystal panel and one drive circuit, this liquid crystal panel comprises a plurality of gate lines and the arrangement interlaced with each other of a plurality of source electrode lines, this driving circuit comprises that time schedule controller, a detecting unit, a level shift circuit, a gate drive unit are arranged on this liquid crystal panel and at least one source drive unit, and this driving method comprises the following steps.
Among the step S500, this time schedule controller is accepted an input frame rate and is provided at least one gate conducting signal and the one source pole data of different input frame rates to write signal.Again, this time schedule controller further provides at least one gate start signal, when this gate start signal when high LJ position becomes low level, this gate conducting signal of activation.
Among the step S510, this detecting unit detects this input frame rate and selector writes signal should import this gate conducting signal and this source electrode data of frame rate.
Among the step S520, this level shift circuit receives this gate conducting signal that meets this input frame rate.
Among the step S530, this shift cache unit comes these gate lines of this liquid crystal panel of conducting according to this gate conducting signal.
Among the step S540, this source drive unit writes signal according to these source electrode data data is write each source electrode line, wherein the duration of charging of each brake cable for this gate conducting signal each gate line of conducting and according to these source electrode data write signal with these data write each source electrode line during, this time schedule controller be adjust these source electrode data write signal work period (duty cycle) so that should the duration of charging before this input frame rate switches and identical after the switching.
In an embodiment, this shift cache unit comprises that one first shift scratch circuit and second shift scratch circuit control odd number bar gate line and even number bar gate line respectively so that these odd number bar gate lines and these even number bar gate line alternate conduction.This level shift circuit will be sent to this first shift scratch circuit to these controlling signal that should first shift scratch circuit, will be sent to this second shift scratch circuit to these controlling signal that should second shift scratch circuit.
This detecting unit comprises a comparer and a multiplexer, comprises in step S510:
This comparer relatively should be imported frame rate and with reference to frame rate; And
This multiplexer is selected importing these controlling signal of frame rate according to a comparative result of this comparer.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; the persond having ordinary knowledge in the technical field of the present invention; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (11)
1. a liquid crystal indicator is characterized in that, comprising:
One liquid crystal panel comprises a plurality of gate lines and the arrangement interlaced with each other of a plurality of source electrode lines; And
One drive circuit, in order to drive this liquid crystal panel show image, this driving circuit comprises:
Time schedule controller is accepted an input frame rate and is provided at least one gate conducting signal and the one source pole data of different input frame rates to write signal;
One detecting unit is detected this input frame rate and selector should this gate conducting signal and this source electrode data of input frame rate write signal;
One level shift circuit receives this gate conducting signal that meets this input frame rate;
One gate drive unit is arranged on this liquid crystal panel, controls these gate lines of this liquid crystal panel according to this gate conducting signal; And
At least one source drive unit writes signal according to these source electrode data data is write each source electrode line,
Wherein respectively the duration of charging of this gate line for this gate drive unit according to this gate conducting signal conducting respectively this gate line and this source drive unit according to these source electrode data write signal with these data write this source electrode line respectively during, this time schedule controller be adjust these source electrode data write signal work period (duty cycle) so that should the duration of charging before this input frame rate switches and identical after the switching.
2. liquid crystal indicator according to claim 1 is characterized in that, wherein this detecting unit is to be arranged in this time schedule controller.
3. liquid crystal indicator according to claim 1 is characterized in that, wherein this detecting unit comprises:
One comparer relatively should be imported frame rate and with reference to frame rate; And
One multiplexer is selected this gate conducting signal and this source electrode data that import frame rate are write signal according to a comparative result of this comparer.
4. liquid crystal indicator according to claim 1 is characterized in that, wherein this time schedule controller further provides at least one gate start signal, when this gate start signal when high levle becomes low level, this gate conducting signal of activation.
5. liquid crystal indicator according to claim 4 is characterized in that, wherein this gate drive unit comprises that one first shift scratch circuit and one second shift scratch circuit control odd number bar gate line and even number bar gate line respectively.
6. liquid crystal indicator according to claim 5 is characterized in that, wherein these odd number bar gate lines and these even number bar gate lines are alternate conduction.
7. the driving method of a liquid crystal indicator, it is characterized in that, this liquid crystal indicator comprises a liquid crystal panel and one drive circuit, this liquid crystal panel comprises a plurality of gate lines and the arrangement interlaced with each other of a plurality of source electrode lines, this driving circuit comprises that time schedule controller, a detecting unit, a level shift circuit, a gate drive unit are arranged on this liquid crystal panel and at least one source drive unit, and this driving method comprises:
This time schedule controller is accepted an input frame rate and is provided at least one gate conducting signal and the one source pole data of different input frame rates to write signal;
This detecting unit detects this input frame rate and selector writes signal should import this gate conducting signal and this source electrode data of frame rate;
This level shift circuit receives this gate conducting signal that meets this input frame rate;
This gate drive unit comes these gate lines of this liquid crystal panel of conducting according to this gate conducting signal; And
This source drive unit writes signal according to these source electrode data data is write each source electrode line,
Wherein respectively the duration of charging of this gate line for this gate drive unit according to this gate conducting signal conducting respectively this gate line and this source drive unit according to these source electrode data write signal with these data write this source electrode line respectively during, this time schedule controller be adjust these source electrode data write signal work period (duty cycle) so that should the duration of charging before this input frame rate switches and identical after the switching.
8. the driving method of liquid crystal indicator according to claim 7, it is characterized in that, wherein this detecting unit comprises a comparer and a multiplexer, detects this input frame rate and selector should comprise in the step of the controlling signal of input frame rate in this detecting unit:
This comparer relatively should be imported frame rate and with reference to frame rate; And
This multiplexer is selected this gate conducting signal and this source electrode data that import frame rate are write signal according to a comparative result of this comparer.
9. the driving method of liquid crystal indicator according to claim 7 is characterized in that, wherein this time schedule controller further provides at least one gate start signal, when this gate start signal when high levle becomes low level, this gate conducting signal of activation.
10. the driving method of liquid crystal indicator according to claim 7 is characterized in that, wherein this shift cache unit comprises that one first shift scratch circuit and second shift scratch circuit control odd number bar gate line and even number bar gate line respectively.
11. the driving method of liquid crystal indicator according to claim 10 is characterized in that, wherein these odd number bar gate lines and these even number bar gate lines are alternate conduction.
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| CN2011102523857A CN102290038A (en) | 2011-08-30 | 2011-08-30 | Liquid crystal display device and driving method thereof |
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| CN2011102523857A CN102290038A (en) | 2011-08-30 | 2011-08-30 | Liquid crystal display device and driving method thereof |
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| CN102290038A true CN102290038A (en) | 2011-12-21 |
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|---|---|
| CN (1) | CN102290038A (en) |
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| CN104835470A (en) * | 2015-05-26 | 2015-08-12 | 合肥京东方光电科技有限公司 | Display substrate driving device and driving method, and display equipment |
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Application publication date: 20111221 |