CN102289278B - Interface with extremely low power consumption - Google Patents
Interface with extremely low power consumption Download PDFInfo
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- CN102289278B CN102289278B CN2011102273669A CN201110227366A CN102289278B CN 102289278 B CN102289278 B CN 102289278B CN 2011102273669 A CN2011102273669 A CN 2011102273669A CN 201110227366 A CN201110227366 A CN 201110227366A CN 102289278 B CN102289278 B CN 102289278B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides an interface with extremely low power consumption, and the interface provided by the invention comprises a memory and a storage controller, wherein an (n-2<n>) decipherer is arranged on the memory; a (2<n>-n) decoder is arranged on the storage controller; the output end of the (n-2<n>) decipherer is connected with the corresponding input end of the (2<n>-n) decoder through a data transmission line; n is a positive integer more than or equal to 1; and within one clock period, the data transmission line only has one transmitted datum. The invention provides a distinctively different signal scheme capable of minimizing the power consumption; and by utilizing the scheme, lower throughput is generated, extra packaging pins are used, and the power consumption of signal transmission can be reduced.
Description
[technical field]
The present invention relates to communication or field of computer technology, particularly a kind of low-power consumption interface, it is fit to have the mobile battery electric power system that lower or medium data transmission requires, as mobile phone, panel computer, IPad and other hand-held communications and calculation element.
[background technology]
Nowadays, every kind of communication or computing system all comprise multiple mutual swap data and carry out the electronics subassembly of instruction.With the example that is applied as of the mobile memory chip in mobile phone, chip is by typical 16 bit wide data buss and central micro-controller communications.Shared instruction and clock sync signal.Mobile device adopts several different methods to minimize chip power-consumption.Power consumption is very low, and in fact, when a large amount of driven external signals had very large capacitive load, most of power consumption consumption was on these external data signals.
Now, do not take specific process in mobile the application, greatly reduce power consumption by external signal.Take Fig. 1 as example, standard mobile memory chip is used as the subassembly of the mobile application apparatuss such as mobile phone.This subassembly can be 1G DDR-2 storer n 16, i.e. 16 bit wide data-interfaces.In order to reduce power consumption, can be optimized this class chip.Yet when transmitting data between system's microcontroller and memory chip, it is generally random data that data transmit.Article 16, in data line, the random data on average 8 transmits and will jump to new state along with each system clock transition.Need in addition 2 data clocks (transmit data every 8 correspondences one), 10 transmission lines will the redirect with each clock transition altogether, produces send and transmit most of power that these data-signals need to consume.
Existing technology attempts to reduce power consumption by new interface, working voltage and the signal swing of this interface lower (seeing SDR, DDR, the JEDEC specification of DDR-2 and DDR-3 memory interface).But, meanwhile, the transmit outer signal losses most operation power consumption of low-power consumption semiconductor element.
[summary of the invention]
The present invention proposes a kind of ultra low power consumption interface, can minimize the power consumption of every signal transmission.
To achieve these goals, the present invention adopts following technical scheme:
A kind of ultra low power consumption interface comprises storer and memory controller, and described storer is provided with n-2
nCode translator, described memory controller is provided with 2
n-n demoder; Described n-2
nThe output terminal of code translator connects 2 by data line
nThe input end that-n demoder is corresponding; N is the positive integer more than or equal to 1; In data line, a transmission of data is only arranged in the clock period.
In the clock period, n-2
nCode translator and 2
nTransmit the n bit data between-n demoder.
Described ultra low power consumption interface also comprises an end connected storage, and the other end connects additional connecting line and the reference voltage line of memory controller.
Data line is provided with electric capacity, to fall low static power consumption.
When storer transmitted identical data continuously to memory controller, the signal on additional connecting line will be by memory transfer to memory controller; Memory controller detects the signal on additional connecting line, confirms thus this clock period, and storer transmitted the data identical with a upper clock cycle.
N=1,2,3,4,5,6,7 or 8, or larger integer.
A kind of electronic system comprises first component and second component, and first component and second component are in exchange logic data cell process, and data cell inside only has a bars transmission line to transmit; The take over party can detect this transmission, and be used for the checking, latch data, need not data clock synchronous.
Be connected with 2 between first component and second component
nIndividual data signal transmission wire, these are 2 years old
nData signal transmission wire only has a bars transmission line to transmit in a clock period, transmits the n bit data; N is the positive integer more than or equal to 1.
Whole electronics system operation is only used a major clock, and the clock from subsystem does not come latch data.
Data line is provided with electric capacity, to reduce quiescent dissipation.
Second component is from the first component receive data, and second component detects single signal transmission on data accepted, and the data that receive from first component are latched in the usage data transmission.
Compared with prior art, the present invention has the following advantages: the present invention carries out decoding by at storer, code translator being set with the data that will transmit in storer, and only having on a data line in the clock period has signal intensity; Demoder on memory controller receives this signal intensity and it is decoded; Because a clock period only has a signal to transmit, the take over party is enough to detect the signal transmission of any arrival, and this is highly effective; If transmit, and only transmit a signal, obviously, data-signal must effectively and can latch, and need not data strobe.But a kind of signaling plan of completely different minimizing power dissipation is proposed in invention; Adopt this scheme, produce lower handling capacity and use extra packaging pin, can reduce the power consumption of signal transmission, for common mobile application apparatus, this restriction is acceptable.
[description of drawings]
Fig. 1 is the interface schematic diagram of standard mobile memory;
Fig. 2 is the schematic diagram of ultra low power consumption interface of the present invention;
Fig. 3 is the schematic diagram of ultra low power consumption interface preferred embodiment of the present invention;
Fig. 4 is that the present invention carries out further revising to reduce the ultra low power consumption interface schematic diagram of quiescent dissipation; Introduce capacitor to avoid stationary singnal to pass through receiver, reduce quiescent dissipation.The Dynamic Signal through the capacitor transmission can only be detected in microcontroller.
[embodiment]
Below in conjunction with accompanying drawing, the present invention is described in further detail.
See also shown in Figure 1ly, usually adopt the standard DDR-2 storer of 16 bit wide data buss in the current mobile consumer goods.Needing in addition 2 data gatings to be used for data synchronously latchs.Transmission means to random data for this, and along with the transmission of each clock signal, average 10 signals will transmit.The power consumption that also means average every transmission is 10 signal intensity/16=0.625 every signal transmission.
In order at utmost to save power consumption, the present invention is in the only once signal transmission of each clock period.In addition, the present invention is in conjunction with data clock free synchronization integration scenario.Owing to only there being a signal to transmit, the take over party is enough to detect the signal transmission of any arrival, and this is highly effective.If transmit, and only transmit a signal, obviously, data-signal must effectively and can latch, and need not data strobe.Must provide in addition a bars transmission line, in case the identical data of twice transmission cause not having the signal transmission.Transmission on this additional signal transmssion line will show this result.
Fig. 2 has shown the principle of this data transmission scheme.In this case, the present invention transmits 3 bit data by 8 data lines.At this moment, the present invention is equivalent to 1/8 coding.Only 1 bars being sent transmission line uses instead in transmitting data 0 to 7.If transmit continuously identical data (not changing data), the signal on haywire will transmit.Receiving microcontroller MC will be by comparing the detection signal transmission with reference voltage Vref.When signal surpassed reference value, the signal transmission will be detected.
In Fig. 2, along with the variation of each signal will have 3 bit data to be transmitted, therefore, power efficiency is 1 signal intensity/3=0.333 every signal transmission now.Note that no longer needs data strobe signal.The power consumption that adopts this scheme is half when adopting general scheme!
See also shown in Figure 3ly, be the detail of construction of the preferred ultra low power consumption interface of the present invention, this ultra low power consumption interface comprises storer and the memory controller MC with 8-3 demoder with 3-8 code translator; Corresponding 8 input ends that connect the 8-3 demoder of 8 output terminals of 3-8 code translator; Be connected with haywire and reference voltage line between storer and memory controller MC.
The specific works process is as follows: the 3bit content in storer will be transmitted (for example 101), it will be decoded into eight-digit binary number (00100000) in storer, then, this eight-digit binary number sends memory controller MC within a clock period, so just realized that the transmission of signal can transmit 3b it data.After memory controller MC receives the eight-digit binary number data of being sent by storer, after there is the decoding of 8-3 demoder in section, send memory controller MC inter-process within it.
For wider interface, the more remarkable effect of power-dissipation-reduced.Each clock transfer 4 bit data needs 16 bit wide signal buss (2 4 powers), and in that event, the signal transmission efficiency is 1 signal intensity/4=0.25 every signal transmission; Each clock transfer 8 bit data needs 256 bit wide signal buss (2 8 powers), and in that event, the signal transmission efficiency is 1 signal intensity/8=0.125 every signal transmission; Each clock transfer 16 bit data needs 64K bit wide signal bus (2 16 powers), and in that event, the signal transmission efficiency is 1 signal intensity/16=0.0625 every signal transmission, and is higher 10 times than the efficient of now DDR-2 interface! That is, according to thought of the present invention, only there is a signal transmission each clock period, and each clock period transmission n bit data, just need 2 so
n(n is the positive integer more than or equal to 1) bit wide signal bus; Need the corresponding n-2 that arranges in storer
nCode translator carries out decoding to the n bit data, arranges 2 in memory controller MC
n-n demoder is to receiving n-2
nThe decoding data that code translator transmits.
Please participate in shown in Figure 4ly, the present embodiment arranges an electric capacity on the line between the input end of the demoder of the decoder output of storer and memory controller MC, interrupt data-signal transmission stationary singnal by capacitor, to avoid the quiescent dissipation loss.
In this disclosure of the invention book, but we propose a kind of signaling plan of completely different minimizing power dissipation.Adopt proposed projects, produce lower handling capacity and extra packaging pin, can reduce the power consumption of signal transmission, for common mobile application apparatus, this restriction is acceptable.
Claims (9)
1. a ultra low power consumption interface, is characterized in that, comprises storer and memory controller, and described storer is provided with n-2
nCode translator, described memory controller is provided with 2
n-n demoder; Described n-2
nThe output terminal of code translator connects 2 by data line
nThe input end that-n demoder is corresponding; N is the positive integer more than or equal to 1; In data line, a transmission of data is only arranged in the clock period; In the clock period, n-2
nCode translator and 2
nTransmit the n bit data between-n demoder.
2. a kind of ultra low power consumption interface as claimed in claim 1, is characterized in that, described ultra low power consumption interface also comprises an end connected storage, and the other end connects additional connecting line and the reference voltage line of memory controller.
3. a kind of ultra low power consumption interface as claimed in claim 1, is characterized in that, data line is provided with electric capacity.
4. a kind of ultra low power consumption interface as claimed in claim 2, is characterized in that, when storer transmitted identical data continuously to memory controller, the signal on additional connecting line will be by memory transfer to memory controller; Memory controller detects the signal on additional connecting line, confirms thus this clock period, and storer transmitted the data identical with a upper clock cycle.
5. an electronic system, is characterized in that, comprises first component and second component, and first component and second component are in exchange logic data cell process, and data cell only has a bars transmission line to transmit in inner clock period; The take over party can detect this transmission, and be used for the checking, latch data, need not data clock synchronous.
6. a kind of electronic system as claimed in claim 5, is characterized in that, is connected with 2 between first component and second component
nIndividual data signal transmission wire, these are 2 years old
nData signal transmission wire only has a bars transmission line to transmit in a clock period, transmits the n bit data; N is the positive integer more than or equal to 1.
7. a kind of electronic system as claimed in claim 5, is characterized in that, whole electronics system operation is only used a major clock, and the clock from subsystem does not come latch data.
8. a kind of electronic system as claimed in claim 5, is characterized in that, the data signal transmission wire between first component and second component is provided with electric capacity.
9. a kind of electronic system as claimed in claim 5, is characterized in that, second component is from the first component receive data, and second component detects single signal transmission on data accepted, and the data that receive from first component are latched in the usage data transmission.
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Citations (4)
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| TW480428B (en) * | 1997-06-23 | 2002-03-21 | Samsung Electronics Co Ltd | Circuit of data input/output and method using the same |
| US7358868B2 (en) * | 2003-01-14 | 2008-04-15 | Stmicroelectronics S.R.L. | Method and circuit system for the synchronous transmission of digital signals through a bus |
| CN101371234A (en) * | 2006-01-30 | 2009-02-18 | 汤姆森特许公司 | Data bus interface with interruptible clock |
| CN101405939A (en) * | 2006-03-21 | 2009-04-08 | Nxp股份有限公司 | Pseudo-synchronous small register designs with very low power consumption and methods to implement |
-
2011
- 2011-08-09 CN CN2011102273669A patent/CN102289278B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW480428B (en) * | 1997-06-23 | 2002-03-21 | Samsung Electronics Co Ltd | Circuit of data input/output and method using the same |
| US7358868B2 (en) * | 2003-01-14 | 2008-04-15 | Stmicroelectronics S.R.L. | Method and circuit system for the synchronous transmission of digital signals through a bus |
| CN101371234A (en) * | 2006-01-30 | 2009-02-18 | 汤姆森特许公司 | Data bus interface with interruptible clock |
| CN101405939A (en) * | 2006-03-21 | 2009-04-08 | Nxp股份有限公司 | Pseudo-synchronous small register designs with very low power consumption and methods to implement |
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Address after: 710075 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |