CN102280381A - Method of planarization insulation layer and method for manufacturing array substrate comprising planarization insulation layer - Google Patents
Method of planarization insulation layer and method for manufacturing array substrate comprising planarization insulation layer Download PDFInfo
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- CN102280381A CN102280381A CN201110174161A CN201110174161A CN102280381A CN 102280381 A CN102280381 A CN 102280381A CN 201110174161 A CN201110174161 A CN 201110174161A CN 201110174161 A CN201110174161 A CN 201110174161A CN 102280381 A CN102280381 A CN 102280381A
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Abstract
The invention discloses a method of a planarization insulation layer and a method for manufacturing an array substrate comprising the planarization insulation layer. The method comprises the following steps: providing a substrate comprising a first surface and a second surface; forming at least one patterning metal layer on the first surface of the substrate, and forming at least one insulation layer on the patterning metal layer; coating a negative photoresist and covering the negative photoresist on the insulation layer; carrying out an exposure manufacture process on the second surface of the base plate, thus the negative photoresist which is blocked by the patterning metal layer is subjected to exposure and is not subjected to exposure; carrying out a developing manufacture process to remove the negative photoresist which is not subjected to exposure; removing partial insulation layer which is not covered by the negative photoresist; and removing the negative photoresist which is subjected to exposure, thus the insulation layer forms a flat surface.
Description
Technical field
The invention relates to a kind of method of planarization insulating layer and the method for the multiple substrate that making has planarization insulating layer, refer to a kind of method of utilizing the multiple substrate that the pattern picture metal level has planarization insulating layer as the method and the making of the planarization insulating layer of light shield especially.
Background technology
LCD (LCD) has many advantages, and for example volume is little, in light weight, power saving etc.Therefore, LCD replaces traditional cathode ray tube (CRT) gradually and becomes the main flow of display.LCD has been applied to electronic products such as hand-held computer, mobile phone widely.Yet LCD still exists needs many shortcomings to overcome, such as the problem of narrower visual angle and brightness disproportionation or the like.
Many wide viewing angle technology in order to overcome the narrower problem in LCD visual angle, to have developed at present.Wherein a kind of is to utilize the plane of transverse electric field effect to switch (in-plane switching, IPS) technology of showing.The IPS technology mainly is that pixel electrode and common electrode are placed same plane, allows the direction of rotation of liquid crystal molecule maintain on the horizontal plane, to promote its visual angle.But because of the aperture opening ratio of Traditional IP S LCD on the low side, so develop fringe field and switch that (fringe-field switching, FFS) technology and plane to line switches (plane-to-line switching, PLS) two kinds of LCD Display Techniques of technology.Because FFS and PLS Display Technique all are to utilize horizontal component of electric field to drive turning to and arranging of liquid crystal, therefore influenced by the external force of horizontal direction.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of the multiple substrate of LCD.As shown in Figure 1, multiple substrate 10 comprises a substrate 12, at least one patterned metal layer 14 and at least one insulating barrier 16 and is covered on the patterned metal layer 14.As shown in Figure 1, therefore the part owing to insulating barrier 16 corresponding pattern metal levels 14 can cause insulating barrier 16 to form a uneven surface h because the thickness of patterned metal layer 14 forms outburst area a.The uneven surface h of this insulating barrier 16 can influence the alignment film that later use brushing (rubbing) mode the forms uniformity of (figure does not show), also may produce uneven horizontal component of electric field, and it is unusual that liquid crystal is rotated, and then causes dark line or ripples line in the demonstration.
Summary of the invention
One of main purpose of the present invention is to provide a kind of method of planarization insulating layer and the method for the multiple substrate that making has planarization insulating layer, causes the reduction of display quality to avoid insulating barrier to have uneven surface.
For reaching above-mentioned purpose, the invention provides a kind of method of planarization insulating layer, comprise a substrate is provided, comprise a first surface and a second surface; At least one patterned metal layer of formation and at least one insulating barrier are covered on the patterned metal layer on the first surface of substrate, and wherein insulating barrier has a uneven surface; Being coated with a negative photoresistance is covered on the insulating barrier; Second surface in substrate carries out an exposure manufacture process, and the negative photoresistance that is not patterned metal level is exposed, and makes and be patterned the negative photoresistance that metal level blocks and can be exposed; Carry out a developing manufacture process to remove the negative photoresistance that is not exposed; Remove the partial insulative layer that is not covered, make insulating barrier form a flat surfaces by negative photoresistance; And remove the negative photoresistance be exposed.
In addition, the invention provides the method that a kind of making has the multiple substrate of planarization insulating layer, comprise a substrate is provided, comprise a first surface and a second surface; Form one first patterned metal layer, one first insulating barrier, one second patterned metal layer and one second insulating barrier on the first surface of substrate in regular turn, wherein second insulating barrier has a uneven surface; Being coated with a negative photoresistance is covered on second insulating barrier; Second surface in substrate carries out an exposure manufacture process, does not make to be exposed by the negative photoresistance of first patterned metal layer and second pattern metal, and the negative photoresistance that is blocked by first patterned metal layer and second patterned metal layer can be exposed; Carry out a developing manufacture process to remove the negative photoresistance that is not exposed; Remove part second insulating barrier that is not covered, make second insulating barrier form a flat surfaces by negative photoresistance; And remove the negative photoresistance be exposed.
The method of planarization insulating layer and making have the method for the multiple substrate of planarization insulating layer according to the present invention, second surface in substrate carries out an exposure manufacture process, and directly utilize patterned metal layer stop portions exposure light source, in other words, patterned metal layer can be used as light shield in the present invention, and under the situation that does not increase extra processing procedure, control the exposure area, and the program of removing via follow-up development and negative photoresistance causes the reduction of display quality to produce the insulating barrier of planarization to avoid insulating barrier to have uneven surface.
Description of drawings
Fig. 1 is the schematic diagram of multiple substrate.
Fig. 2 to Fig. 7 is the schematic diagram of method of the planarization insulating layer of one first preferred embodiment of the present invention.
Fig. 8 to Figure 13 has the schematic diagram of method of the multiple substrate of planarization insulating layer for the making of one second preferred embodiment of the present invention.
Figure 14 has the schematic diagram of method of the multiple substrate of planarization insulating layer for the making of one the 3rd preferred embodiment of the present invention.
[primary clustering symbol description]
| 10 | |
12 | Substrate |
| 14 | |
16 | Insulating barrier |
| a | Outburst area | h | Uneven |
| 30,30’ | |
22,32 | |
| 24 | |
24a,34a | First patterned |
| 24b,34b | Second patterned |
26a,36a | First |
| 26b,36b | Second |
28,38 | |
| 33 | |
40 | |
| 41 | The |
42 | Pixel electrode |
| A | Outburst area | H | Uneven surface |
| P | Flat surfaces | G | Gate |
| S | Source electrode | D | Drain |
| S1 | First surface | S2 | Second surface |
Embodiment
Please refer to Fig. 2 to Fig. 7, Fig. 2 to Fig. 7 is the schematic diagram of method of the planarization insulating layer of one first preferred embodiment of the present invention.As shown in Figure 2, provide a substrate 22.Substrate 22 can be for example employed substrate of multiple substrate of a display floater, but not as limit.Substrate 22 comprises a first surface S1 and a second surface S2.Then upward forming at least one patterned metal layer 24 and at least one insulating barrier 26 in the first surface S1 of substrate 22 is covered on the patterned metal layer 24.In the present embodiment, patterned metal layer 24 comprises one first patterned metal layer 24a and one second patterned metal layer 24b, insulating barrier 26 comprises one first insulating barrier 26a and one second insulating barrier 26b, and the first insulating barrier 26a is positioned on the first patterned metal layer 24a, the second patterned metal layer 24b is positioned on the first insulating barrier 26a, and the second insulating barrier 26b is positioned on the second patterned metal layer 24b, but not as limit.As shown in Figure 2, because the first patterned metal layer 24a and the second patterned metal layer 24b have certain thickness, therefore the part that covers corresponding each patterned metal layer 24 of the second insulating barrier 26b thereon can form an outburst area A, so make the second insulating barrier 26b have a uneven surface H.
As shown in Figure 3, being coated with a negative photoresistance 28 is covered on the second insulating barrier 26b.Then, as shown in Figure 4, carry out an exposure manufacture process (shown in the arrow of Fig. 4) in the second surface S2 of substrate 22, because patterned metal layer 24 has shading characteristic, therefore not being patterned the negative photoresistance 28 that metal level 24 (comprising the first patterned metal layer 24a and the second patterned metal layer 24b) blocks can be exposed, and is patterned the negative photoresistance 28 that metal level 24 blocks and then can be exposed.As shown in Figure 5, carry out a developing manufacture process to remove the negative photoresistance 28 that is not exposed, the negative photoresistance 28 that is exposed then can be retained.Next, as shown in Figure 6, remove the part second insulating barrier 26b that is not covered, so that the second insulating barrier 26b forms a flat surfaces P by negative photoresistance 28.In the present embodiment, remove the second insulating barrier 26b that is not covered and utilize an etch process to be realized by negative photoresistance 28, but not as limit.At last, as shown in Figure 7, remove negative photoresistance 28.The first patterned metal layer 24a comprises a gate line and a gate in the present embodiment.The second patterned metal layer 24b comprises a data wire, one source pole and a drain, but not as limit.
From the above, the method for the planarization insulating layer of present embodiment be utilize patterned metal layer 24 as light shield with the control exposure area, therefore do not need additionally to utilize light shield to define the zone of desiring planarization, therefore can save the cost that extra light shield is made.
Flattening method of the present invention can be applicable to various need and forms on the structure of planarization insulating layer, and insulating barrier can be various retes with light transmitting property, for example inorganic insulation layer such as silicon oxide layer, silicon nitride layer or silicon oxynitride layer, or organic insulator, and do not exceed with the practice of the foregoing description.Embodiment hereinafter has the multiple substrate of planarization insulating layer with making method is example explanation the present invention, but the present invention is not as limit.
Please refer to Fig. 8 to Figure 13.Fig. 8 to Figure 13 has the schematic diagram of method of the multiple substrate of planarization insulating layer for the making of one second preferred embodiment of the present invention.As shown in Figure 8, at first provide a multiple substrate 30.Multiple substrate 30 can be for example employed multiple substrate such as display panels or electric exciting light emitting display panel of various two-d display panel.Multiple substrate 30 comprises a substrate 32, and substrate 32 comprises a first surface S1 and a second surface S2.Then, the first surface S1 in substrate 32 goes up formation one first a patterned metal layer 34a and a common electrode 40.The first patterned metal layer 34a comprises a gate G and a gate line (figure does not show).Common electrode 40 is made of a transparent conductive material.Subsequently, on the first patterned metal layer 34a and common electrode 40, form one first insulating barrier 36a.Afterwards, go up in the first insulating barrier 36a and form semiconductor channel 33 second patterned metal layer 34b, wherein the second patterned metal layer 34b comprises one source pole S, a drain D and a data wire (figure does not show).Then, go up formation one second insulating barrier 36b in the second patterned metal layer 34b, channel semiconductor 33 and the first insulating barrier 36a again.As shown in Figure 8, the part of the corresponding first patterned metal layer 34a of the second insulating barrier 36b and the second patterned metal layer 34b can form an outburst area A, and therefore the second insulating barrier 36b has a uneven surface H.
As shown in Figure 9, being coated with a negative photoresistance 38 is covered on the second insulating barrier 36b.Then, as shown in figure 10, carry out an exposure manufacture process (shown in the arrow of Figure 10) in the second surface S2 of substrate 32, the negative photoresistance 38 that is blocked by the first patterned metal layer 34a and the second patterned metal layer 34b is exposed, and the negative photoresistance 38 that is blocked by the first patterned metal layer 34a and the second patterned metal layer 34b can be exposed.As shown in figure 11, carry out the negative photoresistance 38 that a developing manufacture process is not exposed with removal, and the negative photoresistance 38 that is exposed is kept.Next, as shown in figure 12, remove the part second insulating barrier 36b that is not covered, make the second insulating barrier 36b form a flat surfaces P by negative photoresistance 38.As shown in figure 13, remove negative photoresistance 38.Subsequently, form a contact hole 41 in the second insulating barrier 36b, go up in the second insulating barrier 36b and form a pixel electrode 42, wherein pixel electrode 42 is inserted contact hole 41 and is electrically connected with drain D.
Please refer to Figure 14.Figure 14 has the schematic diagram of method of the multiple substrate of planarization insulating layer for the making of one the 3rd preferred embodiment of the present invention.For the difference between the clearer more different embodiment, in present embodiment and second preferred embodiment, use the identical identical assembly of label mark, and only describe at the different place of two embodiment.Shown in 14 figure, compared to the present invention's second preferred embodiment, in the present embodiment, pixel electrode 42 is to be formed between the first insulating barrier 36a and the second insulating barrier 36b of multiple substrate 30 ', and electrically connect with drain D, common electrode 40 then is to be formed on the second insulating barrier 36b.The flattening method of the second insulating barrier 36b is identical with the practice of second preferred embodiment, sees also the explanation of Fig. 8 to the 13 figure, does not repeat them here.
In the multiple substrate with planarization insulating layer of the present invention second and the 3rd preferred embodiment, the first patterned metal layer 34a comprises gate G, and the second patterned metal layer 34b comprises source S and drain D, so gate G is the below that is formed at source S and drain D, but is not limited thereto.Gate G also can be formed at the top of source S and drain D, and at this moment, the first patterned metal layer 34a comprises source S and drain D, and the second patterned metal layer 34b comprises gate G.
In sum, the method for the multiple substrate that has planarization insulating layer according to the method and the making of planarization insulating layer of the present invention is carried out an exposure manufacture process in the second surface of substrate, and is directly utilized patterned metal layer shield portions exposure light source.In other words, patterned metal layer promptly can be used as light shield with the control exposure area in the present invention, to save the cost that extra light shield is made, and the program of removing via follow-up development and negative photoresistance causes the reduction of display quality to produce the insulating barrier of planarization to avoid insulating barrier to have uneven surface.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. the method for a planarization insulating layer is characterized in that, comprising:
One substrate is provided, comprises a first surface and a second surface;
At least one patterned metal layer of formation and at least one insulating barrier are covered on this patterned metal layer on this first surface of this substrate, and wherein this insulating barrier has a uneven surface;
Being coated with a negative photoresistance is covered on this insulating barrier;
This second surface in this substrate carries out an exposure manufacture process, makes not by should being exposed by negative photoresistance that this patterned metal layer blocks, and makes by should can not being exposed by negative photoresistance that this patterned metal layer blocks;
Carry out a developing manufacture process to remove the negative photoresistance that is somebody's turn to do that is not exposed;
Remove this insulating barrier of part that is not covered, make this insulating barrier form a flat surfaces by this negative photoresistance; And
What removal was exposed should negative photoresistance.
2. according to the method for 1 described planarization insulating layer of claim the, it is characterized in that wherein removing this insulating barrier of part that is not covered by this negative photoresistance is to utilize an etch process.
3. according to the method for 1 described planarization insulating layer of claim the, it is characterized in that, wherein this patterned metal layer comprises one first patterned metal layer and one second patterned metal layer, this at least one insulating barrier comprises one first insulating barrier and one second insulating barrier, this first insulating barrier is to be positioned on this first patterned metal layer, this second patterned metal layer is to be positioned on this first insulating barrier, and this second insulating barrier is to be positioned on this second patterned metal layer.
4. according to the method for 3 described planarization insulating layers of claim the, it is characterized in that wherein this first patterned metal layer comprises a gate line and a gate.
5. according to the method for 3 described planarization insulating layers of claim the, it is characterized in that wherein this second patterned metal layer comprises a data wire, one source pole and a drain.
6. a making has the method for the multiple substrate of planarization insulating layer, it is characterized in that, comprising:
One substrate is provided, comprises a first surface and a second surface;
Form one first patterned metal layer, one first insulating barrier, one second patterned metal layer and one second insulating barrier on this first surface of this substrate in regular turn, wherein this second insulating barrier has a uneven surface;
Being coated with a negative photoresistance is covered on this second insulating barrier;
This second surface in this substrate carries out an exposure manufacture process, make not by should being exposed by negative photoresistance that this first patterned metal layer and this second patterned metal layer block, and make by should can not being exposed by negative photoresistance that this first patterned metal layer and this second patterned metal layer block;
Carry out a developing manufacture process to remove the negative photoresistance that is somebody's turn to do that is not exposed;
Remove this second insulating barrier of part that is not covered, make this second insulating barrier form a flat surfaces by this negative photoresistance; And
What removal was exposed should negative photoresistance.
7. 6 described making have the method for the multiple substrate of planarization insulating layer according to claim the, it is characterized in that, wherein removing this second insulating barrier of part that is not covered by this negative photoresistance is to utilize an etch process.
8. 6 described making have the method for the multiple substrate of planarization insulating layer according to claim the, it is characterized in that, wherein this first patterned metal layer comprises a gate.
9. 6 described making have the method for the multiple substrate of planarization insulating layer according to claim the, it is characterized in that, wherein this second patterned metal layer comprises an one source pole and a drain.
10. 6 described making have the method for the multiple substrate of planarization insulating layer according to claim the, it is characterized in that, other comprises formation one common electrode and a pixel electrode.
11. 10 described making have the method for the multiple substrate of planarization insulating layer according to claim the, it is characterized in that, wherein this common electrode is to be formed between this substrate and this first insulating barrier, and this pixel electrode is to be formed on this second insulating barrier.
12. 10 described making have the method for the multiple substrate of planarization insulating layer according to claim the, it is characterized in that, wherein this pixel electrode is to be formed between this first insulating barrier and this second insulating barrier, and this common electrode is to be formed on this second insulating barrier.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110174161A CN102280381A (en) | 2011-06-27 | 2011-06-27 | Method of planarization insulation layer and method for manufacturing array substrate comprising planarization insulation layer |
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| CN201110174161A CN102280381A (en) | 2011-06-27 | 2011-06-27 | Method of planarization insulation layer and method for manufacturing array substrate comprising planarization insulation layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134431A (en) * | 2016-02-25 | 2017-09-05 | 凌巨科技股份有限公司 | Improve the uneven thin film transistor circuit structure of photoresistance and method |
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| CN1088712A (en) * | 1992-08-27 | 1994-06-29 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
| JPH06326130A (en) * | 1993-05-17 | 1994-11-25 | Matsushita Electric Ind Co Ltd | Flattening method and flattened element |
| CN101169565A (en) * | 2006-10-25 | 2008-04-30 | Lg.菲利浦Lcd株式会社 | Array substrate for liquid crystal display device and method of fabricating the same |
-
2011
- 2011-06-27 CN CN201110174161A patent/CN102280381A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1088712A (en) * | 1992-08-27 | 1994-06-29 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
| JPH06326130A (en) * | 1993-05-17 | 1994-11-25 | Matsushita Electric Ind Co Ltd | Flattening method and flattened element |
| CN101169565A (en) * | 2006-10-25 | 2008-04-30 | Lg.菲利浦Lcd株式会社 | Array substrate for liquid crystal display device and method of fabricating the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134431A (en) * | 2016-02-25 | 2017-09-05 | 凌巨科技股份有限公司 | Improve the uneven thin film transistor circuit structure of photoresistance and method |
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Application publication date: 20111214 |