CN102271227A - Linear image sensor in cmos technology - Google Patents
Linear image sensor in cmos technology Download PDFInfo
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- H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
- H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
- H04N3/1525—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation with charge transfer within the image-sensor, e.g. time delay and integration
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Abstract
A time-delay-integration image sensor comprises a matrix of pixels (Px) organized in rows and columns. Each pixel comprises a first photosensitive element (D1), a storage node (A, C2) and a first transfer element (TGM) connected between the first photosensitive element (D1) and the storage node (A), Each pixel (Px) further comprises a second photosensitive element (D1'), a second transfer element (TGH) connected between the second photosensitive element (D1') and the storage node (A), and a third transfer element (TGB) connected between the storage node (A) and the second photosensitive element (D1') of an adjacent pixel of the column. A control circuit (15) is configured to simultaneously command the first and second transfer elements (TGM, TGH) to on state and the third transfer element (TGB) to off state, and, in a distinct phase, to simultaneously command the first and third transfer elements (TGM, TGB) to on state and the second transfer element (TGH) to off state.
Description
Technical field
The present invention relates to a kind of linear imaging sensor of catching image of being designed to, and particularly, relate to a kind of time delay integration (Time Delay Integration, TDI) transducer by scanning.
Background technology
For example, exercise question people such as Michael G.Farrier is " A Large Area TDI Image Sensor for Low Light Level Imaging "-IEEE Journal of Solid-State Circuits, has described the principle of TDI imageing sensor in SC-15 volume, the article in No. 4, in August, 1980.
Tdi sensor generally is used to catch the image with high-speed mobile and the object observed under relatively poor lighting condition.Its general CCD (charge coupled device) technology of using realizes that this CCD technology has made it possible to obtain best performance up to now aspect sensitivity.
Fig. 1 has schematically shown as the tdi sensor in the CCD technology of describing in above-mentioned article.It comprises the array of photosensitive website (photosensitive site) or photoelectricity website (photosite) 10, and as represented, its row is generally much longer than row.In the example of above-mentioned article, row comprises 1028 photoelectricity websites, and row only comprise 128 photoelectricity websites.At the earth photography of carrying out via satellite, row can comprise about 12,000 photoelectricity websites, and this array comprises tens row.
Vertically arrange the row of array with the motion of objects that will catch its image.Represent of the motion of this image by the decline arrow with respect to this transducer.These arrows also corresponding to the synchronized movement of image, movement of electric charges in the ccd register.
With time for exposure of the speed compatibility of image during, the correspondence section (slice) of every capable captured object.This has caused the accumulation of negative electrical charge (electronics) in the photoelectricity website of this row.
When the section of the image that will be caught by row i moved to the level of capable i+1, the electric charge that accumulates among the i that is expert at was transferred to capable i+1, and this row i+1 continues the electric charge of accumulation at same section during the new time for exposure.Therefore, the transfer of the electric charge from the delegation to the next line takes place with the synchronized movement ground of image.
In each migration period, last column of array thereby comprised by the summation of all hand-manipulating of needle to the electric charge that same section accumulated.Therefore, in theory, the sensitivity of this transducer increases with line number.
In the end of each electric charge transfer and exposure cycle, the electric charge of array last column is transferred in the shift register 12, and its purpose is to read the data of last column.End at this row, photoelectricity website ground will charge stored be displaced to electric charge-electric pressure converter 14 in each photoelectricity website of this register one by one, wherein can pass through treatment circuit (general, this treatment circuit is in this transducer outside) and collect the voltage corresponding with the total electrical charge of each photoelectricity website.
Cause the CCD technology to be used for imageing sensor owing to having benefited from the CMOS technology, so imagined the use of CMOS technology at tdi sensor fewer and fewerily.
The exercise question of Gerald Lepage, Jan Bogaerts and Guy Meynants is that " Time-Delay-Integration Architectures in CMOS Image Sensors "-IEEE Transactions on Electron Devices, the 56th volume, o.11, the article in November, 2009 have described the solution that is used for obtaining by means of cmos image sensor the TDI function.
In cmos image sensor, also catch light with the form of the electric charge at pixel level place.Yet, because each pixel has its oneself voltage sense circuit, so electric charge can not be transferred to one other pixel from a pixel.
Fig. 2 has schematically shown the framework of imagining in this piece article of people such as Lepage.The array 10 of N * M pixel Px ' be associated with the array 16 of the memory cell ∑ of same size and configuration (N * M=5 * 5 here).
In principle, pel array 10 ' (be called " line time " T according to time of being spent of spacing (pitch) with each row of image slices scanning element
L) rate corresponding takes view.Thereby after the time, each during the N of pel array is capable is about to catch same image slices at N line.Each row of memory 16 is associated with the same section of image provisionally.Accumulated the intensity level (that is signal level) that all pixel columns are write down at this section therein.
In case accumulated described level, just memory lines is read, resets, and this memory lines is associated with new image slices according to the mode of circulation at this section.
Thereby, observe, must carry out the accumulation of all row of pel array in each line time.
Yet in the CCD technology, intensity level accumulation operation is shifted corresponding to simple electric charge, and in the CMOS technology, these operations are complicated more significantly.They relate to multiplex operation, analog-to-digital conversion, add operation and the memory access operation that pixel is read bus.This cause in the CMOS technology, being difficult to realizing with the CCD technology in identical view catch speed (or line time T
L).Therefore, must be adjusted into the contemplated minimum line time according to the resolution of the pel array of line number, and be adjusted into desired pel spacing.
In some applications, attempt to improve the content be known as image motion modulation transfer function (MTF), this modulation transfer function (MTF) is one of the parameter of the acutance (sharpness) of performance institute reproduced image.Harmonic motion MTF generally causes the image that blurs.The loss of this resolution is due to the fact that and causes that promptly during the line duration, image slices moves on fixing pixel column.
Above-mentioned article as people such as Lepage is described, and a solution is in travel direction each pixel to be subdivided into two.This relates to the line number that increases pixel when reducing spacing, to keep the dimension (dimension) of transducer.When pixel being subdivided into two equal parts, motion MTF advances to 0.9 from 0.64.On the other hand, time-constrain according to the segmentation factor square and increase.Thereby they are multiplied by 4.
Summary of the invention
Observe the cmos image sensor that a kind of TDI of having function need be provided, make it possible to improve image motion MTF, and do not increase time-constrain.
Tend to by providing a kind of time delay integration imageing sensor to satisfy this demand, this time delay integration imageing sensor comprises the array by the pixel of row and column tissue.Each pixel comprises: first light-sensitive element; Memory node; And first transfer element, be connected between this first light-sensitive element and this memory node.Each pixel also comprises: second light-sensitive element; Second transfer element is connected between this second light-sensitive element and this memory node; And the 3rd transfer element, be connected between second light-sensitive element of neighbor of this memory node and these row.This imageing sensor comprises: control circuit, be configured to side by side be conducting state and be cut-off state with the 3rd transfer element order with this first and second transfer elements order, and in different phase, be configured to side by side be conducting state and be cut-off state with this second transfer element order with this first and the 3rd transfer element order.
A kind of method that is used for lagged product partial image transducer administrative time also is provided.
At each pixel of row, this method one after the other may further comprise the steps: first and second light-sensitive elements of this pixel of exposure during preceding half section; The intensity level of this first light-sensitive element is transferred to the memory node of this pixel, and shift the intensity level of second light-sensitive element in the memory node of this pixel; First and second light-sensitive elements of this pixel of exposure during the later half period; The intensity level of this first light-sensitive element is transferred to the memory node of this pixel, and the intensity level of this second light-sensitive element is transferred to the memory node of the neighbor of these row; And read in the intensity level that accumulates in the memory node of this pixel.
Description of drawings
It is obviously clear more that following description that provide according to the purpose just to non-limiting example and the illustrated specific embodiment of the invention by means of accompanying drawing, other advantages and feature will become, in described accompanying drawing:
Fig. 1 of-description has in the above schematically shown the traditional TDI imageing sensor in the CCD technology;
Fig. 2 of-description has in the above schematically shown the traditional tdi sensor in the CMOS technology;
-Fig. 3 has represented four transistor pixels of cmos sensor;
-Fig. 4 has schematically shown the row of the CMOS tdi sensor that makes it possible to improve image motion MTF;
-Fig. 5 has represented the operating procedure of the pixel of Fig. 4 to Fig. 8; And
-Fig. 9 A is the sequential chart of global operation of pixel that illustrates the transducer of Fig. 4 to Fig. 9 H.
Embodiment
Fig. 3 has represented to be called the traditional cmos pixel of " 4T " with solid line.To adopt such pixel reduce motion effects in tdi sensor thereafter.It comprises the photodiode D1 with intrinsic capacity device C1 or integrating condenser, and described capacitor makes it possible to accumulation by the electric charge that light generated that triggers (strike) this pixel.Transfering transistor TG is connected to photodiode D1 the grid of follower (follower) transistor M2.The grid capacitor of transistor M2 and the capacitor formation buffer condenser C2 that is connected to other assemblies of same node A.Select transistor RS that the source electrode of follower transistor M2 is connected to column bus BC.Reset transistor RST is connected to positive power line Vdd with capacitor C2.Reason for convenience, hereinafter, transistorized control signal has the title identical with described transistor.
The operation of this pixel is as described below briefly.Capacitor C1 is to carrying out integration by the electric charge that light generated that triggers photodiode D1.Before end exposure, (briefly) activating transistor RST is with replacement buffer condenser C2 momently.When end exposure, activating transistor TG momently is to transfer to buffer condenser C2 with electric charge from capacitor C1.If photodiode D1 is pinprick (pinned) photodiode, then the transfer of electric charge is whole, and this has also caused the replacement capacitor C1 by the activation of transistor T G.
Thereby, during each exposure stage, the storage voltage level corresponding in buffer condenser C2 with first prior exposure.Can select transistor RS by before being reset, activating, locate to shift this voltage level of expression intensity level at any time to bus B C by transistor RST.
In the pel array according to Fig. 3, the pixel of row is shared same bus B C.Delegation reads the pixel of row with meeting delegation, and via column bus BC their signal is sent to the array of memory cell ∑, to store (Fig. 2).Select row by means of signal RS.
Be used to make the capacitor C2 of the relative low value that reads minimum that noise level (being called reference level) is applied replacement, this noise level is added to the signal level (that is expectation level) that shifts from capacitor C1.For this The noise that decays, general execution correlated-double-sampling (CDS) is promptly at first sampled to the reference level of pixel, and is deducting this reference level from the signal level of being sampled then after capacitor C1 shifts.Generally externally make this difference in the memory (not shown).
Can from the pixel of Fig. 3, derive pixel by adding the element (that is, being connected to the second photodiode D1b of node A) in the dotted line by the second transfering transistor TG ' as in U.S. Patent application US2006/0256221, describing, be called another type of " sharing pixel ".The purpose of this structure is, reads the space hold that circuit reduces pixel by sharing between some photodiodes.In the foregoing stage, shift the level of each photodiode individually to bus B C.Thereby the beginning of each stage in this two stages reset to capacitor C2, and as the same in simple 4T pixel, and this capacitor C2 can not be used for the information of storing previous image during the obtaining of present image.
Fig. 4 has represented in order to improve the row of the pixel Px that moves MTF and revise.
In order to improve motion MTF, two photodiodes in each pixel, are provided.The integration of the electric charge that is associated with image slices no longer takes place during the line duration in single photodiode, but takes place at two half line time durations in two different photodiodes.This means, shift by the electric charge of organizing these photodiodes suitably, can synchronously carry out the integration of electric charge with higher fidelity and the rolling of image (scoll), thus motion effects (or " moving influence ") is restricted to the half line time (or pixel half spacing).
It is the same that each pixel Px structurally looks like shared pixel.It comprises by two light-sensitive element D1 of column direction alignment and D1 '.Described photodiode is the pinned photodiode of identical dimensional preferably.The photodiode D1 that provides integrating condenser C1 is connected to memory node A (holding capacitor C2) via transfer element TGM (for example, MOS transistor).According to similar mode, the second photodiode D1 ' and integrating condenser C1 ' thereof are connected to node A via the second transfering transistor TGH.
Different with the row that comprise the shared pixel of tradition, each pixel comprises the 3rd transfering transistor TGB, and the 3rd transfering transistor TGB is connected to holding capacitor C2 the photodiode D1 ' of the neighbor of these row.In Fig. 4, the pixel Px (Px of row n+1
N+1) capacitor C2 be connected to the pixel (Px of capable n
n) photodiode D1 ', the capacitor C2 of pixel of row n is connected to the photodiode D1 ' of the pixel of capable n-1, or the like.
As in the circuit of Fig. 3, each pixel provides follower transistor M2, be connected to supply voltage Vdd with the transistor RST of replacement capacitor C2 and be used for intensity level transfer to read bus L, be labeled as the selection transistor of CS here.This signal is routed to is positioned at the analog to digital converter (not shown) that reads bus L one end.
In this configuration, reading bus L is public for all pixels of this row, and only there is an analog to digital converter in every row.The grid of the transistor CS of these row further is connected to the same control line that also is labeled as CS.This control line CS makes it possible to select a permutation of pixel, to read.
Transistor T GH, TGM and the TGB of each pixel Px of control circuit 15 control charts 4.
Fig. 5 illustrates operating procedure according to the row of the pixel of Fig. 4 to Fig. 8. Image slices 18,20 is in succession rolled by the direction of the arrow 22 of indicating among Fig. 5 row along each pixel.Each image slices is divided into two halves, synchronous with between the operational phase of the rolling of more preferably diagram section and transducer.Hereinafter, in conjunction with any two contiguous pixels Px
N+1And Px
nOperation is described.
Fig. 5 schematically shown with the corresponding first integral period T of rolling time of the image hemisection sheet of photodiode front
1During this time, image is with respect to locations of pixels.With pixel Px
nPhotodiode D1 and D1 ' expose to image slices 18, and with pixel Px
N+1Photodiode D1 and D1 ' expose to image slices 20.At this moment the section T
1During this time, the integrating condenser C1 of each pixel and C1 ' accumulate the electric charge corresponding with each section.All transistors end.
In Fig. 6, at integration period T
1End the time, transistor T GH and TGM conducting, and the capacitor C2 that will transfer to pixel in the capacitor C1 and the middle charge stored of C1 ' of this pixel.Pixel Px
N+1Capacitor C2 receive and cut into slices 20 the corresponding electric charge of two halves, and pixel Px
nCapacitor C2 receive and cut into slices 18 the corresponding electric charge of two halves.Other elements of the pixel that is represented by dotted lines are by deexcitation.At period T
1During this time, image slices 18 and 20 has moved half of pel spacing approx.
Fig. 7 has schematically shown second integral period T
2The position of image during this time.Image slices 20 is across two neighbors.Pixel Px
nThe bottom of photodiode D1 ' seizure section 20, and pixel Px
N+1Photodiode D1 catch the top of section 20.Therefore, this period arrives another pixel corresponding to image slices by a pixel.All transistors end.At period T
2During this time, image slices 18 and 20 also will move half spacing, thus mark the end of line time.
In Fig. 8, at integration period T
2During end, transistor T GB and TGM are activated.This configuration in, will with at period T
2The electric charge of the two halves correspondence of the section 20 of integration is transferred to pixel Px once more during this time
N+1Capacitor C2, they accumulate with the electric charge that before had been stored among the capacitor C2 at same section in the step of Fig. 6 there.
After activating transistor TGB and TGM, pixel Px
N+1Capacitor C2 intensity level is divided into groups and pixel Px at section two continuous positions of 20
nCapacitor C2 at section two continuous positions of 18 intensity level is divided into groups.At period T
2During end, can come from described pixel, to extract the intensity level that these accumulated by means of transistor M2 and CS.In other words, each pixel comprises two resolution datas that must read with single frequency simply.This makes it possible to improve motion MTF, and does not have to increase the time-constrain that is used for reading of data.
Fig. 9 A is the sequential chart of having summed up according to the global operation of the row of the pixel of Fig. 4 to Fig. 9 H.Fig. 9 A, Fig. 9 B, Fig. 9 D represent the control signal (or state) of transistor RST, CS, TGH, TGM, TGB to Fig. 9 G.Fig. 9 C and Fig. 9 H represent to be used for the action of the analog to digital converter after reading via bus L data handled.
Correlated-double-sampling is used to avoid the noise of resetting.The activation (Fig. 9 B, Fig. 9 G) of representing to be used to read the selection transistor CS of reference level REF discretely with the activation that is used to read (signal that is accumulated) intensity level SIG.Similarly, represent the conversion (Fig. 9 C, Fig. 9 H) of level REF discretely with the conversion of level SIG.
Define general and line time T in succession between the activation twice at transfering transistor TGH or TGB
LThe time for exposure T of corresponding section
IntIntegration period T
1And T
2(T
1=T
2=T
Int/ 2) take place at this time durations.The periodicity of this signal has reflected the processing of the serial section of this image.
As described in conjunction with Figure 5, at period T
1During this time, at first the photodiode D1 and the D1 ' of a pixel scan image slices.Before the electric charge that will obtain is like this transferred to capacitor C2, by the activating transistor RST capacitor C2 (Fig. 9 A) that resets.Soon, activating transistor CS (Fig. 9 B) is to read and conversion reference level REF (Fig. 9 C) then after capacitor C2 resets.Owing to T change-over time
CDuration than the pulse of signal CS is longer, so represent this change-over time of T by thick line in Fig. 9 C
C
In case reference level is transferred to transducer,, is used for period T with storage with regard to activating transistor TGH and TGM
1End and period T
2First intensity level that begins to carry out mark (Fig. 9 D, Fig. 9 E).
At period T
2During this time, the photodiode D1 ' of the photodiode D1 of same pixel and next pixel scans image slices.Come at period T by activating transistor TGM and TGB (Fig. 9 E, Fig. 9 F)
2Carry out the transfer of associated brightness level during end.
In case having finished this electric charge shifts, just read the intensity level SIG that is accumulated by activating transistor CS (Fig. 9 G) once more, and before then in the array that described intensity level SIG is stored in the memory cell ∑, (Fig. 9 H) comes it is sampled by analog to digital converter.New exposure following one is cut into slices and is begun.
Can observe, be the transfering transistor TGM of the central authorities of request twofold of the frequent degree of request (solicit) transistor T GB and TGH.In fact, the photodiode D1 that is connected to transistor T GM scans whole section (that is, two hemisection sheets), and photodiode D1 ' (belong to photodiode of this pixel and belong to a photodiode of neighbor) only scans half section.
In Fig. 9 F, order transistor T GH and TGM or transistor T GB and TGM at Fig. 9 D simultaneously.Also can activate them one by one.
During the line duration, necessary whole read pixel array, and in storage array 16, it is amounted to.Coming row to connect a row ground (rolling shutter pattern) by each pixel that reads each row simultaneously carries out this and reads.Therefore, line duration T
LDuring this time, the as many conversion of row in execution of the transducer of row and the pel array.Simply by T change-over time
CCome the sequential chart of the row adjacent with the row of Fig. 4 is shifted.
To not describe the storage array of managing according to the mode the same 16 in detail in this application with the situation of traditional TDI-MOS transducer.
Thereby, at moving of a pel spacing and to twice of each image slices scanning: undertaken for the first time and photodiode D1 ' by the half-pixel spacing that staggers with respect to photodiode D1 carries out the second time by photodiode D1.This concrete over-sampling makes it possible to improve significantly image motion MTF, forwards about 0.9 (with Nyquist (Nyquist) frequency computation part) to from 0.637.Different with the technology of prior art, do not revise the spacing of pixel, do not revise the spatial resolution of image yet.Therefore, time-constrain is constant.
In fact, time-constrain is by reading circuit and analog to digital converter applies.In fact, at the array of m row, must line duration T
LThe middle execution changed (or 2m conversion under the situation of CDS) for m time.Pre-determining under the situation of line time in sweep speed and spacing according to image, is the columns that the speed that reads and change-over circuit have limited array.
Claims (8)
1. time delay integration imageing sensor comprises that each pixel comprises by the array (10 ') of the pixel (Px) of row and column tissue:
-the first light-sensitive element (D1);
-memory node (A, C2);
-the first transfer element (TGM) is connected between this first light-sensitive element (D1) and this memory node (A);
It is characterized in that each pixel (Px) comprising:
-the second light-sensitive element (D1 ');
-the second transfer element (TGH) is connected between this second light-sensitive element (D1 ') and this memory node (A);
-Di three transfer elements (TGB) are connected between second light-sensitive element (D1 ') of neighbor of this memory node (A) and these row,
And it is characterized in that, this imageing sensor comprises: control circuit (15), be configured to side by side this first and second transfer element (TGM, TGH) order is cut-off state for conducting state and with the 3rd transfer element (TGB) order, and in different phase, be configured to side by side this first and the 3rd transfer element (TGM, TGB) order is cut-off state for conducting state and with this second transfer element (TGH) order.
2. according to the imageing sensor of claim 1, it is characterized in that it comprises:
-at every row of pixel (Px), be the public bus (L) that reads for each pixel of this row; And
-at every row of pixel, be the public selection wire (CS) that reads for each pixels of this row.
3. according to the imageing sensor of claim 2, it is characterized in that it comprises the array (16) of memory cell (∑), be connected to and read bus (L), come the intensity level that is accumulated of several row of storage pixel (Px) with row by memory cell.
4. according to the imageing sensor of claim 1, it is characterized in that it comprises: the parts (RST) that are used to carry out the correlated-double-sampling of each pixel (Px).
5. according to the imageing sensor of claim 1, it is characterized in that this first and second light-sensitive element (D1, D1 ') is the pinprick diode of identical dimensional.
6. method that is used for lagged product partial image transducer administrative time, this time delay integration imageing sensor comprises the array (10 ') by the pixel (Px) of row and column tissue, at each pixel of row, this method comprises following step in succession:
First and second light-sensitive elements (D1, D1 ') of this pixel of exposure during preceding half section (T1);
The intensity level of this first light-sensitive element (D1) is transferred to the memory node (A) of this pixel, and the intensity level of this second light-sensitive element (D1 ') is transferred to the memory node (A) of this pixel;
This first and second light-sensitive element of this pixel of exposure during the later half period (T2);
The intensity level of this first light-sensitive element (D1) is transferred to the memory node (A) of this pixel, and the intensity level of this second light-sensitive element (D1 ') is transferred to the memory node (A) of the neighbor of these row; And
Read the intensity level that is accumulated in the memory node (A) of this pixel.
7. according to the method for claim 6, may further comprise the steps:
At the intensity level that is accumulated (SIG) that reads this pixel (Px) at every turn before, read the reference level (REF) of this pixel; And
From the intensity level that is accumulated, deduct this reference level.
8. according to the method for claim 6, it is characterized in that, side by side order the pixel (Px) of same row, and during the same period, one after the other each row is carried out addressing.
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| Application Number | Priority Date | Filing Date | Title |
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| FR1002360A FR2961019B1 (en) | 2010-06-03 | 2010-06-03 | LINEAR IMAGE SENSOR IN CMOS TECHNOLOGY |
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| CN2011101470867A Pending CN102271227A (en) | 2010-06-03 | 2011-06-02 | Linear image sensor in cmos technology |
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| US (2) | US8817150B2 (en) |
| EP (1) | EP2398230B1 (en) |
| JP (1) | JP2011259428A (en) |
| CN (1) | CN102271227A (en) |
| FR (3) | FR2961019B1 (en) |
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| CN106129072B (en) * | 2015-05-08 | 2019-07-26 | 豪威科技股份有限公司 | Stacked chips share pixel structure |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2961021A1 (en) | 2011-12-09 |
| US8817150B2 (en) | 2014-08-26 |
| FR2961021B1 (en) | 2013-09-27 |
| FR2961020B1 (en) | 2013-03-15 |
| FR2961019B1 (en) | 2013-04-12 |
| US20130286266A1 (en) | 2013-10-31 |
| EP2398230B1 (en) | 2017-05-03 |
| JP2011259428A (en) | 2011-12-22 |
| EP2398230A2 (en) | 2011-12-21 |
| FR2961020A1 (en) | 2011-12-09 |
| EP2398230A3 (en) | 2012-09-26 |
| US20110298956A1 (en) | 2011-12-08 |
| FR2961019A1 (en) | 2011-12-09 |
| US9172851B2 (en) | 2015-10-27 |
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