CN102263059B - Manufacturing method for integrating schottky diode and power transistor on base material - Google Patents
Manufacturing method for integrating schottky diode and power transistor on base material Download PDFInfo
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- CN102263059B CN102263059B CN 201010186754 CN201010186754A CN102263059B CN 102263059 B CN102263059 B CN 102263059B CN 201010186754 CN201010186754 CN 201010186754 CN 201010186754 A CN201010186754 A CN 201010186754A CN 102263059 B CN102263059 B CN 102263059B
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Abstract
The invention relates to a manufacturing method for integrating a schottky diode and a power transistor on a base material. The manufacturing method comprises the following steps: providing a base material, wherein a transistor area and a schottky diode area are defined on the upper surface of the substrate; forming at least one first trench in the transistor area and at least two second trenchesin the schottky diode area; forming a grid polycrystalline silicon structure in the first trench, forming a second grid polycrystalline silicon structure which is filled in the second trenches and atleast covers the schottky diode area among the second trenches; forming a main body and a source doped area between the first trench and the second trenches in sequence; forming an interlayer dielectric structure for covering the grid polycrystalline silicon structure and a part of the second grid polycrystalline silicon structure so as to define a source contact window on the main body and define a schottky contact window on the second grid polycrystalline silicon structure; and finally, forming a source metal layer and filling the source metal layer into the source contact window and the schottky contact window.
Description
Technical field
The present invention relates to a kind of manufacture method of power semiconductor structure, particularly about a kind of integration power transistor and Schottky diode (Schottky diode) in the manufacture method of base material.
Background technology
In the application of groove power semiconductor, more and more pay attention to the performance of switch speed, the improvement of this characteristic promotes the switch cost that can obviously help in the high-frequency circuit operation.Utilizing Schottky diode to improve the switch cost of power semiconductor assembly, is a common solution.
Fig. 1 utilizes Schottky diode SD1 to improve the circuit diagram of the switch cost of MOS (metal-oxide-semiconductor) transistor T1.As shown in FIG., the body diode of MOS (metal-oxide-semiconductor) transistor T1 (bodydiode) D1 is parallel to Schottky diode SD1.Because the starting resistor of Schottky diode SD is lower than body diode D1.Therefore, when there was forward bias voltage drop in the source-drain electrode of MOS (metal-oxide-semiconductor) transistor T1, Schottky diode SD1 can avoid body diode D1 to be switched on (turn on).That is in the case, electric current is to flow to drain D by source S via Schottky diode SD1.
It should be noted that, changed in the process of not conducting (turnoff) by conducting compared to body diode D1, because existing, minority carrier (minority carrier) can cause time delay, Schottky diode does not have minority carrier, therefore, can avoid time delay, and help to improve switch cost.
Summary of the invention
Therefore, main purpose of the present invention provides a kind of groove power semiconductor structure and preparation method thereof, can utilize existing semiconductor making method, be parallel to this groove-type power transistor at the transistorized Schottky diode of making simultaneously of making groove-type power.
For achieving the above object, the invention provides a kind of integration power transistor and Schottky diode (Schottky diode) in the manufacture method of same base material.This manufacture method is applicable to groove-type power transistor AND gate plane formula power transistor.With regard to the groove-type power transistor, at first, provide the base material of one first conductivity type.Subsequently, form at least one grid polycrystalline silicon structure and one second polysilicon structure in base material, second polysilicon structure has a upper surface of at least a portion covering substrates, specifically comprises: form at least one first groove and at least two second grooves in base material.Next, form a dielectric layer in the inner surface of first groove and second groove.Then, form at least one grid polycrystalline silicon structure in first groove.Next, form one second polysilicon structure and insert in second groove, and cover the upper surface of the base material between second groove.Next, form the source doping region of the body of at least one second conductivity type and one first conductivity type between grid polycrystalline silicon structure and second polysilicon structure in ion implantation mode.Then, form an interlayer dielectric layer on the grid polycrystalline silicon structure, defining the one source pole contact hole, and exposed part second polysilicon structure at least.At last, and be removed to small part second polysilicon structure, to form a Schottky contacts window bare substrate.
According to one embodiment of the invention, interlayer dielectric layer has a first and a second portion, and wherein, first's cover gate polysilicon structure, second portion be a upper surface of cover part second polysilicon structure then.Has an opening between first and second portion to define the source electrode contact hole.
In one embodiment of this invention, the source electrode contact hole is defined between interlayer dielectric layer and second polysilicon structure.
With regard to the plane formula power transistor, according to one embodiment of the invention, grid polycrystalline silicon structure and second polysilicon structure are positioned at the upper surface of base material fully.
To sum up, manufacture method provided by the present invention helps to reduce manufacturing cost.
Can be further understood by following detailed Description Of The Invention and appended accompanying drawing about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 utilizes Schottky diode to improve the circuit diagram of the switch cost of power transistor;
Fig. 2 A to Fig. 2 E integrates power transistor and Schottky diode in first embodiment of the manufacture method of same base material for the present invention;
Fig. 3 A to Fig. 3 E integrates power transistor and Schottky diode in second embodiment of the manufacture method of same base material for the present invention;
Fig. 4 A to Fig. 4 E integrates power transistor and Schottky diode in the 3rd embodiment of the manufacture method of same base material for the present invention;
Fig. 5 A to Fig. 5 E integrates power transistor and Schottky diode in the 4th embodiment of the manufacture method of same base material for the present invention;
Fig. 6 A to Fig. 6 E integrates power transistor and Schottky diode in the 5th embodiment of the manufacture method of same base material for the present invention.
[main element description of reference numerals]
Schottky diode SD1
MOS (metal-oxide-semiconductor) transistor T1
Body diode D1
Grid G
Source S
Drain D
Silicon substrate 100,200
Epitaxial layer 110,210
Transistor area A1, A2
Schottky diode area B1, B2
The first groove 120a
The second groove 120b
Dielectric layer 130,230
Grid polycrystalline silicon structure 142,242
Second polysilicon structure 144,244,444
Drift region 150c, 250c
Source electrode patterned layer 160,260
Source doping region 162,262,362
Heavily doped region 164,264,364,464,564
The first 172,272 of interlayer dielectric layer
The second portion 174,274 of interlayer dielectric layer
Source electrode contact hole 176,276,376,476,576
Schottky contacts window 178,278,478,578
Source metal 180,280
Embodiment
Fig. 2 A to Fig. 2 E integrates power transistor and Schottky diode (Schottkydiode) in first embodiment of the manufacture method of same base material for the present invention.Present embodiment is integrated in same base material with the groove-type power transistor and Schottky diode.Shown in Fig. 2 A, at first, provide the silicon substrate 100 of one first conductivity type, and the epitaxial layer 110 that forms one first conductivity type is on this silicon substrate 100, to constitute the base material of this semiconductor structure.The upper surface definable of this epitaxial layer 110 goes out at least one transistor area A1 and at least one schottky diode area B1, respectively in order to hold the groove-type power transistor and Schottky diode.Subsequently, form at least one first groove 120a in transistor area A1 and at least two second groove 120b in schottky diode area B1 (among the figure be example with four second groove 120b).Then, form the inner surface that a dielectric layer 130 covers the first groove 120a and the second groove 120b at least.Wherein, be formed at the interior dielectric layer 130 of the first groove 120a namely as the transistorized gate dielectric of groove-type power.
Subsequently, shown in Fig. 2 B, deposit a polysilicon layer (not shown) on epitaxial layer 110, and impose micro image etching procedure, form a grid polycrystalline silicon structure 142 in the first groove 120a, form one second polysilicon structure 144 simultaneously in the top of the second groove 120b.Grid polycrystalline silicon structure 142 is as the transistorized grid of groove-type power.Second polysilicon structure 144 has a plurality of extensions to be inserted in these second grooves 120b, and covers the upper surface of the epitaxial layer 110 of these second grooves 120b.
Next, be shielding with second polysilicon structure 144, implant second conductivity type and be doped in the epitaxial layer 110.This ion implantation step forms body 150a around the first groove 120a except meeting in transistor area A1, also can form body 150b between the first groove 120a and the second groove 120b.But, because the existence of second polysilicon structure 144, between the adjacent second groove 120b, can not form the body of second conductivity type.Next, utilize the one source pole light shield, form one source pole patterned layer 160 in body 150a, on the 150b, to define the position of source electrode.Then, utilize this source electrode patterned layer 160 and second polysilicon structure 144 for shielding, implant first conductivity type and be doped in body 150a, in the 150b, forming a plurality of source doping region 162 in body 150a, in the 150b.With regard to body 150b, have two source doping region 162 and be adjacent to the first groove 120a and the second groove 120b respectively.
Subsequently, shown in Fig. 2 C, deposit interlayer dielectric material (not shown) cover gate polysilicon structure 142, epitaxial layer 110 and second polysilicon structure 144 comprehensively.Then, remove in the lithography mode and to be positioned at body 150a, the part interlayer dielectric material of 150b top is to form an interlayer dielectric layer.This interlayer dielectric layer has a first 172 and at least one second portion 174 on epitaxial layer 110.Wherein, first's 172 cover gate polysilicon structures 142.Second portion 174 covers the side of second polysilicon structure 144 fully, but only covers the part upper surface of second polysilicon structure 144.And 174 of first 172 and second portions define source electrode contact hole 176.Subsequently, utilize interlayer dielectric layer for shielding, implant second conductivity type and be doped in body 150a, in the 150b, to form heavily doped region 164 between adjacent two source doping region 162.
As shown in FIG., in the present embodiment, the second portion 174 of interlayer dielectric layer is positioned at the top of the second groove 120b that is adjacent to transistor area A1, and, only cover second groove 120b and the adjacent domain thereof be positioned under it, and do not extend to other the second groove 120b.With regard to an embodiment, the width of this second portion 174 can roughly be equal to the width of first 172.Secondly, the schottky diode area B1 that present embodiment is defined on the base material is positioned between two transistor area A1, and this interlayer dielectric layer has the relative both sides that two second portions 174 lay respectively at schottky diode area B1.Between these two second portions 174, define a Schottky contacts window 178.
Next, shown in Fig. 2 D, utilize interlayer dielectric layer to be shielding, with the anisotropic etching technology, etching is exposed to outer epitaxial layer 110 and second polysilicon structure 144, forms source electrode contact hole 176 in body 150a, in the 150b, with exposed source doping region 162 and aforementioned heavily doped region 164.This etching step forms Schottky contacts window 178 simultaneously in second polysilicon structure 144, with drift region (drift region) 150c in the exposed epitaxial layer 110.Generally speaking, before carrying out this etching step, can impose a heat earlier and drive in (drive-in) step, the scope of heavily doped region 164 is goed deep in the epitaxial layer 110, to guarantee after forming source electrode contact hole 176, still to possess part heavily doped region 164 in the bottom of source electrode contact hole 176.
Shown in Fig. 2 E, after the making of finishing source electrode contact hole 176 and Schottky contacts window 178, deposition one source pole metal level 180 covers interlayer dielectric layer, and inserts source electrode contact hole 176 and Schottky contacts window 178, to form Schottky diode in the bottom surface of Schottky contacts window 178.
The manufacture method of present embodiment is in the step of making grid polycrystalline silicon structure 142, make second polysilicon structure 144 simultaneously in schottky diode area B1, and utilize this second polysilicon structure 144, prevent that follow-up ion implantation step from mixing in schottky diode area B1 implantation.In addition, second polysilicon structure 144 is not electrically connected to grid (being grid polycrystalline silicon structure 142), and is electrically connected to source electrode (being source doping region 162).In addition, the manufacture method of present embodiment in making the step of interlayer dielectric layer, except forming first's 172 cover gate polysilicon structures 142, also form simultaneously second portion 174 on second polysilicon structure 144 to define Schottky contacts window 178.And utilize subsequent etch body 150a, 150b is to form the step of source electrode contact hole 176, and second polysilicon structure 144 of etching simultaneously is to form Schottky contacts window 178.Therefore, the manufacture method that present embodiment provides can directly be applied mechanically to the transistorized manufacture method of general plough groove type, and helps to reduce manufacturing cost.
Secondly, please refer to shown in Fig. 2 E, because second polysilicon structure 144 sees through source metal 180 and is electrically connected to source electrode, when source electrode and drain electrode (are body 150a, when being subjected to reverse blas the epitaxial layer 110 of 150b below), the scope that is positioned at second groove 120b exhaustion region (depletionregion) on every side can enlarge, and helps to promote Schottky diode for the resistivity of reverse blas.Distance between adjacent two second groove 120b can influence the folder that causes of second polysilicon structure 144 (pinch off) effect only, and then influence Schottky diode for the resistivity of reverse blas.With regard to a preferred embodiment, the spacing distance of adjacent two second groove 120b is preferably less than the spacing distance of adjacent two first groove 120a.
Fig. 3 A to Fig. 3 E integrates power transistor and Schottky diode in second embodiment of the manufacture method of same base material for the present invention.Present embodiment is integrated in same base material with plane formula power transistor and Schottky diode.As shown in Figure 3A, at first, provide the silicon substrate 200 of one first conductivity type, and the epitaxial layer 210 that forms one first conductivity type is on this silicon substrate 200, to constitute the base material of this semiconductor structure.Upper surface definable at epitaxial layer 210 goes out at least one transistor area A2 and at least one schottky diode area B2, respectively in order to hold the groove-type power transistor and Schottky diode.Subsequently, form a dielectric layer 230 in the upper surface of epitaxial layer 210.
Next, deposit a polysilicon layer (not shown) on epitaxial layer 210, and impose micro image etching procedure, to form a grid polycrystalline silicon structure 242 and one second polysilicon structure 244 on epitaxial layer 210.Wherein, grid polycrystalline silicon structure 242 is positioned at transistor area A2, with the grid as the plane formula power transistor.Second polysilicon structure 244 is positioned at schottky diode area B2.And this second polysilicon structure 244 is made of at least one block (with two block 244a disconnected from each other, 244b is example among the figure).Next, be shielding with grid polycrystalline silicon structure 242 and second polysilicon structure 244, implant second conductivity type and be doped in the epitaxial layer 210.This ion implantation step forms body 250a except meeting between grid polycrystalline silicon structure 242 and second polysilicon structure 244, also can form body 250b between 244b at adjacent two block 244a of second polysilicon structure 244.
Next, shown in Fig. 3 B, utilize the one source pole light shield, form one source pole patterned layer 260 in body 250a, on the 250b, to define the position of source electrode.Subsequently, utilize this source electrode patterned layer 260, grid polycrystalline silicon structure 242 and second polysilicon structure 244 for shielding, implant first conductivity type to be doped in the epitaxial layer 210, forming a plurality of source doping region 262 in body 250a, in the 250b.
Next, shown in Fig. 3 C, deposit interlayer dielectric material (not shown) cover gate polysilicon structure 242, epitaxial layer 210 and second polysilicon structure 244 comprehensively.Then, remove unnecessary portions in the lithography mode, to form an interlayer dielectric layer on epitaxial layer 210.This interlayer dielectric layer has a first 272 and at least one second portion 274.Wherein, first's 272 cover gate polysilicon structures 242.Second portion 274 covers second polysilicon structure 244.In the second portion 274 of interlayer dielectric layer and have a plurality of openings 275 with each block 244a of exposed second polysilicon structure 244,244b.In addition, 274 of the first 272 of interlayer dielectric layer and second portions form one source pole contact hole 276, with exposed source doping region 262.Aforementioned each opening 275 namely defines the position of Schottky contacts window.Subsequently, utilize interlayer dielectric layer and second polysilicon structure 244 for shielding, implant second conductivity type and be doped in body 250a, in the 250b, to form heavily doped region 264 in body 250a, in the 250b.
Next, shown in Fig. 3 D, utilizing the first 272 of interlayer dielectric layer and second portion 274 is shielding, with anisotropic etching technology etching second polysilicon structure 244, to form at least one Schottky contacts window 278.These Schottky contacts windows 278 run through each block 244a of second polysilicon structure 244, and 244b is with exposed each block 244a that is positioned at, the drift region 250c of 244b below.At last, shown in Fig. 3 E, form one source pole metal level 280 and cover interlayer dielectric layer, and insert source electrode contact hole 276 and Schottky contacts window 278, to form Schottky diode in Schottky contacts window 278 bottom surfaces.
It should be noted that in etching to form in the step of Schottky contacts window 278, outside the first 272 of interlayer dielectric layer and the epitaxial layer 210 between the second portion 274 are exposed to.The epitaxial layer 210 of this part can be simultaneously etched in the step that forms Schottky contacts window 278, and make the bottom surface of source electrode contact hole 276 extend downwards.For guaranteeing to still have part heavily doped region 264 to be retained in source electrode contact hole 276 bottoms through behind this etching step.Please refer to Fig. 3 C and Fig. 3 D, present embodiment is divided into two stages with the step that etching forms source electrode contact hole 276 and Schottky contacts window 278.Shown in Fig. 3 C, through behind the etching step of phase I, the bottom surface of source electrode contact hole 276 has been positioned at body 250a, and in the 250b, but the bottom surface of Schottky contacts window 278 still is arranged in second polysilicon structure 244, does not extend to epitaxial layer 210 as yet.After implantation second conductivity type mixes to form the step of heavily doped region 264, shown in Fig. 3 D, the etching step of second stage makes Schottky contacts window 278 run through second polysilicon structure 244 downwards, with the exposed drift region 250c that is positioned at second polysilicon structure, 244 belows.As described above, the step that etching is formed source electrode contact hole 276 and Schottky contacts window 278 is divided into two stages, can make heavily doped region 264 go deep into body 250a, in the 250b, can avoid simultaneously causing heavily doped region 264 to be removed fully because the etch depth in single stage is excessive.
Fig. 4 A to Fig. 4 E integrates power transistor and Schottky diode in the 3rd embodiment of the manufacture method of same base material for the present invention.Present embodiment is integrated in same base material with the groove-type power transistor and Schottky diode.Please refer to shown in Fig. 4 B and the 4C, the main difference of present embodiment and the first embodiment of the present invention is that present embodiment has omitted the source electrode patterned layer 160 of Fig. 2 B, directly implants first conductivity type and is doped into body 150a, the surf zone of 150b is to form source doping region 362.In addition, present embodiment is not after forming interlayer dielectric layer, implant second conductivity type immediately and mix to form heavily doped region 164, but form source electrode contact hole 376 earlier in body 150a, 150b is interior with exposed source doping region 362, and then implant second conductivity type and be doped in body 150a, in the 150b, to form heavily doped region 364 in the bottom of source electrode contact hole 376.
Fig. 5 A to Fig. 5 E integrates power transistor and Schottky diode in the 4th embodiment of the manufacture method of same base material for the present invention.Present embodiment is integrated in same base material with the groove-type power transistor and Schottky diode.Please refer to shown in Fig. 5 B, the main difference of present embodiment and the third embodiment of the present invention is, second polysilicon structure 444 of present embodiment made, the second groove 120b that its side rough alignment is corresponding and the intersection of body 150b.This second groove 120b is adjacent to the first groove 120a in the transistor area A1.In addition, shown in 5C figure, the interlayer dielectric layer of present embodiment does not have the second portion 174 shown in 2C figure.Present embodiment directly utilizes the space of 444 of the first 172 of interlayer dielectric layer and second polysilicon structures, defines source electrode contact hole 476.
Shown in Fig. 5 C, the manufacture method of present embodiment directly utilizes interlayer dielectric layer to be shielding behind the first's 172 cover gate polysilicon structures 142 that form interlayer dielectric layer, and etching epitaxial layer 140 is to form source electrode contact hole 476.Subsequently, see through interlayer dielectric layer and second polysilicon structure 444, implant second conductivity type in ion implantation mode and be doped into body 150a, 150b is interior to form a heavily doped region 464 in the bottom of source electrode contact hole 476.It should be noted that in aforementioned etching step second polysilicon structure 444 can be by the while skiving.Removed fully and expose epitaxial layer 110 surfaces for avoiding being covered in second polysilicon structure 444 on the epitaxial layer 110, second polysilicon structure 444 that is covered on the epitaxial layer 110 must have adequate thickness.
Shown in Fig. 5 D, forming heavily doped region 464 after the step of the bottom of source electrode contact hole 476, utilize etching mode, removal is covered in second polysilicon structure 444 on epitaxial layer 110 surfaces, exposing the drift region 150c that is positioned at second polysilicon structure, 444 belows, that is form a Schottky contacts window 478.This etching step together with the time remove the epitaxial layer 110 of part, and cause the degree of depth of source electrode contact hole 476 to be deepened.For guaranteeing through behind this etching step, still can possess part heavily doped region 464 in the bottom of source electrode contact hole 476, before the etching step that carries out Fig. 5 D, can impose a heat earlier and drive in step, make heavily doped region 464 go deep into body 150a, in the 150b.At last, shown in Fig. 5 E, form one source pole metal level 180 and cover dielectric structure 172 between ground floor, and insert source electrode contact hole 476, to form Schottky diode in schottky diode area B1.
Fig. 6 A to Fig. 6 E integrates power transistor and Schottky diode in the 5th embodiment of the manufacture method of same base material for the present invention.Present embodiment is integrated in same base material with plane formula power transistor and Schottky diode.Please refer to shown in Fig. 6 C, the main difference of present embodiment and the second embodiment of the present invention is, the interlayer dielectric layer of present embodiment does not have the second portion 274 shown in Fig. 3 C, and present embodiment is directly to utilize the first 272 of interlayer dielectric layer and the position that second polysilicon structure 244 defines source electrode contact hole 576.
Shown in Fig. 6 C, behind the first's 272 cover gate polysilicon structures 242 that form interlayer dielectric layer, utilize interlayer dielectric layer to be shielding immediately, etching epitaxial layer 210 is to form source electrode contact hole 576 between interlayer dielectric layer and second polysilicon structure 244.It should be noted that in this etching step being exposed to the second outer polysilicon structure 244 can be by the while skiving.Removed fully for fear of second polysilicon structure 244 and cause outside epitaxial layer 210 is exposed to, second polysilicon structure 244 must have enough thickness.
After forming source electrode contact hole 576, implant second conductivity type immediately and be doped in body 250a, in the 250b, to form heavily doped region 564 in the bottom of source electrode contact hole 576.Next, impose heat and drive in step, make heavily doped region 564 go deep into body 250a, in the 250b.Then, shown in Fig. 6 D, utilize etching mode, remove second polysilicon structure 244 that is covered on the epitaxial layer 210, with the exposed drift region 250c that is positioned at second polysilicon structure, 244 belows, that is form a Schottky contacts window 578.At last, shown in Fig. 6 E, form one source pole metal level 280 and cover dielectric structure 272 between ground floor, and insert source electrode contact hole 576 and Schottky contacts window 578.
But the above only is preferred embodiment of the present invention, can not limit scope of the invention process with this, and namely all simple equivalent of doing according to claim of the present invention and description of the invention content change and revise, and all still belongs in the scope that the present invention contains.Arbitrary embodiment of the present invention or claim must not reach disclosed whole purposes or advantage or characteristics in addition.In addition, summary part and denomination of invention only are the usefulness of auxiliary patent document search, are not to limit protection scope of the present invention.
Claims (12)
1. integrate Schottky diode and power transistor in the manufacture method of base material for one kind, it is characterized in that, comprise the following steps:
The base material of one first conductivity type is provided;
Form at least one grid polycrystalline silicon structure and one second polysilicon structure in this base material, this second polysilicon structure has the upper surface that at least a portion covers this base material;
Form the source doping region of the body of at least one second conductivity type and one first conductivity type between this grid polycrystalline silicon structure and this second polysilicon structure in ion implantation mode;
Form an interlayer dielectric layer on this grid polycrystalline silicon structure, this interlayer dielectric layer has a first and a second portion, this first covers this grid polycrystalline silicon structure, this second portion is a upper surface of this second polysilicon structure of cover part, with this second polysilicon structure of exposed part at least, has an opening between this first and this second portion to define the one source pole contact hole; And
Be removed to this second polysilicon structure of small part, forming exposed this base material of a Schottky contacts window, and this source electrode contact hole is in the step that forms this Schottky contacts window, is formed at simultaneously in this body.
2. manufacture method as claimed in claim 1 is characterized in that, forms this grid polycrystalline silicon structure and this second polysilicon structure comprises in the step of this base material:
Form at least one first groove and at least two second grooves in this base material;
Form a dielectric layer in the inner surface of this first groove and described a plurality of second grooves;
Form this grid polycrystalline silicon structure in this first groove; And
Form this second polysilicon structure and insert in described a plurality of second groove, and cover this upper surface of this base material between described a plurality of second groove.
3. manufacture method as claimed in claim 2 is characterized in that, the quantity of this second groove is more than or equal to three.
4. manufacture method as claimed in claim 2 is characterized in that, the step that forms this source doping region comprises: form on a photoresistance pattern and this body, to define at least two source doping region respectively in abutting connection with this first groove and this second groove.
5. manufacture method as claimed in claim 1 is characterized in that, define the step of this source electrode contact hole after, more comprise seeing through the doping that this source electrode contact hole is implanted one second conductivity type, to form a heavily doped region in this body.
6. manufacture method as claimed in claim 2 is characterized in that, this second portion is to aim at this corresponding second groove.
7. manufacture method as claimed in claim 2 is characterized in that, a side of this second polysilicon structure is the intersection of aiming at this second groove and this body.
8. manufacture method as claimed in claim 2 is characterized in that, this source electrode contact hole is to be defined between this interlayer dielectric layer and this second polysilicon structure.
9. manufacture method as claimed in claim 1 is characterized in that, this grid polycrystalline silicon structure is to make with step with this second polysilicon structure.
10. manufacture method as claimed in claim 1 is characterized in that, this grid polycrystalline silicon structure and this second polysilicon structure are to be positioned at fully on this upper surface of this base material.
11. manufacture method as claimed in claim 1 is characterized in that, form the step of this interlayer dielectric layer after, more comprise seeing through this this body of interlayer dielectric layer etching, to form this source electrode contact hole.
12. manufacture method as claimed in claim 10 is characterized in that, forms the step of this Schottky contacts window, is with the anisotropic etching technology, removes this second polysilicon structure fully.
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| CN103840014B (en) * | 2012-11-21 | 2016-11-23 | 上海华虹宏力半导体制造有限公司 | A kind of groove-shaped Schottky diode device structure and process implementation method |
| CN105957865A (en) * | 2016-06-27 | 2016-09-21 | 电子科技大学 | MOSFET (Metal Oxide Semiconductor Field Effect Transistor) integrated with trench Schottky |
| CN108470719B (en) * | 2018-04-28 | 2023-07-07 | 江苏新顺微电子股份有限公司 | Composite TMBS device and manufacturing method thereof |
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| US20070075364A1 (en) * | 2005-09-30 | 2007-04-05 | Analog Power Intellectual Properties Limited | Power MOSFETs and methods of making same |
| US7732842B2 (en) * | 2006-12-06 | 2010-06-08 | Fairchild Semiconductor Corporation | Structure and method for forming a planar schottky contact |
| CN102214603B (en) * | 2010-04-06 | 2013-09-04 | 科轩微电子股份有限公司 | Power semiconductor structure with schottky diode and manufacturing method thereof |
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