CN102262904B - Large bit-per-cell three-dimensional mask-programmable memory - Google Patents
Large bit-per-cell three-dimensional mask-programmable memory Download PDFInfo
- Publication number
- CN102262904B CN102262904B CN201010194950.4A CN201010194950A CN102262904B CN 102262904 B CN102262904 B CN 102262904B CN 201010194950 A CN201010194950 A CN 201010194950A CN 102262904 B CN102262904 B CN 102262904B
- Authority
- CN
- China
- Prior art keywords
- storage element
- film
- mprom
- resistive
- conductive membrane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention provides a large bit-per-cell three-dimensional mask-programmable memory (3D-MPROMB), each storage element of which can store multidigit (such as four bits) information. By the addition of resistor films and/or resistor elements in a storage element, 3D-MPROMB increases the storage element voltage-current curve adjustable range.
Description
Technical field
The present invention relates to integrated circuit fields, or rather, relate to mask-programmable memory.
Background technology
Mask-programmable memory (mask-programmable read-only memory, referred to as mask-ROM) refers in process of production, the storer of especially logging data in photoetching process.Three-dimensional masking film program storer (three-dimensional mask-programmable memory, referred to as 3D-MPROM) is a kind of mask-ROM containing multiple mutual overlay masking program storage layer.Compared with other mask-ROM, 3D-MPROM has great capacity and extremely low cost.
Chinese patent " 3 D ROM and manufacture method thereof " (patent No.: ZL98119572.5) proposes multiple 3D-MPROM.Fig. 1 describes a kind of typical 3D-MPROM.It contains an a Semiconductor substrate 0s and 3D-MPROM heap 0.Transistor in Semiconductor substrate 0s forms the peripheral circuit of 3D-MPROM.3D-MPROM heap 0 is stacked on substrate 0s.In this example, 3D-MPROM heap 0 is containing two accumulation layers 100,200, and accumulation layer 200 is stacked in accumulation layer 100.Each accumulation layer (as 100) is upper containing many address wires (as 20a, 20b, 30a...) and multiple 3D-MPROM storage element (referred to as 3D-MPROM unit) (as 1aa, 1ab...).Contact channels hole (as 30av, 30av ') accumulation layer (as 100,200) and substrate 0s are coupled.
In conventional art, most of 3D-MPROM adopts scale-of-two, namely 3D-MPROM unit has two states ' 1 ' and ' 0 ': storage element (' 1 ' storage element) the energy On current being in state ' 1 ', the storage element (' 0 ' storage element) being in state ' 0 ' then can not.Each scale-of-two 3D-MPROM unit can store 1 information.
As shown in Figure 2 A, ' 1 ' storage element 1aa contains a high address line 20a, an one deck ROM film 3a and low address line 30a.ROM film 3a contains accurate conductive membrane 5.This accurate conductive membrane 5 has nonlinear resistance property, and its good conductivity is in one direction in other direction.Accurate conductive membrane 5 generally adopts diode.Here, it is a p-i-n diode, and containing p film 12, i film 14 and n film 16.Accurate conductive membrane 5 also can be other diode, as pn diode, schottky diode etc.Due in insulating medium 11 containing access opening 18, when add on high address line 20a read voltage time, low address line 30a can measure read current.This corresponds to state ' 1 '.
As shown in Figure 2 B, ' 0 ' storage element 1ba contains a high address line 20b, an one deck ROM film 3b and low address line 30a.ROM film 3b contains dielectric insulating film 11.Due in insulating medium 11 not containing access opening, when add on high address line 20b read voltage time, low address line 30a can not measure read current.This corresponds to state ' 0 '.
Except scale-of-two, 3D-MPROM also can adopt N (N is positive integer and N > 2) system, and namely 3D-MPROM unit has N kind state, and the storage element being in different conditions has different volt-ampere characteristics.Each N system 3D-MPROM unit can store b position information.Here, b=log
2(N); B can be integer, also can be non-integer.(number of patent application: 200610100860.8) describe multiple N system 3D-MPROM comprises knot shape type N system 3D-MPROM and junction characteristic type N system 3D-MPROM to Chinese patent application " N ary mask-programmable memory ".
In knot shape type N system 3D-MPROM, the storage element of different conditions has different structures, as different knot shapes.As shown in Figure 2 C, a knot shape type storage element 1ca contains a high address line 20c, an one deck ROM film 3c and low address line 30a.ROM film 3c contains one deck insulating medium 11, passage portion hole 18 ' and the accurate conductive membrane 5 of one deck.Compared with Fig. 2 A, passage portion hole 18 ' can only by high address line 20c and accurate conductive membrane 5 partial coupling.Correspondingly, storage element 1ca has different volt-ampere characteristics from storage element 1aa.
In junction characteristic type N system 3D-MPROM, the storage element of different conditions has different junction characteristics, as different doping contents.As shown in Figure 2 D, a junction characteristic type storage element 1da contains a high address line 20d, an one deck ROM film 3d and low address line 30a.ROM film 3a (Fig. 2 A) in ROM film 3d and storage element 1aa has similar structure, and they are all containing p-i-n diode.But the diode 5 ' of ROM film 3d has different doping contents from the diode 5 of ROM film 3a.This can be realized by photoetching and ion implantation.Correspondingly, storage element 1da has different volt-ampere characteristics from storage element 1aa.
This further improves the implementation method of above-mentioned patented claim clearly, so as in larger scope (as ~ 4.5V or larger) the V.A. curve of adjustment storage element, thus realize multidigit unit (as 4 bits).In this manual, b bit (b-bit-per-cell) refers to that each storage element can store b position information, as in 4 bit storeies, each storage element can store 4 information.Correspondingly, (large bit-per-cell 3D-MPROM, referred to as 3D-MPROM for this kind of multidigit unit of clearly demarcated proposition three-dimensional masking film program storer
b).
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of three-dimensional masking film program storer with vast capacity.
Another object of the present invention is to provide a kind of three-dimensional masking film program storer with Ultra Low Cost.
Another object of the present invention is to provide the three-dimensional masking film program storer that a kind of each storage element can store multidigit (as 4 or more) information.
According to these and other object, the invention provides a kind of multidigit unit three-dimensional masking film program storer (3D-MPROM
b), its each storage element can store multidigit (as 4) information.3D-MPROM
bby increasing resistive film and/or resistive element increases the adjustable scope of storage element V.A. curve in storage element.Correspondingly, 3D-MPROM
bthe 3D-MPROM containing resistive film can be divided into
b(3D-MPROM
bwith resistive layer, referred to as 3D-MPROM
rL) and containing the 3D-MPROM of resistive element
b(3D-MPROM
bwith resistive element, referred to as 3D-MPROM
rE).
3D-MPROM of the present invention
bcomprise: a Semiconductor substrate containing transistor; Multiple be stacked in substrate and with the masking film program accumulation layer of Substrate coupling, each accumulation layer contains the multiple masking film program storage elements comprising the first storage element and the second storage element, each storage element contains accurate conductive membrane, this accurate conductive membrane good conductivity is in one direction in other direction, described multiple storage element has N (N > 2) and plants state, and the storage element under different conditions has different volt-ampere characteristics; The threshold voltage of described first storage element is minimum in all states; The threshold voltage of described second storage element is greater than described first storage element, and described second storage element is at least more than described first storage element containing one deck resistive film.
3D-MPROM of the present invention
balso comprise: a Semiconductor substrate containing transistor; Multiple be stacked in substrate and with the masking film program accumulation layer of Substrate coupling, each accumulation layer contains the multiple masking film program storage elements comprising the first storage element and the second storage element, each storage element contains accurate conductive membrane, this accurate conductive membrane good conductivity is in one direction in other direction, described multiple storage element has N (N > 2) and plants state, and the storage element under different conditions has different volt-ampere characteristics; The threshold voltage of described first storage element is minimum in all states; The threshold voltage of described second storage element is greater than described first storage element, and the accurate conductive membrane of described second storage element contains higher resistive element concentration than the accurate conductive membrane of described first storage element.
Accompanying drawing explanation
Fig. 1 is the sectional drawing representing a kind of 3D-MPROM;
Fig. 2 A-Fig. 2 D is the sectional drawing representing ' 1 ' 3D-MPROM unit in conventional art, ' 0 ' 3D-MPROM unit, knot shape type N system 3D-MPROM unit, junction characteristic type N system 3D-MPROM unit;
Fig. 3 represents a kind of 4 bit 3D-MPROM
bthe volt-ampere characteristic of 16 kinds of states in (b=4, N=16);
Fig. 4 A-Fig. 4 D represents several containing resistive film 3D-MPROM
b(3D-MPROM
rL) unit sectional drawing;
Fig. 5 compares primitive, resistive film and 3D-MPROM
rLthe V.A. curve of unit;
Fig. 6 A-Fig. 6 D is the sectional drawing representing four kinds of resistive films;
Fig. 7 represents a kind of 3D-MPROM
rLthe vertical view of resistive film mask plate adopted, and in technological process the relative position of resistive film figure and height address wire figure;
Fig. 8 A-Fig. 8 C represents a kind of 3D-MPROM
rLthe technological process of unit.Structure in this figure is the sectional drawing along AA ' line in Fig. 7;
Fig. 9 A-Fig. 9 C represents that three kinds containing partial ohmic film 3D-MPROM
bthe sectional drawing of unit;
Figure 10 represents a kind of containing resistive element 3D-MPROM
b(3D-MPROM
rE) unit sectional drawing;
Figure 11 compares silicon diode, SiO
x(x < 2) diode and SiO
2the V.A. curve of film;
Figure 12 A and Figure 12 B represents 3D-MPROM
rEa kind of technological process of unit;
Figure 13 A-Figure 13 C represents three kind of 2 bit 3D-MPROM
bthe sectional drawing of (b=2, N=4);
Figure 14 A represents a kind of 2 bit 3D-MPROM
bcircuit diagram; Figure 14 B is the sequential chart of wordline and bit-line voltage when representing a kind of read operation;
Figure 15 A represents a kind of 4 bit 3D-MPROM
bthe form that (b=4, N=16) state is arranged; Figure 15 B represents a kind of 4 bit 3D-MPROM
bsectional drawing.
Except Figure 15 A, this Figure of description not drawn on scale.
Embodiment
The invention provides a kind of multidigit unit three-dimensional masking film program storer (3D-MPROM
b), its each storage element can store multidigit (as 4) information.Fig. 3 is a kind of 4 bit 3D-MPROM
bthe V.A. curve 410-425 of 16 kinds of states in (b=4, N=16).They and state ' 0 '-' f ' one_to_one corresponding.Notice that the current axis of this figure adopts index scale.When flowing through the controller electric current (I in storage element
t) time, storage element conducting, the voltage at this moment on storage element is threshold voltage (V
t).Such as, the threshold voltage of state ' 0 ' is V
t0; ...; The threshold voltage of state ' f ' is V
tf.This instructions adopts following specification: have less V
tstorage element be endowed less state value, as having minimum V
tstorage element be in state ' 0 '; There is the second little V
tstorage element be in state ' 1 '; ....Certainly, other specification is adopted also to be feasible.
In order to tolerate process change and reading error, adjacent states V
tinterval delta V
tgeneral needs ~ 0.3V or larger, therefore V
twindow-i.e. maximum V
t(V
tf) and minimum V
t(V
t0) difference-general needs ~ 4.5V or larger.In order to realize so large V
twindow, the present invention proposes in storage element, increase resistive film and/or resistive element.Correspondingly, 3D-MPROMB can be divided into the 3D-MPROM containing resistive film
b(3D-MPROM
rL) and containing the 3D-MPROM of resistive element
b(3D-MPROM
rE).
3D-MPROM
rLexample see Fig. 4 A-Fig. 9 C.Wherein, Fig. 4 A-Fig. 4 D describes multiple 3D-MPROM
rLunit.As shown in Figure 4 A, this storage element is a primitive 1za.Primitive 1za has minimum V in all states
t-V
t0.It contains multilayer film, comprises high address line 20z, ROM film 3z and low address line 30a.These films are called as basement membrane together.Wherein, address wire 20z, 30a contain conductor material, as highly doped polysilicon (poly Si), tungsten (W), titanium-tungsten (TiW), titanium nitride (TiN), copper (Cu) etc.ROM film 3z is only containing accurate conductive membrane 25.Accurate conductive membrane 25 has nonlinear resistance property, and its good conductivity is in one direction in other direction.Accurate conductive membrane 25 generally adopts diode.Here, it is a p-i-n diode, and containing p film 22, i film 24 and n film 26.About the details of accurate conductive membrane can with reference to Chinese patent ZL98119572.5.
Fig. 4 B describes the first 3D-MPROM
rLunit 1ea.It contains high address line 20e, ROM film 3e and low address line 30a.Address wire 20e, 30a contain conductor material.ROM film 3e, except accurate conductive membrane 25 (comprising p film 22, i film 24 and n film 26), also contains one deck resistive film 23.In this embodiment, resistive film 23 is positioned on accurate conductive membrane 25.At I
ttime, the resistance of resistive film 23 preferably close to or be greater than the resistance of accurate conductive membrane 25.Due to primitive 1za except address wire 20z, 30a only containing accurate conductive membrane 25, therefore the resistance of resistive film 23 preferably close to or be greater than the resistance of primitive 1za.
Fig. 4 C describes the second 3D-MPROM
rLunit 1fa.It contains high address line 20f, ROM film 3f and low address line 30a.Address wire 20f, 30a contain conductor material.ROM film 3f, except accurate conductive membrane 25 (comprising p film 22, i film 24 and n film 26), also contains one deck resistive film 23.In this embodiment, resistive film 23 is positioned among accurate conductive membrane 25, namely between top p film 22 and the i film 24 of centre.Similarly, at I
ttime, the resistance of resistive film 23 preferably close to or be greater than the resistance of primitive 1za.
Fig. 4 D describes the third 3D-MPROM
rLunit 1ga.It contains high address line 20g, ROM film 3g and low address line 30a.Address wire 20g, 30a contain conductor material.ROM film 3g, except accurate conductive membrane 25 (comprising p film 22, i film 24 and n film 26), also contains one deck resistive film 23.In this embodiment, resistive film 23 is positioned under accurate conductive membrane 25.Similarly, at I
ttime, the resistance of resistive film 23 preferably close to or be greater than the resistance of primitive 1za.
In order to form three-dimensional structure (namely multiple accumulation layer can be mutually stacked), the 3D-MPROM in same accumulation layer
rLunit (1ea/1fa/1ga.Here, "/" represents "or") and primitive 1za needs provide a good basis for accumulation layer above.That is, their high address line (20e/20f/20g, 20z) preferably can flattened (as adopt chemical mechanical polishing method, i.e. CMP method).This needs the thickness T of resistive film 23
rmeet following requirement: 1) in the embodiment of Fig. 4 C and Fig. 4 D, if ROM film (3f/3g, 3z) also needs flattened, T
rthe thickness T of the top film 22 of accurate conductive membrane 25 in primitive 1za should be less than
u; 2) in the embodiment of Fig. 4 B-Fig. 4 D, if ROM film (3e/3f/3g, 3z) does not need flattened, then T
rthe thickness T of high address line 20z in primitive 1za should be less than
a.
Fig. 5 compares primitive 1za, resistive film 23 and 3D-MPROM
rLthe V.A. curve of unit 1ea.They represent with 430,431 and 432 respectively.Due at 3D-MPROM
rLin unit 1ea, resistive film 23 and accurate conductive membrane 25 are cascaded, therefore 3D-MPROM
rLthe V.A. curve 432 of unit 1ea is offset by the V.A. curve 430 of accurate conductive membrane 25 (namely primitive 1za) to form, and side-play amount is determined by the V.A. curve 431 of resistive film 23: at I
ttime, 3D-MPROM
rLthe V of unit 1ea
tthe V of primitive 1za
t0with the voltage V on resistive film 23
rsum, i.e. V
t=V
t0+ V
r.
Fig. 6 A-Fig. 6 D is the sectional drawing of four kinds of resistive films.Wherein, the resistive film in Fig. 6 A 23 is containing one deck core resistive film 502.This core resistive film 502 has the exponential type volt-ampere characteristic shown in Fig. 5.It contains layer of semiconductor film, and/or the deielectric-coating that thin.Semiconductor material can be silicon (Si), carbon (C), germanium (Ge), carbon-silicon compound (SiC), germanium silicon compound (SiGe) etc.; It preferably has on-monocrystalline structure, as impalpable structure, microstructure or polycrystalline structure.An example of semiconductor film is the non-setting silicon of 45nm, and it can by storage element V
tskew ~ 4.5V or more.Deielectric-coating can be monox (SiO
2), silicon nitride (Si
3n
4) or other protective ceramic material (see Chinese patent ZL98119257.2).Although deielectric-coating is considered to dielectric film traditionally, when its very thin thickness, it has exponential type volt-ampere characteristic.Therefore, deielectric-coating is suitable for resistive film.The example of deielectric-coating comprises the monox of 5nm or the silicon nitride of 9nm, and these deielectric-coating can by V
tskew ~ 4.5V or more.
Fig. 6 B-Fig. 6 D describes other three kinds of resistive films 23.In fig. 6b, one deck barrier film 501 is contained above core resistive film 502; In figure 6 c, one deck barrier film 503 is contained below core resistive film 502; In figure 6d, core resistive film 502 upper and lower is respectively containing one deck barrier film 501,503.Barrier film provides a better interface for resistive film 23, and it can also as etching stopping film.In general, barrier film contains conductor material, as highly doped polysilicon (poly Si), tungsten (W), titanium-tungsten (TiW), titanium nitride (TiN), copper (Cu) etc.
Fig. 7 represents a kind of for 3D-MPROM
rLthe vertical view of resistive film mask plate, and in technological process the relative position of resistive film figure 7x, 7y and high address line graph 20a, 20b, 20e and low address line graph 30a, 30b.Relative to the characteristic dimension 1F of high address line graph, the characteristic dimension of resistive film figure can be larger, is nF (n > 1, best ~ 2).And adjacent resistive film figure (as 7ab, 7bb) can also combine to form a resistive film figure 7y.Therefore, resistive film mask plate is a nF mask plate (n > 1, best ~ 2).Such as, the 3D-MPROM of 20nm node
rLthe resistive film mask plate of 40nm node can be adopted.
Fig. 8 A-Fig. 8 C represents a kind of 3D-MPROM
rLthe technological process of unit 1ea.It comprises the steps: A) form low address line 30a, the then accurate conductive membrane 25 of deposit, and etched and become multiple cylinder 25 (Fig. 8 A); B) deposit medium 27 in complanation layer.Afterwards, deposit resistive film 23 also utilizes the resistive film mask plate in Fig. 7 to carry out Graphic Exchanging, then etches resistive film 23.Notice that resistive film 23 is of a size of nF (n > 1, best ~ 2) (Fig. 8 B); C) deposit high address line film 20e (Fig. 8 C) being etched.This etch step using medium in layer 27 as etching stopping film, to remove partial ohmic film 23.Therefore, in last storage element structure, resistive film 23 and high address line 20e autoregistration (Fig. 4 B).For the personage being familiar with this specialty, the 3D-MPROM in Fig. 4 C and Fig. 4 D
rLunit 1fa, 1ga also can adopt similar step to complete.
According to the above description to technological process, the final form of resistive film 23 is determined by the lap of resistive film figure 7x and high address line graph 20e.This self aligned technological process requires lower to the edge definition of resistive film figure.That is, the 3D-MPROM of 20nm node
rLnot only can adopt the resistive film mask plate (Fig. 7) of 40nm node, and this mask plate can also be a non-high-precision mask plate.Therefore, 3D-MPROM
rLmask plate become instinct to be reduced significantly.Finally, because above-mentioned technological process requires lower, so 3D-MPROM to the alignment precision between high address line and resistive film
rLphotoetching process cost also relatively low.
3D-MPROM
rLcan combine with knot shape type N system 3D-MPROM (see Chinese patent application 200610100860.8), the shape namely by changing resistive film realizes more kinds of states.Correspondingly, the present invention also proposes a kind of 3D-MPROM (3D-MPROM containing partial ohmic film
bwith partialresistive layer, referred to as 3D-MPROM
pRL).Fig. 9 A-Fig. 9 C describes three kinds of 3D-MPROM
pRLunit.
As shown in Figure 9 A, 3D-MPROM
pRLunit 1ha contains high address line 20h, ROM film 3h and low address line 30a.Wherein, ROM film 3h contains block media film 29, partial ohmic film 23 ' and accurate conductive membrane 25.Block media film 29 and partial ohmic film 23 ' are positioned at above accurate conductive membrane 25.High address line 20h passage sub-resistance film 23 ' only with accurate conductive membrane 25 partial coupling.Due to partial ohmic film 23 ' and the resistive film 23 in Fig. 4 B, to have difformity-partial ohmic film 23 ' ratio resistance film 23 little, and therefore the resistance of storage element 1ha is larger than the resistance of storage element 1ea in Fig. 4 B.Particularly, the contact area 21 between partial ohmic film 23 ' and accurate conductive membrane 25 is less than the sectional area of accurate conductive membrane 25, and the sectional area of contact area in Fig. 4 B between resistive film 23 and accurate conductive membrane 25 and accurate conductive membrane 25 is close.By changing the width f of surface of contact 21, different resistance can be caused, thus form more kinds of states.Because f is determined by resistive film figure, therefore a resistive film mask plate just can by multidigit Data Enter to each storage element.Similarly, at I
ttime, the resistance of partial ohmic film 23 ' preferably close to or be greater than the resistance of primitive 1za.Clearly, the various invention spirit in Chinese patent application 200610100860.8 all can be applied to 3D-MPROM
pRL.
Fig. 9 B and Fig. 9 C describes other two kinds of 3D-MPROM
pRLunit 1ia, 1ja.They are similar to 3D-MPROM in Fig. 9 A
pRLunit 1ha.Unique difference is the position of its partial ohmic film 23 ': partial ohmic film 23 ' is arranged in accurate conductive membrane 25 in figures 9 b and 9; In Fig. 9 C, partial ohmic film 23 ' is positioned at accurate conductive membrane 25 times.Similarly, by changing the numerical value of f, different resistance can be caused, thus form more kinds of states.Like this, a resistive film mask plate just can by multidigit Data Enter to each storage element.
The 3D-MPROM of resistive element is contained at one
b(3D-MPROM
rE) in, 3D-MPROM
rEthe accurate conductive membrane of unit contains higher resistive element concentration than the accurate conductive membrane of primitive.Figure 10-Figure 12 B describes multiple 3D-MPROM
rE.As shown in Figure 10,3D-MPROM
rEunit 1ka contains high address line 20k, ROM film 3k and low address line 30a.Wherein, ROM film 3k contains accurate conductive membrane 25 '.Compare with the primitive 1za on its left side, 3D-MPROM
rEthe accurate conductive membrane 25 ' of unit 1ka has similar structures with the accurate conductive membrane 25 of primitive 1za, is namely p-i-n diode.But accurate conductive membrane 25 ' contains higher resistive element concentration than accurate conductive membrane 25.With after in primitive 1za, the semiconductor material (as silicon) of accurate conductive membrane 25 (as p-i-n diode) combines, resistive element (as oxygen, nitrogen, carbon etc.) can increase the resistivity of this semiconductor material, and the concentration increase of resistive element causes resistivity to increase.These are different from doped chemical (as boron, phosphorus, arsenic) conventional in semiconductor material: these doped chemicals reduce the resistivity of semiconductor, and the concentration increase of doped chemical causes resistivity to reduce.
Figure 11 compares silicon diode (i.e. primitive), SiO
x(x < 2) diode (i.e. 3D-MPROM
rEunit) and SiO
2the V.A. curve of film.They represent with 440,441 and 442 respectively.Clearly, SiO
xthe V.A. curve 441 of (x < 2) diode should be positioned at silicon diode V.A. curve 440 and SiO
2between film V.A. curve 442.This is because SiO
2siO
xa kind of extreme case of (x < 2): work as SiO
xin (x < 2) the content height of oxygen to a certain extent time, SiO
xjust become SiO
2.Therefore, SiO
xthe V of (x < 2) diode
tshould between the V of silicon diode
t0and SiO
2the V of film
txbetween, i.e. V
t0< V
t< V
tx.Due to V
txnumerical value is very big, 3D-MPROM
rEthe V of unit
tcan regulate in tremendous range.Similar with oxygen, nitrogen also can regulate 3D-MPROM in tremendous range
rEthe V of unit
t.In addition, carbon also can be used for regulating V
t.This is because carbon can form SiC with silicon
z(z < 1).SiC
zas a kind of semiconductor material, its band gap (bandgap) is wider than silicon.In general, in diode, the band gap of semiconductor material is wider, the V of this diode
thigher.
Figure 12 A and Figure 12 B represents 3D-MPROM
rEa kind of technological process of unit 1ka.First low address line 30a and accurate conductive membrane 25 is formed.Then in photoresist 28, opening 28o is formed by a resistive element mask plate.Resistive element mask plate and resistive film mask plate similar, be all nF mask plate (n > 1, best ~ 2).Here, the width of opening 28o is nF (n > 1, best ~ 2), larger than the width (~ F) of high address line 20k.Then in accurate conductive membrane 25, resistive element (as oxygen, nitrogen, carbon etc.) (Figure 12 A) is injected by ion implantation.This ion implantation step can increase the concentration of resistive element under opening 28o.Afterwards, remove photoresist 28 and accurate conductive membrane 25 is etched into cylinder 25 ' (Figure 12 B).Remaining step and primitive 1za similar (see Fig. 8 B and Fig. 8 C).With 3D-MPROM
rLsimilar, the 3D-MPROM of 20nm node
rEnot only can adopt the resistive element mask plate of 40nm node, and this mask plate can also be a non-high-precision mask plate.In sum, 3D-MPROM
bdata Enter cost more than most people imagine low.
3D-MPROM
rL(Fig. 4 B-Fig. 4 D, Fig. 9 A-Fig. 9 C), 3D-MPROM
rE(Figure 10) can combine with knot shape type N system 3D-MPROM, junction characteristic type N system 3D-MPROM (see Chinese patent application 200610100860.8), improve the quantity of information that each storage element stores further.Figure 13 A-Figure 14 B describes multiple 2 bit 3D-MPROM
b(b=2, N=4); Figure 15 A and Figure 15 B describes a kind of 4 bit 3D-MPROM
b(b=4, N=16).
Figure 13 A-Figure 13 C describes three kind of 2 bit 3D-MPROM
b.As shown in FIG. 13A, this embodiment combines the 3D-MPROM in Fig. 4 B
rLwith the 3D-MPROM in Figure 10
rE.These four storage elements 1za, 1ma, 1na, 1oa represent four kinds of states.Primitive 1za is not containing any resistive film or resistive element.The accurate conductive membrane 25 ' of storage element 1ma is at least containing a kind of resistive element.Storage element 1na contains one deck resistive film 23 in accurate conductive membrane 25.Storage element 1oa contains resistive element and resistive film.In addition, storage element 1ma can have different doping contents from primitive 1za.Clearly, this embodiment only needs 2 mask plates (i.e. resistive film mask plate and resistive element mask plate) just can by 2 Data Enters to each storage element.
Figure 13 B represents the second 2 bit 3D-MPROM
b.It has employed 3D-MPROM in Fig. 4 B
rLtwo kinds of embodiments.These four storage elements 1za, 1pa, 1qa, 1ra represent four kinds of states.Such as, the resistive film 23a of storage element 1pa contains the non-setting silicon of 15nm, and the resistive film 23b of storage element 1qa contains the non-setting silicon of 30nm, and storage element 1ra contains resistive film 23a and 23b, i.e. the non-setting silicon of 45nm.And for example, the resistive film 23a of storage element 1pa contains 3nm silicon nitride, and the resistive film 23b of storage element 1qa contains 6nm silicon nitride, and storage element 1ra is then containing 9nm nitrogenize shape silicon.Similarly, this embodiment only needs 2 resistive film mask plates just can by 2 Data Enters to each storage element.
Figure 13 C represents the third 2 bit 3D-MPROM
b.It combines 3D-MPROM in Fig. 4 B and Fig. 4 D
rLtwo kinds of embodiments.These four storage elements 1za, 1sa, 1ta, 1ua represent four kinds of states.The resistive film 23c of storage element 1sa is positioned at above accurate conductive membrane 25, and the resistive film 23d of storage element 1ta is positioned at below accurate conductive membrane 25, and storage element 1ua contains two-layer resistive film 23c and 23d, and they lay respectively at above and below accurate conductive membrane 25.Also only needs 2 resistive film mask plates just can by 2 Data Enters to each storage element for this embodiment.
To 3D-MPROM
bwhen carrying out read operation, need to provide a series of progressively increase read voltage signal.Once read voltage greatly to producing read current in a storage element, then produce an output signal, voltage of reading at this moment corresponds to state residing for this storage element.Figure 14 A and Figure 14 B describes a kind of 2 bit 3D-MPROM
breading circuit and read operation.
As shown in Figure 14 A, this 2 bit 3D-MPROM
bcomprise two parts: memory heap 0 and peripheral circuit 0K.Memory heap 0 comprises data group 30DT (comprising data element 1ca-1cz, data bit line 30a-30z) and dummy argument group 32DY (comprising dummy argument 1c0-1c3, umbral position line 32a-32d).Data element stores data, and dummy argument provides reference signal for read operation.Data element and dummy argument all have 4 kinds of states ' 0 '-' 3 '.Such as, data element 1ca and dummy argument 1c1 is in state ' 1 '.The state residing for numeral storage element in this figure bracket.In this embodiment, the dummy argument and the data element that are in equal state have identical structure and adopt same material.Such dummy argument can not cause extra production cost, therefore can reduce 3D-MPROM
bcost.
Peripheral circuit 0K is formed in substrate 0s, and is coupled with memory heap 0 by contact channels hole.It contains word line voltage and produces circuit 50, line decoder 52, column decoder 54, reference signal generation circuit 56, sensor amplifier 58, data buffer 60 and N system-binary translator 62 etc.Word line voltage produces circuit 50 and produces at different read phase and different read voltage.This is read voltage according to row address 52A and delivers to corresponding wordline (as 20c) by line decoder 52.Corresponding bit line is inputted 51 with first of sensor amplifier 58 according to column address 54A and is coupled by column decoder 54.Reference signal generation circuit 56 produces reference voltage 53 for sensor amplifier 58.It contains multiple Switch Controller (as 56a '), and each Switch Controller contains the transistor that a pair is shared gate signal (as 56a).
The sequential chart of wordline and bit-line voltage when Figure 14 B represents a kind of read operation.Each read operation needs containing N-1 read phase.This embodiment contains 3 read phase: T0-T2.At each read phase, the wordline chosen (as 20c) adds and reads voltage accordingly.According to the state residing for storage element (1ca-1cz, 1c0-1c3), different storage element flows through different read currents, and on the bit line be coupled with it like this, the voltage of (30a-30z, 32a-32d) also rises with different rates.At the end of each read phase is fast, the voltage in data group 30DT on all data bit lines (30a-30z) is read one by one.If bit line (as 30a) voltage is greater than trigger voltage V
x, then export 55 and uprise.Meanwhile, respective bit line (30a) is set to high voltage V by sensor amplifier 58 in residue read operation
h, the diode read in voltage damage respective stored unit (1ca) remained in read operation can be avoided like this.Below introduce the details of each read phase:
A) in the first read phase T0, wordline 20c adds first and reads voltage V
r0.At this moment, bit line (30a-30z, 32a-32d) voltage rises with different rates according to storage element state.For state ' 0 ' (as storage element 1ca, 1c0), read voltage V
r0produce a large read current, therefore bit line (30a, 32a) voltage rise is very fast; For state ' 1 ' (as storage element 1cz, 1c1), read voltage V
r0produce little read current, therefore bit line (30z, 32b) voltage rise is very slow; ....Meanwhile, in reference signal generation circuit 56, only gate signal 56a is set high, and Switch Controller 56a ' closes, and such umbral position line 32a, 32b are coupled.Therefore, reference voltage 53 is the average of state ' 0 ' and state ' 1 ' bit-line voltage.At the end of T0 is fast, the voltage on data bit lines (30a-30z) all in data group 30DT compares with reference voltage 53 by sensor amplifier 58 one by one, exports 55 and is sent to data buffer 60.
B) in the second read phase T1, wordline 20c adds second and reads voltage V
r1.For state ' 0 ' (as storage element 1ca, 1c0), bit line (30a, 32a) is set to V when T0
h; For state ' 1 ' (as storage element 1cz, 1c1), read voltage V
r1produce a large read current, therefore bit line (30z, 32b) voltage rise is very fast; For state ' 2 ' (as storage element 1cb, 1c2), read voltage V
r1produce little read current, therefore bit line (30b, 32c) voltage rise is very slow; ....Meanwhile, in reference signal generation circuit 56, only gate signal 56b is set high, and Switch Controller 56b ' closes, and such umbral position line 32b, 32c are coupled.Therefore, reference voltage 53 is the average of state ' 1 ' and state ' 2 ' bit-line voltage.At the end of T1 is fast, the voltage in data group 30DT on all data bit lines (30a-30z) is read one by one, exports 55 and is sent to data buffer 60.
C) in third reading stage T2, wordline 20c adds third reading voltage V
r2.For state ' 0 ' and ' 1 ' (as storage element 1ca, 1c0; 1cz, 1c1), bit line (30a, 32a; 30z, 32b) be set to V when T0 and T1
h; For state ' 2 ' (as storage element 1cb, 1c2), read voltage V
r2produce a large read current, therefore bit line (30b, 32c) voltage rise is very fast; ....Meanwhile, in reference signal generation circuit 56, only gate signal 56c is set high, and Switch Controller 56c ' closes, and such umbral position line 32c, 32d are coupled.Therefore, reference voltage 53 is the average of state ' 2 ' and state ' 3 ' bit-line voltage.At the end of T2 is fast, the voltage in data group 30DT on all data bit lines (30a-30z) is read one by one, exports 55 and is sent to data buffer 60.
D) at the end of read operation, the data be stored in data buffer 60 are converted to binary data by N system-2 system converter 62.Like this, 4 binary data be stored in storage element 1ca-1cz are read out.
Figure 15 A and Figure 15 B describes a kind of 4 bit 3D-MPROM
b.Form in Figure 15 A lists the setting of its 16 kinds of states; Figure 15 B is its sectional drawing.For the personage being familiar with this specialty, the reading circuit in Figure 14 A and Figure 14 B and read operation can be applied to 4 bit 3D-MPROM
bin.
As shown in fig. 15, in order to realize 4 bits, storage element can change in 4 dimensions: high resistance membrane 23x, middle resistive film 23y, low resistance film 23z and resistive element."Yes" in table represents employing resistive film or resistive element; "No" represents and does not adopt.Because often dimension has two kinds of selections ("Yes" and "No"), this embodiment has 16 kinds of states.This 4 dimension can be realized by 4 mask plates, i.e. high resistance membrane mask plate, middle resistive film mask plate, low resistance film mask plate and resistive element mask plate.
As shown in fig. 15b, this 4 bit 3D-MPROM
bcontaining a Semiconductor substrate 0s and 3D-MPROM
bheap 0.This Semiconductor substrate 0s contains multiple transistor 0T (comprising grid 0P).These transistors 0T and interconnection layer 0I thereof forms 3D-MPROM together
bthe peripheral circuit 0X of heap 0.3D-MPROM
bheap 0 is stacked on substrate 0s.In this embodiment, it contains 4 accumulation layer 100-400: accumulation layer 100 is containing wordline (80a-80h...), bit line (90d...) and storage element (1ad-1hd...); Accumulation layer 200 stacked with accumulation layer 100 on, and containing wordline (80a-80h...), bit line (90d
*...) and storage element (1ad
*...); Accumulation layer 300 stacked with accumulation layer 200 on, and containing wordline (80a '-80h ' ...), bit line (90d ' ...) and storage element (1a ' d '-1h ' d ' ...); Accumulation layer 400 stacked with accumulation layer 300 on, and containing wordline (80a '-80h ' ...), bit line (90d " ...) and storage element (1a ' d " ...).Accumulation layer (as 100) is coupled with substrate 0s by contact channels hole (as 90dv).
Storage element 1ad-1hd, 1a in accumulation layer 100,300 ' d '-1h ' d ' represents state ' 0 '-' f ' (with reference to figure 15A) respectively.Such as, storage element 1ad represents state ' 0 ', and it is a primitive, namely not containing any resistive film or resistive element; Storage element 1bd represents state ' 1 ', and its diode 25 ' is containing resistive element; Storage element 1cd represents state ' 2 ', and it contains low resistance film 23z; Storage element 1ed represents state ' 4 ', and it contains middle resistive film 23y; Storage element 1a ' d ' represents state ' 8 ', and it contains high resistance membrane 23x; Storage element 1h ' d ' represents state ' f ', and it contains high resistance membrane 23x, middle resistive film 23y, low resistance film 23z and resistive element; ....For easy meter, the storage element details in accumulation layer 200,400 and the contact channels hole of accumulation layer 200-400 do not draw.
Embodiment in Figure 15 B combines the 3D-MPROM of multiple improvement, as mixolimnion 3D-MPROM (see Chinese patent application 200610162698.2) and narrow linewidth 3D-MPROM (see Chinese patent application 200810183936.7).Part accumulation layer (as 100,200) shared address line (80a-80h...) in mixolimnion 3D-MPROM; Other accumulation layer (as 200,300) then not shared address line, and separated by inter-level dielectric film 121.In narrow linewidth 3D-MPROM, the characteristic dimension of accumulation layer address wire is less than the characteristic dimension of substrate crystal tube grid.Further combined with three-dimensional memory module (see Chinese patent application 200710194280.4), one adopts the x8x8x4 3D-MPROM module of 20nm technology can store ~ 1TB information.Here, x8x8x4 refers to that this module contains 8 3D-MPROM
bchip, each 3D-MPROM
bchip contains 8 accumulation layers, and each storage element stores 4 information.
In Figure 13 A-Figure 13 C, 2 mask plates are only needed just by 2 Data Enters to each storage element, can namely to realize 2 bits; In Figure 15 A and Figure 15 B, 4 mask plates are only needed just by 4 Data Enters to each storage element, can namely to realize 4 bits.In fact, at 3D-MPROM
bin, each mask plate can in storage element many typings 1 information.For example, 5 mask plates can realize 5 bits, and 6 mask plates can realize 6 bits ....If adopt 3D-MPROM in Fig. 9 A-Fig. 9 C
pRL, the number of mask plate can also reduce further.This is than in the scale-of-two 3D-MPROM of conventional art, and every many typings 1 information, with regard to the how stacked accumulation layer of needs, saves a lot of production cost.
Although above instructions specifically describes examples more of the present invention, those skilled in the art should understand, not away under the prerequisite of the spirit and scope of the present invention, can change form of the present invention and details, this does not hinder them to apply spirit of the present invention.Therefore, except the spirit according to additional claims, the present invention should not be subject to any restriction.
Claims (8)
1. a multidigit unit three-dimensional masking film program storer, is characterized in that containing:
A Semiconductor substrate containing transistor;
Multiple be stacked in substrate and with the masking film program accumulation layer of Substrate coupling, each accumulation layer contains the multiple masking film program storage elements comprising the first storage element and the second storage element; Each storage element contains accurate conductive membrane, and this accurate conductive membrane good conductivity is in one direction in other direction; Described multiple storage element has N kind state, wherein, and N > 2; Storage element under different conditions has different volt-ampere characteristics;
The threshold voltage of described first storage element is minimum in all states; The threshold voltage of described second storage element is greater than described first storage element; Described second storage element is at least more than described first storage element containing one deck first resistive film.
2. multidigit according to claim 1 unit three-dimensional masking film program storer, is further characterized in that: when the electric current flowing through described second storage element is threshold current, the resistance of described first resistive film close to or be greater than the resistance of described first storage element.
3. multidigit unit according to claim 1 three-dimensional masking film program storer, is further characterized in that: described first resistive film contains at least one deck semiconductor film.
4. multidigit unit according to claim 1 three-dimensional masking film program storer, is further characterized in that: described first resistive film contains at least one layer dielectric.
5. multidigit according to claim 1 unit three-dimensional masking film program storer, is further characterized in that: the thickness of top film in the accurate conductive membrane that described first resistive film thickness is less than described first storage element.
6. multidigit unit according to claim 1 three-dimensional masking film program storer, is further characterized in that:
Containing the 3rd storage element, the threshold voltage of described 3rd storage element is greater than described first storage element, and described 3rd storage element is at least more than described first storage element containing one deck second resistive film;
Described first and second resistive films have difformity.
7. multidigit unit according to claim 1 three-dimensional masking film program storer, is further characterized in that:
Containing the 3rd storage element, the threshold voltage of described 3rd storage element is greater than described first storage element, and described 3rd storage element is at least more than described first storage element containing one deck second resistive film;
Containing the 4th storage element, the threshold voltage of described 4th storage element is greater than described second and the 3rd storage element, and described 4th storage element contains described first and second resistive films.
8. multidigit unit according to claim 1 three-dimensional masking film program storer, be further characterized in that: containing the 3rd storage element, the accurate conductive membrane of described 3rd storage element contains higher resistive element concentration than the accurate conductive membrane of described first storage element.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050524.1A CN103794611B (en) | 2010-05-24 | 2010-05-24 | Many bits three-dimensional masking film program memorizer |
| CN201010194950.4A CN102262904B (en) | 2010-05-24 | 2010-05-24 | Large bit-per-cell three-dimensional mask-programmable memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010194950.4A CN102262904B (en) | 2010-05-24 | 2010-05-24 | Large bit-per-cell three-dimensional mask-programmable memory |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410050524.1A Division CN103794611B (en) | 2010-05-24 | 2010-05-24 | Many bits three-dimensional masking film program memorizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102262904A CN102262904A (en) | 2011-11-30 |
| CN102262904B true CN102262904B (en) | 2014-12-24 |
Family
ID=45009510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010194950.4A Expired - Fee Related CN102262904B (en) | 2010-05-24 | 2010-05-24 | Large bit-per-cell three-dimensional mask-programmable memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102262904B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107978336B (en) * | 2016-10-24 | 2020-04-10 | 杭州海存信息技术有限公司 | Multi-bit three-dimensional offset printing memory |
| US9001555B2 (en) * | 2012-03-30 | 2015-04-07 | Chengdu Haicun Ip Technology Llc | Small-grain three-dimensional memory |
| KR20150043759A (en) * | 2013-10-15 | 2015-04-23 | 에스케이하이닉스 주식회사 | Resistance variable memory apparatus and manufacturing method thereof |
| CN109119121A (en) * | 2016-04-14 | 2019-01-01 | 厦门海存艾匹科技有限公司 | The three-dimensional one-time programming memory of double offset |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1099695C (en) * | 1998-09-24 | 2003-01-22 | 张国飙 | Three-dimensional read-only memory |
| CN1412850A (en) * | 2001-10-07 | 2003-04-23 | 张国飙 | Three-D integrated memory |
| CN1485925A (en) * | 1998-09-24 | 2004-03-31 | 张国飙 | Read-only memory element of three-dimensional storage |
| CN1897161A (en) * | 2005-07-15 | 2007-01-17 | 张国飙 | N-ary mask-programmable memory |
| CN101110269A (en) * | 2002-11-17 | 2008-01-23 | 张国飙 | Improved three-dimensional read-only memory |
-
2010
- 2010-05-24 CN CN201010194950.4A patent/CN102262904B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1099695C (en) * | 1998-09-24 | 2003-01-22 | 张国飙 | Three-dimensional read-only memory |
| CN1485925A (en) * | 1998-09-24 | 2004-03-31 | 张国飙 | Read-only memory element of three-dimensional storage |
| CN1412850A (en) * | 2001-10-07 | 2003-04-23 | 张国飙 | Three-D integrated memory |
| CN101110269A (en) * | 2002-11-17 | 2008-01-23 | 张国飙 | Improved three-dimensional read-only memory |
| CN1897161A (en) * | 2005-07-15 | 2007-01-17 | 张国飙 | N-ary mask-programmable memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102262904A (en) | 2011-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11849593B2 (en) | Vertical cross-point arrays for ultra-high-density memory applications | |
| US10529778B2 (en) | Vertical cross-point memory arrays | |
| US8884376B2 (en) | Large bit-per-cell three-dimensional mask-programmable read-only memory | |
| US9246089B2 (en) | Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states | |
| JP5454945B2 (en) | Storage device | |
| JP5237105B2 (en) | Reversible resistivity switching metal oxide or nitride layer with added metal | |
| JP5042233B2 (en) | Deposited semiconductor structure and fabrication method for minimizing n-type dopant diffusion | |
| CN104253130A (en) | Semiconductor device | |
| US20090230376A1 (en) | Resistive memory devices | |
| CN102262904B (en) | Large bit-per-cell three-dimensional mask-programmable memory | |
| EP3688805A1 (en) | Vertical backend transistor with ferroelectric material | |
| TW202029191A (en) | Memory device and method for reading a memory device | |
| US7887999B2 (en) | Method of making a pillar pattern using triple or quadruple exposure | |
| US11948616B2 (en) | Semiconductor structure and manufacturing method thereof | |
| KR20180019220A (en) | Laminated thin film memory | |
| CN103794611A (en) | Multi-bit three-dimensional mask programming storage | |
| CN111668367A (en) | Storage device | |
| US9680092B2 (en) | Current selectors formed using single stack structures | |
| EP4044240A1 (en) | Semiconductor structure, memory cell, and memory array | |
| US6873535B1 (en) | Multiple width and/or thickness write line in MRAM | |
| US20230337419A1 (en) | One-time-programmable memory devices | |
| US20230317798A1 (en) | Antimony-gallium-zinc-oxide materials | |
| US20230301195A1 (en) | Magnetic memory device | |
| US11056535B2 (en) | Non-volatile memory element arrays in a wheatstone bridge arrangement | |
| KR102379706B1 (en) | variable resistance memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: 610041 B-36, 6 Yongfeng Road, Chengdu, Sichuan Patentee after: Zhang Guobiao Address before: 610051 5A-001 box 59, Jianshe Road, Sichuan, Chengdu, China Patentee before: Zhang Guobiao Address after: 610041 B-36, 6 Yongfeng Road, Chengdu, Sichuan Patentee after: Zhang Guobiao Address before: 610051 5A-001 box 59, Jianshe Road, Sichuan, Chengdu, China Patentee before: Zhang Guobiao |
|
| CP02 | Change in the address of a patent holder | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141224 Termination date: 20190524 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |