CN102255618A - Low-overhead transient fault automatic correction circuit for high speed adder - Google Patents
Low-overhead transient fault automatic correction circuit for high speed adder Download PDFInfo
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- CN102255618A CN102255618A CN2010101769465A CN201010176946A CN102255618A CN 102255618 A CN102255618 A CN 102255618A CN 2010101769465 A CN2010101769465 A CN 2010101769465A CN 201010176946 A CN201010176946 A CN 201010176946A CN 102255618 A CN102255618 A CN 102255618A
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Abstract
Transient faults in a combinational logic become a major challenge for the VLSI (very large scale integrated circuit) design. As a typical component in the combinational logic, an adder is widely applied to an arithmetic unit. The invention discloses a low-overhead transient fault automatic correction circuit for a high speed adder. According to the structure, through developing the abundant inherent hardware redundancy and time redundancy existing in the adder circuit, automatic correction on the transient faults in the high speed adder can be realized with lower overhead, thus the fault-tolerant area and performance overheads can be obviously reduced; and through combining a fault correction technology based on a C unit and the inherent hardware redundancy and time redundancy, the transient fault correction capacity of the adder can be further enhanced. The adder provided by the invention has preferably compromised area-delay overhead compared with other structures.
Description
Technical field
The invention belongs to the integrated circuit (IC) design field, be mainly concerned with the transient fault prevention and the recovery field of integrated circuit (IC) chip, refer in particular to the design reinforcement technology of utilizing circuit, the high-speed adder transient fault of realizing low expense is from dynamic(al) correction, thus the structure and the technology of raising circuit reliability.
Background technology
Transient fault in the integrated circuit is mainly caused by various high energy particles.When high energy particle is injected integrated circuit, instantaneous discharging and recharging will be taken place, the electric charge that charges and discharge is absorbed by the sensitizing range, will cause the integrated circuit (IC) logic state to change, and causes run-time error or output error, has had a strong impact on the reliability of integrated circuit.Cause the high energy particle of transient fault, be mainly derived from cosmic radiation environment, nuclear radiation environment and encapsulating material etc.Think in the past because high energy particle energy when getting through the earth's atmosphere weakens rapidly, will can not cause ground integrated circuit generation capability error.But along with the continuous development of manufacturing process, the characteristic size of very lagre scale integrated circuit (VLSIC) is more and more littler, all corresponding reducing such as its gate length, node size, the degree of depth, oxidated layer thickness, and P-N knot critical charge also descends greatly.On the other hand, operating frequency of integrated circuit is more and more higher, and operating voltage is more and more lower.These variations all make integrated circuit that single particle effect has been shown stronger sensitiveness.So more low-energy particle also might influence the normal operation of integrated circuit.Studies show that the inefficacy that transient fault causes is the most important failure cause of integrated circuit.Therefore, not only in space environment, even integrated circuit on the ground also is faced with the threat of high energy particle.The integrated circuit that is applied to military and aerospace field must be considered the transient fault that high energy particle causes, to improve the reliability of system.
There was research to point out that compare with sequence circuit, combinational circuit is lower to the sensitiveness of high energy particle in the past, was difficult for producing transient fault.But because sequential element compound with regular structure such as memory, (Error CorrectionCodes, ECC) etc. method is protected can to use parity check or error correction coding.The combinational circuit complex structure, systematicness is relatively poor, can't application class like method protect.And along with the development of integrated circuit technology, the transient fault in the combinational circuit will be caught up with even surpass memory, become the main cause that causes ic failure, must consider the protection of transient fault.
In the very high application of reliability requirements such as space flight and aviation, generally (Triple ModularRedundancy TMR) reinforces combinational circuit by triplication redundancy.Triplication redundancy copies as three copies with ifq circuit, and output utilizes three to select two voting machines to select to circuit, thereby guarantees result's correctness.Yet triplication redundancy can bring very big area, power consumption and performance cost, and cost is too high for common integrated circuit, can't large-scale application.And duplication redundancy copies as two copies with original circuit, and the output result is compared with the detected transient fault, has reduced fault-tolerant expense.But this method can't be corrected the fault in the circuit automatically, needs to increase extra fault processing mechanism, the complexity of the design that this increases again.
In order to overcome the above problems, the researcher proposes two kinds of technology: copy error correction and time shift error correcting technique.Fig. 1 (a) has represented the structure of copy error correction, it is applied to C unit (its circuit structure as shown in Figure 2) in the duplication redundancy structure, replace the comparison circuit of original two parts copy output, can correct the transient fault in the circuit automatically, but area overhead is still bigger.Fig. 1 (b) has represented the structure of time shift error correction, it does not adopt the duplication redundancy structure, but after the output of circuit, add a delay unit, output after original output and the time-delay enters the C unit simultaneously, also can correct the transient fault in the circuit automatically, compare with the copy error correction, area overhead reduces greatly, but the time-delay of circuit has bigger increase.
Summary of the invention
Though copy error correction and time shift error correcting technique have reduced the expense of triplication redundancy, and solved duplication redundancy can only error detection can't error correction problem, they still exist bigger area overhead or time-delay expense, have limited two kinds of The Application of Technology.There is a large amount of intrinsic redundant resources in combinational circuit inside, comprises hardware redundancy and time redundancy.Yet existing technology is only studied a certain redundancy separately, and these two kinds of resources of the abundant development and utilization of technology are seldom arranged.Be used for fault-tolerantly if can fully develop these hardware redundancies and time redundancy resource, can reduce the area and the time-delay expense of copy error correction and time shift error correcting technique greatly, make the utilization of resources more efficient, with the highly reliable circuit of very little cost design.
Adder is a kind of typical element of combinational logic circuit, is widely used in the various arithmetic elements of integrated circuit.The reliability of adder has significant effects to the reliability of entire chip.The present invention is based on above thought, proposed a kind of high-speed adder transient fault automatic calibration circuit of low expense, the major technology point comprises following several aspect:
1. hardware redundancy resource intrinsic in the exploitation adder is used for error correction, has reduced fault-tolerant area overhead;
2. intrinsic time redundancy resource is used for error correction and area reduction in the exploitation adder, has not only reduced fault-tolerant time-delay expense, has also reduced the area of circuit to a certain extent;
3. will combine with intrinsic hardware of exploitation and time redundancy based on the error correction techniques of C unit, strengthen the fault-tolerant ability of adder, make it to correct voluntarily transient fault wherein.
High-speed adder transient fault correcting circuit disclosed by the invention is paid close attention to the ability that reduces fault-tolerant expense and improve error correction.Technical advantage of the present invention is:
1. can realize the protection of transient fault with less area and time-delay expense, only need very little cost, and can keep the performance advantage of high-speed adder;
2. fully develop hardware and time redundancy resource intrinsic in the adder, improved the level of resources utilization, reduced the unnecessary wasting of resources;
3. can realize stronger fault-tolerant ability to the transient fault in the circuit from dynamic(al) correction, strengthen the reliability of adder greatly.
Technology proposed by the invention can expand in other combinational circuit structure.Along with the fast development of technology, the transient fault problem of combinational circuit becomes more and more serious, and intrinsic redundant resource improves its reliability in the exploitation combinational circuit, and required expense is less, has great importance and practical value.
Description of drawings
Error correction of Fig. 1 copy and time shift error correction structure;
Fig. 2 C element circuit structure;
Fig. 3 high-speed adder general structure disclosed by the invention;
Fig. 4 high-speed adder transient fault disclosed by the invention correcting circuit group carry G/P produces part;
Fig. 5 high-speed adder transient fault disclosed by the invention correcting circuit carry tree part;
Fig. 6 tradition is based on the critical path and the non-critical path signal of sparse tree high-speed adder;
Fig. 7 high-speed adder transient fault disclosed by the invention correcting circuit critical path and non-critical path part;
The area of Fig. 8 the present invention and other structure, time-delay and area-delay product are relatively.
Embodiment
Below in conjunction with accompanying drawing, describe the structure and the course of work of the high-speed adder transient fault automatic calibration circuit of low expense disclosed by the invention in detail.
The high-speed adder transient fault automatic calibration circuit of low expense disclosed by the invention is made of three parts, as shown in Figure 3, is respectively group carry G/P and produces part, carry tree part and part and produce and select part.In order clearly to set forth, below be the example explanation with 64 adders.In fact, structure of the present invention is applicable to the adder of any bit wide.
Group carry G/P produces the G/P group carry signal that part produces 4 group.Be input as 4 A
I+3～A
iAnd B
I+3～B
i, through three grades of logics, the output group carry produces signal G
I+3, iWith group carry transmitting signal P
I+3, i, as shown in Figure 4.4 of the superiors Filled Rectangles are expressed as follows operation respectively from right-to-left among the figure:
2 solid circles in intermediate layer are expressed as follows operation respectively from right-to-left:
G
i+1，i＝G
i+1+P
i+1·G
i，P
i+1，i＝P
i+1·P
i [Equ.5]
G
i+3，i+2＝G
i+3+P
i+3·G
i+2，P
i+3，i+2＝P
i+3·P
i+2 [Equ.6]
Undermost 1 solid circles is expressed as follows operation:
G
i+3，i＝G
i+3，i+2+P
i+3，i+2·G
i+1，i，P
i+3，i＝P
i+3，i+2·P
i+1，i [Equ.7]
In 64 adders, have the group carry G/P generation module in 16 picture groups 4.In order to strengthen the reliability that group carry G/P produces part, each module is all duplicated portion, and two copies use identical input, and the unlike signal of sparse carry tree is linked in output.
The sparse carry tree part is made up of the one-level carry node of sparse carry node permutation, increase and one group of last C unit, as shown in Figure 5.The sparse carry node array is the part in the blue frame in the drawings, the carry node array of Kogge-Stone (KS) adder of they and a N/4 position is similar, for 64 adders, is made up of 16 row altogether, totally 4 grades of every row, each solid circles node is realized following function:
G
i+1，i＝G
i+1+P
i+1·G
i，P
i+1，i＝P
i+1·P
i [Equ.8]
The following function of hollow circular realization in the sparse carry node array:
G
i+1，i＝G
i+1+P
i+1·G
i [Equ.9]
In the sparse carry node array, the node of black and line are used to calculate 4i+3 (i=0,2,4 ..., 14) position carry, and red node and line are used to calculate 4i+3 (i=1,3,5 ... 15) Wei carry, there is not signal to connect between black and red two parts, separate, be independent of each other.Like this, black and red two parts form natural hardware resource redundancy, and it is fault-tolerant that we utilize this intrinsic redundancy properties to be used for, and can improve resource utilization greatly.
In order to develop redundancy, behind the sparse carry node array, increase one-level carry node, thereby make every 4i+3 (i=0,1,2 ..., 15) and the carry signal of position all calculated by black and red two parts.Two groups of outputs that group carry G/P produces part link to each other with danger signal with black respectively.The adder carry tree forms two independently copies like this.
Behind the one-level carry node that increases, we increase one-level C unit.Like this, the similar of adder carry tree and copy error correction can correct any transient fault that wherein occurs automatically.Different with the copy error correction is that we do not need to increase a large amount of hardware spendings, but realize duplicating of hardware by developing intrinsic hardware redundancy, greatly reduce fault-tolerant area overhead.
Fig. 6 has represented the critical path and the non-critical path of traditional sparse tree adder, wherein non-critical path is part and produces and the structure of selecting part, it by two groups 4 cascaded carry adder (Ripple Carry Adder, RCA) and one group 4 MUX (MUX) form.Two groups 4 carry propagate adder produces carry respectively and is the part of " 0 " and psum0 and carry part and the psum1 for " 1 ", psum0 and psum1 are connected to MUX, select by the carry signal that critical path obtains, finally obtain adder and.Because the time-delay on the non-critical path much smaller than the time-delay of critical path, therefore exists be not fully utilized more slack time.Be the intrinsic time redundant resource in the adder this part slack time.The present invention is by transforming non-critical path, fully develops intrinsic time redundancy resource and carries out fault-tolerantly, and utilizes time redundancy to reduce area, greatly reduces fault-tolerant time overhead, reduced area of chip simultaneously.
Part that the present invention proposes and generation and selection part are as shown in Figure 7.We only use a carry to be the 4 Bits Serial add with carry musical instruments used in a Buddhist or Taoist mass of " 0 " on non-critical path, connect one group of delay unit τ in the output of 4 adders.The original output of 4 adders and the output of delaying time through the τ unit are connected in one group of C unit, and this forms the structure of a similar time shift error correction.Different with the time shift error correction is that owing to be in non-critical path, we have utilized the time redundancy in the adder to construct the time shift error correction, can not increase time-delay, promptly can not cause any loss to the performance of adder.
The output of C unit is psum0, after the C unit, connects a RIC module that has proposed again, thereby produces psum1.Psum0 and psum1 insert MUX and select to export final result.Here we come the development time redundancy by using the RIC structure, reduce by one 4 bit-serial adder, in order to exchange the reduction of area for.Therefore, the intrinsic time redundant resource in the non-critical path is fully utilized, and has not only increased the ability of the automatic error correction of adder, and has reduced the use of device, thereby reduces area.
(Area DelayProduct, ADP) three aspects compare, as shown in Figure 8 in area, time-delay and area-delay product for the adder structure that we propose the present invention and other adder.Relatively the standard K S adder with no error correcting capability is reference, participates in triplication redundancy adder (TMR+RIC), copy error correction adder (ECD) and time shift error correction adder (ECTO) that reliable adder relatively has triplication redundancy adder (TMR), has the RIC structure.Can see that from the result area of triplication redundancy adder is about more than 300% of standard K S adder, so area-delay product is up to 3.96; Triplication redundancy adder with RIC structure makes area reduce to a certain extent by increasing less time-delay, so area-delay product decreases than triplication redundancy adder; Copy error correction adder is owing to only use duplication redundancy, area to be about about 250% of standard K S adder, so area-delay product is reduced to 2.39; Time shift error correction adder has maximum time-delay, and is very little but its area overhead but is reduced to, so area-delay product is corresponding less, is about 1.96; And the adder that the present invention proposes has been owing to fully developed hardware redundancy and the time redundancy in the adder, so area and time-delay all reduce greatly, is about 112% and 106% of standard K S adder respectively.Reducing significantly of area and time-delay makes structure of the present invention have minimum area-delay product, is about 1.19.
In sum, in view of reliable adder area overhead and the time-delay expense bigger problem of transient fault from dynamic(al) correction, the invention discloses a kind of high-speed adder transient fault automatic calibration circuit of low expense, by naturally occurring hardware redundancy and time redundancy resource in the abundant exploitation adder, thereby reduce area and the time-delay expense of high-speed adder transient fault significantly from dynamic(al) correction.The technology that is proposed can expand in other combinational circuit structure.Along with the fast development of technology, the transient fault problem of combinational circuit becomes more and more serious, and intrinsic redundant resource improves its reliability in the exploitation combinational circuit, and required expense is less, has certain practical value.
Claims (1)
1. the high-speed adder transient fault automatic calibration circuit of a low expense is characterized in that:
By with the intrinsic hardware redundancy in the parallel adder critical path carry tree with have the C unit combination of transient fault calibration capability, can with lower area overhead realize transient fault in the critical path circuit from dynamic(al) correction; By adopting the sparse tree structure to combine with the exploitation of intrinsic hardware redundancy, greatly reduce the line complexity, further reduce area, improve performance simultaneously; By the C unit combination of the intrinsic time in the parallel adder non-critical path is redundant and recoverable transient fault, can with transient fault in the lower time-delay expense realization non-critical path circuit from dynamic(al) correction; By with the input of reverse carry (InvertedCarry-In, RIC) technology combines with the exploitation of intrinsic time redundancy, exchanges hardware consumption the slack time of available non-critical path for, further reduces the adder area; Concrete circuit form comprises carry tree and the part on the non-critical path on group carry (G/P) generation, the critical path and produces and select three parts; Group carry (G/P) generating unit branch comprises two groups of independently group carry (G/P) generation modules, in order to form the copy structure; The sparse tree part of carry tree is identical with the Kogge-Stone carry tree of one (N/4) position, needs to increase the one-level carry logic after the sparse carry tree, in order to the odd even carry signal is produced independently two group carry signals; Connect one group of C unit after the one-level carry logic that increases, form copy error correction structure; Part and generation are used one group of 4 Bits Serial add with carry musical instruments used in a Buddhist or Taoist mass with selecting part, and input (Cin) is " 0 "; Connect one group of C unit behind the 4 Bits Serial add with carry musical instruments used in a Buddhist or Taoist mass, two inputs of C unit are respectively the output of 4 Bits Serial add with carry musical instruments used in a Buddhist or Taoist mass and through the 4 Bits Serial add with carry musical instruments used in a Buddhist or Taoist mass output after the time-delay of τ unit, form time shift error correction structure; Adopt the RIC structure to produce two outputs (Psum0 and Psum1) after the C unit, select through a MUX (MUX) at last, get adder output result to the end.
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| CN 201010176946 CN102255618B (en) | 2010-05-20 | 2010-05-20 | Low-overhead transient fault automatic correction circuit for high speed adder |
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| CN102255618B CN102255618B (en) | 2013-07-31 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108832990A (en) * | 2018-06-08 | 2018-11-16 | 上海微小卫星工程中心 | A kind of space single particle effect instant recovery method for real time communication device |
| CN108958703A (en) * | 2017-05-18 | 2018-12-07 | 龙芯中科技术有限公司 | adder |
| CN111798917A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | Data processing method and device for dynamic test result of single event effect of memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85103579A (en) * | 1985-05-08 | 1986-11-05 | 索尼公司 | The interpretation method of error correcting code and system |
| US5812601A (en) * | 1996-11-15 | 1998-09-22 | Telefonaktiebolaget Lm Ericsson | Coding for higher-level modulation |
-
2010
- 2010-05-20 CN CN 201010176946 patent/CN102255618B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85103579A (en) * | 1985-05-08 | 1986-11-05 | 索尼公司 | The interpretation method of error correcting code and system |
| US5812601A (en) * | 1996-11-15 | 1998-09-22 | Telefonaktiebolaget Lm Ericsson | Coding for higher-level modulation |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108958703A (en) * | 2017-05-18 | 2018-12-07 | 龙芯中科技术有限公司 | adder |
| CN108958703B (en) * | 2017-05-18 | 2020-11-06 | 龙芯中科技术有限公司 | Adder |
| CN108832990A (en) * | 2018-06-08 | 2018-11-16 | 上海微小卫星工程中心 | A kind of space single particle effect instant recovery method for real time communication device |
| CN111798917A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | Data processing method and device for dynamic test result of single event effect of memory |
| CN111798917B (en) * | 2020-06-30 | 2021-07-30 | 湘潭大学 | Data processing method and device for dynamic test result of single event effect of memory |
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