CN102255618A - Low-overhead transient fault automatic correction circuit for high speed adder - Google Patents

Abstract

Transient faults in combinational logic become an important challenge in VLSI circuit design. As a typical component of combinational logic, adders are widely used in arithmetic units. The invention discloses a low-overhead high-speed adder transient fault automatic correction circuit. This structure realizes the automatic correction of transient faults in high-speed adders with low overhead by exploiting the inherent hardware redundancy and time redundancy that exist in a large number of adder circuits, which significantly reduces the area and performance overhead of fault tolerance; The fault correction technology of the C unit, combined with the inherent hardware redundancy and time redundancy, further enhances the transient fault correction capability of the adder. The proposed adder has a better area-delay overhead tradeoff than other structures.

Description

A Low Overhead High Speed Adder Transient Fault Automatic Correction Circuit

technical field

The invention belongs to the field of integrated circuit design, mainly relates to the field of transient fault prevention and recovery of integrated circuit chips, in particular refers to the use of circuit design reinforcement technology to realize automatic correction of transient faults of high-speed adders with low overhead, thereby improving circuit reliability structure and technology.

Background technique

Transient faults in integrated circuits are mainly caused by various high-energy particles. When high-energy particles are injected into the integrated circuit, instantaneous charge and discharge will occur, and the charged and discharged charge will be absorbed by the sensitive area, which will cause the logic state of the integrated circuit to change, cause operation errors or output errors, and seriously affect the reliability of the integrated circuit. The high-energy particles that cause transient faults mainly come from the cosmic radiation environment, nuclear radiation environment and packaging materials. It was thought in the past that high-energy particles would not cause malfunctions in integrated circuits on the ground because of the rapid loss of energy as they travel through the atmosphere. However, with the continuous development of the manufacturing process, the feature size of VLSI is getting smaller and smaller, and its gate length, node size, depth, oxide layer thickness, etc. are all reduced accordingly, and the critical charge of the P-N junction is also greatly reduced. On the other hand, the operating frequency of integrated circuits is getting higher and higher, and the operating voltage is getting lower and lower. These changes have made integrated circuits more sensitive to single event effects. So lower energy particles may also affect the normal operation of integrated circuits. Studies have shown that failures caused by transient faults are the most important cause of failure in integrated circuits. Therefore, not only in the space environment, but even integrated circuits on the ground are also facing the threat of high-energy particles. Integrated circuits used in military and aerospace fields must consider transient faults caused by high-energy particles to improve system reliability.

Previous studies have pointed out that compared with sequential circuits, combinational circuits are less sensitive to high-energy particles and less prone to transient failures. However, due to the regular structure of sequential components such as memories, methods such as parity check or error correction codes (Error Correction Codes, ECC) can be used for protection. Combination circuits are complex in structure and poor in regularity, so similar methods cannot be applied for protection. Moreover, with the development of integrated circuit technology, the transient fault in the combined circuit will catch up with or even surpass the memory, and become the main reason for the failure of the integrated circuit, so the protection of the transient fault must be considered.

In applications with high reliability requirements such as aerospace, combined circuits are generally reinforced by Triple Modular Redundancy (TMR). Triple-mode redundancy copies the original circuit into three copies, and selects the output of the circuit with two-out-of-three voters to ensure the correctness of the results. However, triple-mode redundancy will bring a large area, power consumption and performance overhead, and the cost is too high for ordinary integrated circuits to be used on a large scale. The dual-mode redundancy copies the original circuit into two copies, and compares the output results to detect transient faults, reducing the cost of fault tolerance. However, this method cannot automatically correct faults in the circuit, and an additional error handling mechanism needs to be added, which increases the complexity of the design.

In order to solve the above problems, the researchers proposed two technologies: replica error correction and time-shift error correction technology. Figure 1(a) shows the structure of the copy error correction, which applies the C unit (its circuit structure shown in Figure 2) to the dual-mode redundant structure, replacing the comparison circuit output by the original two parts of the copy, which can automatically correct the circuit transient faults in , but the area overhead is still large. Figure 1(b) shows the structure of time-shift error correction. It does not adopt the dual-mode redundant structure, but adds a delay unit after the output of the circuit. The original output and the delayed output enter the C unit at the same time. Transient faults in the circuit can be automatically corrected. Compared with replica error correction, the area overhead is greatly reduced, but the delay of the circuit will be greatly increased.

Contents of the invention

Although copy error correction and time-shift error correction technologies reduce the overhead of triple-mode redundancy and solve the problem that dual-mode redundancy can only detect errors but not correct them, they still have large area overhead or delay overhead. The application of both techniques is limited. There are a large number of inherently redundant resources in combinational circuits, including hardware redundancy and time redundancy. However, existing technologies only study a certain kind of redundancy, and few technologies fully develop and utilize these two resources. If these hardware redundancy and time redundancy resources can be fully developed for fault tolerance, the area and delay overhead of replica error correction and time-shift error correction technology can be greatly reduced, making resource utilization more efficient, and designing high reliable circuit.

An adder is one of the most typical components of a combinational logic circuit and is widely used in various arithmetic units of integrated circuits. The reliability of the adder has an important influence on the reliability of the whole chip. Based on the above ideas, the present invention proposes a low-overhead high-speed adder transient fault automatic correction circuit, and the main technical points include the following aspects:

1. Develop the inherent hardware redundancy resources in the adder for error correction, reducing the area overhead of fault tolerance;

2. Develop the inherent time redundancy resources in the adder for error correction and area reduction, which not only reduces the delay overhead of fault tolerance, but also reduces the circuit area to a certain extent;

3. Combining C-unit-based error correction techniques with developing inherent hardware and time redundancy to enhance the fault tolerance of the adder so that it can self-correct transient faults in it.

The high-speed adder transient fault correction circuit disclosed by the invention focuses on reducing the overhead of fault tolerance and improving the ability of error correction. The technical advantage of the present invention is:

1. It can realize the protection of transient faults with a small area and delay overhead, requires only a small cost, and can maintain the performance advantages of high-speed adders;

2. Fully exploit the inherent hardware and time redundant resources in the adder, improve resource utilization efficiency, and reduce unnecessary waste of resources;

3. It can automatically correct the transient faults in the circuit, realizes strong fault tolerance, and greatly enhances the reliability of the adder.

The technique proposed by the present invention can be extended to other combinational circuit structures. With the rapid development of technology, the problem of transient faults in combinational circuits has become more and more serious. It is of great significance and practical value to develop the inherent redundant resources in combinational circuits to improve their reliability and require less overhead.

Description of drawings

Figure 1 Replica error correction and time shift error correction structure;

Figure 2C unit circuit structure;

The overall structure of the high-speed adder disclosed by the present invention of Fig. 3;

Fig. 4 The high-speed adder transient fault correction circuit group carry G/P generation part disclosed by the present invention;

Fig. 5 The carry tree part of the high-speed adder transient fault correction circuit disclosed by the present invention;

Fig. 6 schematic diagram of critical path and non-critical path of traditional high-speed adder based on sparse tree;

Fig. 7 The critical path and non-critical path parts of the high-speed adder transient fault correction circuit disclosed by the present invention;

Figure 8 compares the area, delay and area delay product of the present invention with other structures.

Detailed ways

The structure and working process of the low-overhead high-speed adder transient fault automatic correction circuit disclosed by the present invention will be described in detail below in conjunction with the accompanying drawings.

The low-overhead high-speed adder transient fault automatic correction circuit disclosed by the present invention consists of three parts, as shown in FIG. 3 , which are the group carry G/P generation part, the carry tree part, and the partial sum generation and selection part. In order to illustrate clearly, a 64-bit adder is taken as an example below. In fact, the structure of the present invention is applicable to adders of any bit width.

The group carry G/P generating part generates a 4-bit group G/P group carry signal. The input is 4-bit A _i+3 ～A _i and B _i+3 ～B _i , after three-level logic, the output group carry generation signal G _i+3,i and group carry propagation signal P _i+3,i , such as Figure 4 shows. The four solid rectangles at the top of the figure represent the following operations from right to left:

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; Equivalent</span>}<span\; class="notranslate">\; .</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span>$

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; Equivalent</span>}<span\; class="notranslate">\; .</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; ]</span>$

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; Equivalent</span>}<span\; class="notranslate">\; .</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; ]</span>$

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; B</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; Equivalent</span>}<span\; class="notranslate">\; .</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; ]</span>$

The two solid circles in the middle layer represent the following operations from right to left:

G _i+1,i =G _i+1 +P _i+1 G _i ,P _i+1,i =P _i+1 P _i [Equ.5]

G _i+3,i+2 =G _i+3 +P _i+3 G _i+2 ,P _i+3,i+2 =P _i+3 P _i+2 [Equ.6]

A solid circle at the bottom indicates the following operations:

G _i+3,i =G _i+3,i+2 +P _i+3,i+2 G _i+1,i ,P _i+3,i =P _i+3,i+2 P _{i +1,i} [Equ.7]

In the 64-bit adder, there are 16 groups of carry G/P generation modules in Figure 4. In order to enhance the reliability of the group carry G/P generation part, each module has a copy, the two copies use the same input, and the output is connected to a different signal of the sparse carry tree.

The part of the sparse carry tree is composed of the entire column of sparse carry nodes, an increased one-level carry node and the last group of C units, as shown in Figure 5. The sparse carry node array is the part in the blue box in the figure. They are similar to the carry node array of an N/4-bit Kogge-Stone (KS) adder. For a 64-bit adder, it consists of 16 columns. Each There are 4 levels in total, and each solid circular node realizes the following functions:

G _i+1,i =G _i+1 +P _i+1 G _i ,P _i+1,i =P _i+1 P _i [Equ.8]

The hollow circles in the sparse carry node array implement the following functions:

G _{i+1, i} ＝G _i+1 +P _i+1 ·G _i [Equ.9]

In the sparse carry node array, the black nodes and lines are used to calculate the carry of 4i+3 (i=0, 2, 4, ..., 14), while the red nodes and lines are used to calculate 4i+3 ( i=1, 3, 5, . . . , 15) bit carry, there is no signal connection between the black and red parts, and they are independent of each other and do not affect each other. In this way, the black and red parts form natural hardware resource redundancy. We use this inherent redundancy feature for fault tolerance, which can greatly improve resource utilization.

In order to develop redundancy, a one-level carry node is added behind the sparse carry node array, so that every 4i+3 (i=0, 1, 2, . . . , 15) bit carry signal is calculated by two parts, black and red. The two groups of outputs of the group carry G/P generating part are respectively connected with the black and red signals. This way the adder carry tree forms two independent copies.

After adding one level of carry nodes, we add one level of C units. In this way, the carry tree of the adder is similar to the structure of the error correction of the replica, which can automatically correct any transient faults that occur in it. Unlike copy error correction, we do not need to add a lot of hardware overhead, but realize hardware replication by developing inherent hardware redundancy, which greatly reduces the area overhead of fault tolerance.

Figure 6 shows the critical path and non-critical path of the traditional sparse tree adder, wherein the non-critical path is the structure of the partial sum generation and selection part, which consists of two sets of 4-bit serial carry adders (Ripple Carry Adder, RCA) and a set of 4-bit multiplexers (MUX). Two sets of 4-bit carry-propagation adders generate the carry-in "0" part and psum0 and the carry-out part and psum1 respectively, psum0 and psum1 are connected to the multiplexer, and are selected by the carry signal obtained from the critical path , and finally get the sum of the adder. Since the delay on the non-critical path is much smaller than that on the critical path, there are more slack times that are not fully utilized. This part of the slack time is the inherent time redundancy resource in the adder. The present invention fully develops inherent time redundancy resources for fault tolerance by transforming non-critical paths, and utilizes time redundancy to reduce the area, thereby greatly reducing the time overhead of fault tolerance and simultaneously reducing the area of the chip.

The part proposed by the present invention and the generation and selection part are shown in FIG. 7 . We only use a 4-bit serial carry adder whose carry is "0" on the non-critical path, and a group of delay units τ are connected to the output of the 4-bit adder. The original output of the 4-bit adder and the delayed output of the τ unit are connected to a group of C units, which forms a structure similar to time-shifted error correction. Different from time-shift error correction, because it is in the non-critical path, we use the time redundancy in the adder to construct time-shift error correction, which will not increase the delay, that is, it will not cause any impact on the performance of the adder. loss.

The output of the C unit is psum0, and after the C unit, a proposed RIC module is connected to generate psum1. psum0 and psum1 are connected to the multiplexer to select and output the final result. Here we exploit time redundancy by using the RIC structure, reducing a 4-bit serial adder in exchange for area reduction. Therefore, the inherent time redundancy resources in non-critical paths are fully utilized, which not only increases the automatic error correction capability of the adder, but also reduces the use of devices, thereby reducing the area.

We compare the adder structure proposed by the present invention with other adders in terms of area, delay and area delay product (Area Delay Product, ADP), as shown in Figure 8. The comparison is based on the standard KS adder without error correction capability. The reliable adders involved in the comparison include triple-mode redundant adder (TMR), triple-mode redundant adder with RIC structure (TMR+RIC), and replica error-correcting adder device (ECD) and time shift error correction adder (ECTO). It can be seen from the results that the area of the three-mode redundant adder is about 300% of the standard KS adder, so the area delay product is as high as 3.96; The area is reduced to a certain extent, so the area delay product is lower than that of the three-mode redundant adder; because the copy error correction adder only uses dual-mode redundancy, the area is about 250% of the standard KS adder, Therefore the area delay product is reduced to 2.39; The time-shift error correction adder has the maximum delay, but its area overhead is reduced to very little, so the area delay product is correspondingly smaller, about 1.96; and the addition proposed by the present invention Due to the full development of the hardware redundancy and time redundancy in the adder, the area and delay are greatly reduced, which are about 112% and 106% of the standard KS adder, respectively. The substantial reduction in area and delay results in the structure of the present invention having the smallest area delay product of about 1.19.

To sum up, in view of the problem of large area overhead and delay overhead of reliable adders for automatic correction of transient faults, the present invention discloses a low-overhead high-speed automatic correction circuit for transient faults of adders. By fully developing the adder The hardware redundancy and time redundancy resources that exist naturally in the system can greatly reduce the area and delay overhead of automatic correction of transient faults of high-speed adders. The proposed technique can be extended to other combinational circuit structures. With the rapid development of technology, the problem of transient faults in combinational circuits is becoming more and more serious. It is of practical value to develop inherent redundant resources in combinational circuits to improve their reliability, which requires less overhead.

Claims (1)

1. a low overhead high-speed adder transient fault automatic correction circuit, characterized in that: By combining the inherent hardware redundancy in the carry tree of the critical path of the parallel adder and the C unit with transient fault correction capability, the automatic correction of transient faults in the critical path circuit can be realized with a low area overhead; by using the sparse tree The combination of structure and the development of inherent hardware redundancy greatly reduces the wiring complexity, further reduces the area, and improves performance at the same time; by combining the inherent time redundancy in the non-critical path of the parallel adder and the C Unit combination can realize automatic correction of transient faults in non-critical path circuits with low delay overhead; by combining Inverted Carry-In (RIC) technology with the development of inherent time redundancy, non-critical The slack time of the critical path is exchanged for hardware consumption, further reducing the area of the adder; the specific circuit form includes three components: group carry (G/P) generation, carry tree on the critical path, and partial sum generation and selection on the non-critical path part; the group carry (G/P) generation part includes two groups of independent group carry (G/P) generation modules to form a copy structure; the sparse tree part of the carry tree is combined with a (N/4) Kogge-Stone The carry tree is the same. After the sparse carry tree, one-level carry logic needs to be added to generate two sets of independent carry signals from the parity carry signal; the added one-level carry logic is followed by a group of C units to form a copy error correction structure; The sum generation and selection part uses a group of 4-bit serial carry adders, and the input (Cin) is "0"; the 4-bit serial carry adder is followed by a group of C units, and the two inputs of the C units are respectively 4-bit strings The output of the carry bit adder and the output of the 4-bit serial carry adder after the delay of the τ unit form a time-shift error correction structure; after the C unit, the RIC structure is used to generate two outputs (Psum0 and Psum1), and finally after a multiple The path selector (MUX) is selected to obtain the final output result of the adder.

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