CN102254862A

CN102254862A - Semiconductor device manufacturing method

Info

Publication number: CN102254862A
Application number: CN2010101830425A
Authority: CN
Inventors: 张文雄
Original assignee: HONGBAO TECHNOLOGY CO LTD
Current assignee: Sharp Corp
Priority date: 2010-05-18
Filing date: 2010-05-18
Publication date: 2011-11-23
Anticipated expiration: 2030-05-18
Also published as: CN102254862B

Abstract

The invention provides a semiconductor device manufacturing method, which comprises the following steps of: first providing a bearing substrate and a plurality of wafer slices, wherein each wafer slice has an active surface and a back surface which are opposite to each other, and comprises at least one connection gasket positioned on the active surface; then forming bonding layers between the bearing substrate and the active surfaces of the wafer slices to bond the wafer slices to the bearing substrate; next forming at least one silicon through hole in each wafer slice to electrically connect the wafer slices and corresponding connection gaskets; and finally separating the wafer slices from the bearing substrate. By the method, the bearing substrate is reusable, and subsequent processes can be performed on parts, with high yield, in wafers to save the cost and improve the whole process yield.

Description

The manufacture method of semiconductor device

Technical field

The present invention relates to semiconductor device, and particularly relate to a kind of manufacture method of semiconductor device.

Background technology

The most basic process unit is the full wafer wafer in the conventional semiconductor process equipment, and the full wafer wafer is after processing, and the defective because of processing technology has the subregion to take place electrically or the situation of dysplasia inevitably.When these bad districts account for the ratio of the wafer gross area area when too high,, be tantamount to waste the production capacity of process equipment, and then increased the technology cost, and reduced process efficiency if follow-uply carry out processed with the full wafer wafer again.

Summary of the invention

Purpose of the present invention is exactly that a kind of manufacture method of semiconductor device is being provided, and can reduce the technology cost and improve process efficiency.

For reaching above-mentioned purpose, the present invention proposes a kind of manufacture method of semiconductor device.At first, provide bearing basement and a plurality of wafer slice.Each wafer slice has the active surface and the back side, and wherein active surface is relative with the back side, and each wafer slice comprises at least one connection gasket, is positioned on the active surface.Then, between the active surface of bearing basement and wafer slice, form adhesion coating, so that wafer slice is adhered on the bearing basement.In each wafer slice, form at least one silicon through hole again and electrically connect with corresponding connection gasket.Afterwards, make these wafer slice separate with bearing basement.

In a preferred embodiment of the invention, above-mentioned adhesion coating is patterned distribution between bearing basement and wafer slice.

In a preferred embodiment of the invention, making above-mentioned these wafer slice and bearing basement after separating, also comprising each wafer slice is cut, to obtain a plurality of chips (chip).

In a preferred embodiment of the invention, the method that removes above-mentioned adhesion coating comprises UV-irradiation, hot melt, mechanical stripping or dissolution with solvents.

In a preferred embodiment of the invention, the method that forms silicon through hole is to form at least one perforation earlier in each wafer slice, then forms dielectric layer at the back side of wafer slice, so that dielectric layer is inserted in these perforations.Then, remove the part dielectric layer of position in perforation, to expose corresponding connection gasket.Afterwards, in these perforations, insert metal level, to form the silicon through hole that electrically connects with connection gasket.

In a preferred embodiment of the invention, the method that above-mentioned wafer slice is provided can be that the wafer with at least one available area and at least one bad district is provided earlier, then along the available area cut crystal, to obtain above-mentioned wafer slice.

In a preferred embodiment of the invention, above-mentioned bearing basement is a transparent substrates.

In a preferred embodiment of the invention, wherein before forming above-mentioned these silicon through hole, also comprise above-mentioned these wafer slice of thinning.

The manufacture method of semiconductor device of the present invention adheres to these wafer slice on the bearing basement that meets the board specification after can picking out the available area of each wafer earlier and it being cut down again, is beneficial to carry out follow-up silicon through hole technology.And, because being adhesion coatings with the temporary adhesion strength of tool, these wafer slice are adhered on the bearing basement, therefore can before being cut into chip, wafer slice earlier wafer slice be separated with bearing basement, but so that bearing basement tool reuse.That is to say that the present invention can carry out subsequent technique at the high part of yield in the single-wafer, to save cost and to improve the overall process yield.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Figure 1A to Fig. 1 H illustrates and is the generalized section of semiconductor device in the embodiments of the invention in part technology.

Fig. 2 A to Fig. 2 B illustrates the schematic diagram for the method that wafer slice is provided in the embodiments of the invention.

Fig. 3 A to Fig. 3 B illustrates to form the flow process profile of metal level in the embodiments of the invention in perforation.

Fig. 4 is the generalized section of semiconductor device in part technology in the embodiments of the invention.

Fig. 5 illustrates and is the generalized section of semiconductor device in the embodiments of the invention in part technology.

Description of reference numerals

100: wafer

102: available area

104: bad district

110: bearing basement

120: wafer slice

122: active surface

124: the back side

126: connection gasket

127: silicon through hole

127a: perforation

127b: dielectric layer

127c, 129a: metal level

129b: metal pattern

128: semiconductor element

130: adhesion coating

200: chip

Embodiment

See also Figure 1A to Fig. 1 H, it illustrates the generalized section of semiconductor device in part technology into embodiments of the invention.

See also Figure 1A, bearing basement 110 and a plurality of wafer slice 120 at first are provided.Bearing basement 110 can be transparent circular-base, meeting existing board, but not as limit.Each wafer slice 120 have respectively respect to one another active surperficial 122 with the back side 124, and each wafer slice 120 can comprise at least one connection gasket 126, is positioned on active surperficial 122.Specifically, connection gasket 126 be formed on wafer slice 120 active surperficial 122 on circuit (figure does not show) electrically connect.In addition, wafer slice 120 active surperficial 122 on be formed with at least one semiconductor element 128, it is by circuit and connection gasket 126 and electrically connect with external circuit.In the present embodiment, semiconductor element 128 for example is microlens array (micro lens array) and colored filter (color filter) array, but the present invention is not as limit.

What deserves to be mentioned is that these wafer slice 120 can be from same wafer, also can be from different wafer.Specifically, shown in Fig. 2 A, present embodiment provides the wafer 100 with known available area 102 and bad district 104 earlier, and then shown in Fig. 2 B, along available area 102 cut crystals 100, to obtain wafer slice 120.In other words, wafer slice 120 is to get by the available area 102 that cuts lower wafer 100.

See also Figure 1B, at active surperficial 122 formation adhesion coatings 130 of bearing basement 110 and wafer slice 120, so that wafer slice 120 is adhered on the bearing basement 110.In the present embodiment, adhesion coating 130 can be covered with between active surperficial 122 and bearing basement 110 of wafer slice 120.Specifically, adhesion coating 130 is the adhesion coatings with temporary adhesion strength, for example ultraviolet glue, PUR or can solvent with the solvable dispergation of its dissolving, but the present invention is not as limit.

See also Fig. 1 C, carry out thinning technology, with the thickness of reduction wafer slice 120 from the back side 124 of these wafer slice 120.And the wafer slice 120 of present embodiment at the thickness after the thinning technology approximately between 100～200 microns, but the present invention is as limit, persons skilled in the art can be decided according to actual demand voluntarily.

See also Fig. 1 D to Fig. 1 F, in each wafer slice 120, form at least one silicon through hole 127 and electrically connect with connection gasket 126.Specifically, the method that forms silicon through hole 127 is to form at least one perforation 127a earlier in each wafer slice 120, shown in Fig. 1 D, and the method that forms perforation 127a can be laser beam perforation or dark reactive ion etch (deep reactive ion etching, DRIE), but not as limit.

Please consult Fig. 1 E again, then on the back side 124 of wafer slice 120, form dielectric layer 127b, and it is inserted in the perforation 127a.Then, remove and be positioned at perforation 127a and connection gasket 126 lip-deep part dielectric layer 127b, to expose connection gasket 126.In the present embodiment, dielectric layer 127b for example is a silicon dioxide, but not as limit.Can be to use laser or dark reactive ion etch and remove the method that is positioned at part dielectric layer 127b, but not as limit.

Afterwards, please refer to Fig. 1 F, in perforation 127a, insert metal level 127c, and form the silicon through hole 127 that electrically connects with corresponding connection gasket 126.At this, metal level 127c is electrically insulated with wafer slice 120 by dielectric layer 127b, with the problem of avoiding being short-circuited between each silicon through hole 127.And the self-corresponding perforation 127a of each metal level 127c extends to the back side 124 of this wafer slice 120.Specifically, the method that forms metal level 127c is to form layer of metal layer 129a earlier on the back side 124 of these wafer slice 120, as shown in Figure 3A, and to fill up the perforation 127a of each wafer slice 120.Then, shown in Fig. 3 B, remove the part metals layer 129a on the back side 124 that is positioned at wafer slice 120.For instance, the part metals layer 129a of position on the back side 124 of wafer slice 120 for example is by chemico-mechanical polishing (Chemical Mechanical Polishing, mode CMP) and being removed.

Follow-up, on the back side 124 of wafer slice 120, form a plurality of metal pattern 129b shown in Fig. 1 F, and electrically connect with metal level 129a respectively.That is to say that the metal level 127c of present embodiment is made of metal level 129a and metal pattern 129b, wherein metal level 129a is different with the material of metal pattern 129b, but the invention is not restricted to this.In other embodiments, metal level 127c also can be formed on the back side 124 of wafer slice 120, and conformally inserts the single rete in the perforation 127a, as shown in Figure 4.At this, metal level 127c can by high conductive material for example copper, aluminium or other high conductive materials make, but not as limit.

After forming metal level 127c, make wafer slice 120 separate, shown in Fig. 1 G with bearing basement 110.Specifically, present embodiment for example is with UV-irradiation adhesion coating 130, hot melt adhesion coating 130, utilizes mechanical force that wafer slice 120 is peeled off in the substrate 110 or come separating wafer section 120 and bearing basement 110 in modes such as dissolution with solvents adhesion coatings 130 from carrying, but the present invention is not as limit.

It should be noted that, though present embodiment is that adhesion coating 130 is covered with between bearing basement 110 and wafer slice 120, but in other embodiments, as shown in Figure 5, adhesion coating 130 is distributed between bearing basement 110 and the wafer slice 120 with also can being patterning, and not with wafer slice 120 active surperficial 122 on element contact, to avoid when removing adhesion coating 130, damaging these semiconductor elements 128.

See also Fig. 1 H, present embodiment more then cuts each wafer slice 120 with wafer slice 120 and bearing basement 110 after separatings, uses for follow-up packaging technology to obtain a plurality of chips 200.For instance, these chips 200 can be CMOS image sensor, chip of micro-electro-mechanical system, high-frequency semiconductor element or other semiconductor chips of stacked package each other, but the present invention is not as limit.

In sum, the manufacture method of semiconductor device of the present invention adheres to these wafer slice on the bearing basement that meets the board specification, to carry out subsequent technique after can picking out the available area of each wafer earlier and it being cut down again.That is to say that the present invention can carry out subsequent technique at the high part of yield in the single-wafer, to save cost and to improve the overall process yield.

And these wafer slice can be adhered on the bearing basement by the adhesion coating of the temporary adhesion strength of tool, and before wafer slice is cut into chip, earlier wafer slice are separated with bearing basement.Thus, bearing basement is promptly reusable, with further reduction technology cost.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any persons skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.

Claims

1. the manufacture method of a semiconductor device comprises:

Bearing basement and a plurality of wafer slice are provided, and respectively this wafer slice has the active surface and the back side, and wherein this active surface is relative with this back side, and respectively this wafer slice comprises at least one connection gasket, is positioned on this active surface;

Between this active surface of this bearing basement and these a plurality of wafer slice, form adhesion coating, should a plurality of wafer slice adhering on this bearing basement;

In this wafer slice respectively, form at least one silicon through hole and electrically connect with these a plurality of connection gaskets; And

Make these a plurality of wafer slice separate with this bearing basement.

2. the manufacture method of semiconductor device as claimed in claim 1, wherein this adhesion coating is patterned distribution between this bearing basement and this a plurality of wafer slice.

3. the manufacture method of semiconductor device as claimed in claim 1 wherein makes these a plurality of wafer slice and this bearing basement after separating, also comprises respectively this wafer slice of cutting, to obtain a plurality of chips respectively.

4. the manufacture method of semiconductor device as claimed in claim 1, the method that wherein makes these a plurality of wafer slice separate with this bearing basement comprise with this adhesion coating of UV-irradiation, this adhesion coating of hot melt, mechanical stripping or with this adhesion coating of dissolution with solvents.

5. the manufacture method of semiconductor device as claimed in claim 1, the method that wherein forms these a plurality of silicon through hole comprises:

In respectively forming consistent at least hole in this wafer slice;

Form dielectric layer on the back side of these a plurality of wafer slice, wherein this dielectric layer is inserted in these a plurality of perforations;

Remove this dielectric layer of part that is positioned at these a plurality of perforations, to expose this a plurality of connection gaskets; And

In these a plurality of perforations, insert metal level, electrically connect with these a plurality of connection gaskets to form these a plurality of silicon through hole.

6. the manufacture method of semiconductor device as claimed in claim 1 wherein provides the method for these a plurality of wafer slice to comprise:

Wafer is provided, and this wafer has at least one available area and at least one bad district; And

Cut this wafer along this available area, to obtain these a plurality of wafer slice.

7. the manufacture method of semiconductor device as claimed in claim 1, this bearing basement is a transparent substrates.

8. the manufacture method of semiconductor device as claimed in claim 1 wherein before forming these a plurality of silicon through hole, also comprises these a plurality of wafer slice of thinning.