CN105514038A - Methods for dicing semiconductor wafer - Google Patents

Methods for dicing semiconductor wafer Download PDF

Info

Publication number
CN105514038A
CN105514038A CN201510669938.7A CN201510669938A CN105514038A CN 105514038 A CN105514038 A CN 105514038A CN 201510669938 A CN201510669938 A CN 201510669938A CN 105514038 A CN105514038 A CN 105514038A
Authority
CN
China
Prior art keywords
wafer
film
nude film
passivation layer
active surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510669938.7A
Other languages
Chinese (zh)
Other versions
CN105514038B (en
Inventor
尼尔逊·威廉·约翰
苏斯王孙逊·奈萨厐
何明永
王宝龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UTAC Headquarters Pte Ltd
Original Assignee
UTAC Headquarters Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UTAC Headquarters Pte Ltd filed Critical UTAC Headquarters Pte Ltd
Publication of CN105514038A publication Critical patent/CN105514038A/en
Application granted granted Critical
Publication of CN105514038B publication Critical patent/CN105514038B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Abstract

Methods for dicing a wafer are presented. The method includes providing a wafer having first and second major surfaces. The wafer is provided with a plurality of dies on main device regions. The dies are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

Description

The method of cutting semiconductor chip
The cross reference of related application
This application claims U.S. Provisional Application numbers 62062,967, on October 13 2014 applying date, the priority of title " method of cutting semiconductor chip ", its disclosure is all herein incorporated by reference for various object.
Background technology
Cutting technique, is also called segmentation, is commonly used to the multiple chips be separated to form on wafer.Various cutting technique can be adopted the multiple chips be formed on wafer to be separated into one single chip and to be used for encapsulation.A kind of conventional process is mechanical sawing.In mechanical sawing process, the diamond saw of high speed rotating along saw lanes or segmentation passage chip is separate.But due to the mechanical stress that the edge of a knife causes, easily there is crackle or chip in each chip.In addition, it is very time-consuming for adopting mechanical sawing to separate chip from full wafer wafer.
In order to alleviate the problems referred to above, a kind of plasma etching process is proposed for cutting or segmentation wafer.But we find, common plasma etching process can not separate nude film from wafer effectively, and the nude film of cutting also may suffer the pollution that caused by plasma etching process.Common plasma etching process also can cause coarse or uneven side surface or the sidewall of the nude film cut.
In view of this, reliable desirable to provide one, simple, efficient, cost-effective method, for from wafer cutting semiconductor chip or nude film.
Summary of the invention
Usually, embodiment relates to the cutting method of semiconductor die.In one aspect, a kind of method splitting wafer is disclosed.The method comprises the wafer providing and have the first first type surface and the second first type surface.Wafer preparation has multiple nude film, and the plurality of nude film is positioned on main equipment region, and is separated from each other by the segmentation passage on wafer first first type surface.First first type surface or the second first type surface of wafer provide film.This film at least covers the region corresponding to main equipment region.The method also comprises and utilizes film as etching mask, and the multiple nude films on described wafer are separated into multiple independent nude film to form space by the semiconductor material plasma etched wafer exposed by wafer.
These embodiments and other advantages disclosed herein and feature, will by apparent in conjunction with following description and accompanying drawing.In addition, it is not mutually exclusive for should understanding each embodiment described herein, can be present in various assembled arrangement.
Accompanying drawing explanation
In accompanying drawing, identical Reference numeral generally represents the same parts in different views.In addition, accompanying drawing is not necessarily drawn in proportion, but generally focuses in explanation principle of the present invention.In following description, describe various embodiments of the present invention with reference to the accompanying drawings, wherein:
Fig. 1 illustrates the simplification front view of semiconductor wafer;
Fig. 2 a-2e, Fig. 3 a-3b, Fig. 4 a-4d and Fig. 5 a-5d illustrate each embodiment of the technique of cutting semiconductor chip.
Embodiment
Usually, embodiment relates to the method for cutting or dividing semiconductor wafer.Embodiment described by the disclosure relates to the plasma etching process in cutting technique.Embodiment of the present disclosure can be applicable to the wafer cutting any type, comprises the wafer to mechanical stress sensitivity, such as wherein has the wafer of low k and ultralow-k material film.In the disclosure, the cutting method of description also be can be used for wafer-level chip scale package (WLCSP) application, after wherein carrying out wafer-class encapsulation, perform segmentation.Such as, described chip/nude film or encapsulation can comprise the integrated circuit (IC) of any type, such as memory device, optoelectronic device, logical device, communication equipment, digital signal processor (DSP), microcontroller, system integrated chip and other types equipment or its combination, wherein memory device comprises dynamic random access memory (DRAM), static RAM (SRAM) and various types of nonvolatile memory (comprising programmable read only memory (PROM) and flash memory).These die/chip or encapsulation can be incorporated to electronic product or equipment, such as mobile phone, computer and mobile product and intelligent movable product.Nude film also can be used for being incorporated to other types product.
Fig. 1 illustrates the simplification front view of semiconductor wafer 110.Such as, semiconductor wafer can be silicon chip.Also the wafer of other suitable type can be used.Such as, wafer can be p-type or N-shaped wafers doped.
See Fig. 1, wafer comprises first surface 110a, first surface 110a is formed with multiple die/chip 115.The plurality of die/chip can walk abreast formation on wafer.Such as, nude film is arranged along the row of first direction (x) and the row of second direction (y).Shown wafer comprises multiple main equipment region 122 and framework (or circumference) region 126.Main equipment region comprises the characteristic sum cross tie part of semiconductor die or chip.Main equipment region comprises circuit unit (not shown), and such as transistor, resistor, capacitor and interconnects are to form die/chip.For perimeter region, it is around main equipment region.Such as, perimeter region does not comprise circuit unit, and on wafer, be used as scribing road or segmentation passage/road 126.Adjacent die/chip is spaced by scribing road or segmentation passage or is separated.By along these scribing roads or segmentation channel segmentation wafer, nude film is separated from each other.Each cutting method described below can be used for separating nude film from wafer.
Fig. 2 a-2e illustrates from wafer cutting semiconductor nude film or the method for chip or the embodiment of technique 200.Such as, wafer can be similar to or be same as the wafer 110 illustrating as Fig. 1 and describe.Like this, for simplicity, mutual component or the feature with same reference numbers do not describe or are not described in detail.
Fig. 2 a illustrates the wafer 110 with first surface 110a and second surface 110b.Wafer is used as the substrate forming nude film or chip.Such as, first surface 110a is active surface, and second surface 110b is passive surface or passive surface.The active surface of wafer refers to the surface wherein defining integrated circuit.The passive surface of wafer refers to the back side on the surface wherein defining integrated circuit.Such as, wafer comprises semiconductor wafer, such as silicon chip.Also the semiconductor wafer of other suitable type can be used.In one embodiment, wafer, through process, comprises multiple nude film or chip 115.Such as, multiple nude film parallel processing on wafer.Nude film 115 comprises the circuit unit on the active surface being formed in wafer or substrate.Such as, circuit unit comprises transistor, resistor, capacitor and interconnects to form IC integrated circuit.Multiple nude film is formed on wafer, and by scribing road or segmentation passage/road spaced.In order to the object simplified and illustrate, wafer as shown in Figure 2 a, comprises four nude films 115 1-115 4.Should be understood that the nude film that wafer can comprise different suitable number is located thereon.As shown, each nude film 115 1-115 4spaced by segmentation passage/road 126.
The active surface of wafer performs front end of line (FEOL) technique to form circuit unit, perform back end of line (BEOL) technique to form cross tie part (as metal wire or contact via hole).As shown in Figure 2 a, wafer 110 is processed until wherein stage of being formed on the active surface of wafer of final passivating film or layer 131.Such as, this final passivation layer comprises polyimides, and can pass through chemical vapour deposition (CVD) (CVD) formation on the active surface of wafer.Also other suitable dielectric material and technology can be adopted to form final passivation layer.In one embodiment, passivation layer 132 is formed in the mode do not extended on segmentation passage/road 126.Such as, this realizes by mask technique or etching technique.Such as, passivation layer can be deposited on the active surface of wafer, and the passivation layer part on segmentation passage can adopt mask etch technology to be removed by etching.Alternatively, when passivation layer deposition is on wafer, mask can be provided if photoresist is to cover segmentation passage.The passivation layer be configured on mask can be removed together with photoresist, leaves the passivation layer in main equipment region.The technology that other also can be used to be applicable to, makes passivation layer be arranged on the circumference in main equipment region, and does not extend to the perimeter region corresponding to segmentation passage.
According to demand, one or more monitoring pattern 135 can be formed in the segmentation passage/road of wafer.Such as, this monitoring pattern (monitoringpattern) comprises the alignment mark/pattern of the accurate aligning for ensureing wafer in a lithographic process, the layer whether actual process control modules (PCM) with desired thickness and size is formed for confirming, or the test element group (TEG) of electrology characteristic for the circuit unit of measuring formation.Also other monitoring pattern be applicable to can be formed in segmentation passage.Such as, monitor pattern and comprise metal material, such as copper.Also the metal material of other suitable type can be used.
In one embodiment, the opening (not shown) of the final passivation layer 132 that the active surface 110a of wafer is formed exposes die contact pad (not shown), this die contact pad is formed row's external electrical contacts or a die contact part 170.Die contact pad provides the connector of the circuit for nude film.Such as, die contact pad is made up of electric conducting material, such as copper, aluminium, gold, nickel or its alloy.The electric conducting material of other type also can be used for die contact pad.
In one embodiment, wafer is with salient point, and its external contacts 170 has the chondritic or sphere that are formed on the active surface of wafer, as shown in Figure 2 a.Such as, external contacts comprises soldered ball.Thering is provided the external contacts of other suitable type, is also feasible such as, but not limited to copper post, copper post with solder cap, principal column projection or its combination.External contacts provides electrical connector, for coupling external equipment (not shown), and such as circuit board.In other embodiments, at this operation stage, wafer can not provide external contacts.
A part for wafer substrates 110 can be removed.In one embodiment, Partial wafer substrate can adopt backgrinding process to remove.This is by realizing the wafer transfer of part process to support platform 140, as shown in Figure 2 a.Such as, supporting platform can be grinding back surface band.The wafer arrangement of this part process, in support platform, makes the active surface 110a of wafer towards support platform.Due to the adhesion characteristics of grinding back surface band, the active surface of wafer adheres to grinding back surface band.As shown, external contacts 170 is attached and is embedded in grinding back surface band.In one embodiment, grinding back surface band does not extend to the edge of wafer, and the part of the active surface of wafer is exposed along the edge of wafer.
The second surface 110b that process wafer exposes.Such as, this technique removes part wafer substrates from second surface, and the thickness of wafer is reduced to T2 from thickness T1 originally.In one embodiment, the thickness of wafer substrates is reduced by mechanical lapping, chemical etching or its combination.Other technology be applicable to also can be used for removing part wafer substrates, to reduce the thickness of wafer.In one embodiment, the thickness of wafer is reduced to thickness T2, about 200-300 μm.Also other suitable thickness sizes can be used.
See Fig. 2 b, be provided in the film that the second surface 110a of wafer is formed.In one embodiment, this film is back-protective layer 150.Such as, back-protective layer comprises thermoplastic polymer based resin molding, and it has heat curing-type viscosity.Back-protective layer can be arranged by belt-like form, and is put on second (or passive) surperficial 110b of wafer by laminating technology.Other material be applicable to and technology comprise some glue, a rolling etc. and also can be used for forming back-protective layer.Such as, back-protective layer 150 comprises the thickness of about 25 μm.Also other suitable thickness sizes can be used.
In one embodiment, this technique proceeds to process back-protective layer 150.As shown in Figure 2 c, optionally remove part back-protective layer, with the part below second (or passive) the surperficial 110b exposing wafer.In one embodiment, the part that back-protective layer is configured in corresponding to the segmentation passage/road on the active surface of wafer is removed.In one embodiment, these partial rear protective layers are by removals such as chemical etching, laser ablation, mechanical sawings.In one embodiment; utilize thermal camera to identify and recorded information; the position, size etc. of the segmentation passage on such as active surface, carry out guiding tool (such as laser beam, diamond cut off wheel) from passive surface removal partial rear protective layer.Also can adopt other appropriate technology, the partial rear protective layer guaranteeing to cover the region corresponding to segmentation passage is removed.
The semi-conducting material of the wafer that this technique continuation removal is not protected by back-protective layer and exposed.As shown in Figure 2 d, wafer is placed in plasma etching chamber 250.This plasma etching chamber can be the plasma etching chamber of any suitable type.Fig. 2 d illustrates the simplification view of plasma etch.This plasma etching chamber comprises the first (top) plate and second (bottom) plate, or electrode 252 and 254.Top plate and bottom plate all with power supply 256 electric coupling.Power supply can be DC DC power supply.Also other suitable power supply can be used electrically to be biased top electrodes and bottom electrode.Such as, bottom electrode 254 comprises the cavity holding and have the wafer 110 of grinding back surface band 140.In one embodiment, wafer arrangement on bottom electrode, make its active surface 110a towards and be configured on bottom electrode 254, and its passive surperficial 110b bottom electrode dorsad.As mentioned above, grinding back surface band does not extend to the edge of wafer.This makes grinding back surface band be configured in the cavity of bottom electrode, and the end portion of the active surface of the wafer exposed along the edge of wafer is configured in the jag part of bottom electrode and contacts with it, makes wafer bias in follow-up plasma etching process.Also other bottom electrode being applicable to configuration can be used to keep and the biased wafer with grinding back surface band.
Plasma etching chamber is provided with the reacting gas optionally can removing the semi-conducting material of wafer.The reacting gas utilized has high selectivity for the semi-conducting material such as silicon of wafer.Reacting gas is generally fluorine base gas, such as SF 6, C 4f 8, CHF 3, XeF 2or other suitable silicon materials for wafer substrates have the reacting gas of high selectivity.Electromagnetic field (not shown) puts on bottom electrode.The gas molecule of this electric field ionization reaction gas, produces etch plasma 258.As shown, etch plasma is being formed with on the wafer 110 of back-protective layer 150.In one embodiment, the semi-conducting material of the wafer do not protected by back-protective layer that plasma etching or removal are exposed, as silicon.Therefore, in plasma etching process, the back-protective layer of process protects the semi-conducting material below it, and is also used as etching mask.As shown in Figure 2 d, in one embodiment, do not covered by back-protective layer and the semi-conducting material of wafer that exposes, the passive surperficial 110b utilizing plasma etching process to pass through to expose removes.Therefore, due to the removal of the semi-conducting material of wafer of exposing, space 145 is formed.Because the silicon materials of plasma etching process to wafer have high selectivity, when arrive at such as grinding back surface band or monitoring pattern (if any words) non-silicon material time, this plasma etching process stops.Therefore, the wafer substrate material that plasma etching process exposes in etched voids, until silicon materials are completely removed, to form the space or groove that extend downward grinding back surface band top.Such as, this space has and the identical width of segmentation passage, and with wafer thickness T 2the identical degree of depth.
In one embodiment, this technique proceeds to the Support bracket 230 providing and have top surface 230a and lower surface 230b.This Support bracket can be the interim bracket of the wafer of process etching.This bracket has enough rigidity, to be used as the temporary support keeping grinding back surface band in subsequent technique.As non-limiting example, Support bracket can be silicon wafer, metallic plate etc.The material of various applicable type also can be used for as Support bracket.
In one embodiment, by being attached on first or the top surface 230 of Support bracket by grinding back surface band, the wafer being attached with grinding back surface band is transferred to interim bracket, as shown in Figure 2 e.Grinding back surface band is attached to interim bracket due to its adhesion characteristic.Therefore, do not need additional adhesives that grinding back surface band is attached to Support bracket.In other embodiments, adhesive layer can be set and will there is the die attach of grinding back surface band to Support bracket.The adhesive of various suitable type can be used, the temporary adhesion of grinding back surface band and Support bracket is provided.
In one embodiment, unsticking process is performed.This unsticking process can cause grinding back surface band to lose or reduce its bonding strength, separates from grinding back surface band to make the die/chip of cutting.Such as, this unsticking process comprises temperature or heat treatment.Also the unsticking process of other types can be used.The type of grinding back surface band is depended in unsticking process.Such as, unsticking process can comprise any suitable process, such as thermal process, UV radiation or its combination.Each nude film cut off by plasma etching process completely or chip are by picking up the instrument of putting to pick up.In other embodiments, grinding back surface band can be attached to wafer ring (not shown) before putting on the active surface of wafer.In this case, after plasma etching process, wafer ring and grinding back surface band are used as Support bracket.When after nude film pickup, monitoring pattern 135, such as alignment mark or pattern, PCM or TEG, will stay on the surface of lapping tape 140 overleaf.
Fig. 3 a-3b illustrates the embodiment of technique 300 from wafer cutting or dividing semiconductor nude film or chip.This technique 300 can comprise the similar technical process described in the technique 200 with such as Fig. 2 a-2e.For simplicity, mutual component or the feature with same reference numbers can not describe or be not described in detail.Description below mainly concentrates on the difference of technique 300 and technique 200.
As shown in Figure 3 a, at the same phase process wafer 110 that Fig. 2 a describes.In one embodiment, wafer 110, through process, comprises multiple nude film or chip 115.Multiple nude film is formed on wafer, and by scribing road or segmentation passage/road 126 spaced.According to demand, monitoring pattern 135, such as aligned pattern or mark, PCM and/or TEG, can be formed in the segmentation passage/road of wafer.Process wafer 110 is until wherein stage of being formed on the active surface 110a of wafer of final passivation layer 232.In one embodiment, passivation layer 232 is as shown in Figure 3 a with the difference of passivation layer 132 as shown in Figure 2 a, and passivation layer 232 is also formed in the mode extended along segmentation passage/road 126.Such as, this passivation layer 232 can cover the monitoring pattern of configuration in segmentation passage.
In one embodiment, wafer is the wafer with salient point, and its external contacts 170 has chondritic or sphere, the active surface of wafer is formed, as shown in Figure 3 a.Wafer arrangement in support platform 140, as on grinding back surface band.As shown, the active surface 110a of wafer is towards support platform.External contacts 170 is attached and is embedded in grinding back surface 140.Describe similar with Fig. 2 a, grinding back surface band does not extend to the edge of wafer, and the end portion of the active surface of wafer is exposed along the edge of wafer.
Technique 300 continues there is additional procedure, such as described by Fig. 2 b-2d.Such as; backgrinding process can be performed the initial thickness T1 of wafer is reduced to thickness T2; back-protective layer 150 is set on the surface at second (passive) of wafer and processes this back-protective layer, the back-protective layer segment be arranged on corresponding on the region in the segmentation passage/road on the active surface of wafer is removed.Additional technique also comprises the semi-conducting material performing plasma etching process and expose to remove wafer, and as silicon, its passive surface of exposing is not protected by back-protective layer.These additional technique relate to the material similar or identical with Fig. 2 b-2d and technology, and thus they describe accordingly and do not repeat them here.
Plasma etching process has high selectivity for the silicon materials of wafer.Like this, in one embodiment, the back-protective layer of process is used for plasma etching process as etching mask.When arrive at such as passivation layer 232 or monitoring pattern (if any words) non-silicon material time, this plasma etching process stops.Therefore, the wafer substrate material exposed in plasma etching process etched voids, until silicon materials are removed, to be formed to downward-extension until its arrive at passivation layer and/or monitoring pattern (if any words) surface.Such as, this space has the width identical with segmentation passage, and the degree of depth identical with wafer thickness T2.
In one embodiment, by being attached on first or top surface 230a of Support bracket by grinding back surface band, the wafer being attached with grinding back surface band is transferred to interim bracket 230, as shown in Figure 3 b.Unsticking process can be performed, make grinding back surface band lose its adhesiveness.Each nude film cut off by plasma etching process completely or chip are by picking up the instrument of putting to pick up.In one embodiment, in the pick-up process of nude film, passivation layer 232 can be cut off.Such as, the pulling force in pick-up process causes passivation layer 232 along the edge of nude film or sidewall fracture, and each die chips cuts off passivation layer each other.When after nude film pickup, monitoring pattern 135, such as alignment mark or pattern, PCM or TEG, will stay on the surface of lapping tape 140 overleaf.In another embodiment, the jet of air wind drift or laser beam puts on passivation layer by the space 145 formed in plasma etching process.Such as, the jet of air wind drift or laser beam removes the passivation layer part exposed in segmentation passage/road, makes the passivation layer of each chip separate.In other embodiments, overleaf protective layer 150 can arrange extra band (not shown), and grinding back surface band 140 is by the UV process that is applicable to or heat treatment removal.When removing or peel off grinding back surface passivation layer, passivation layer can cut off.This is by separate for the passivation layer of each chip.If extra band is arranged on back-protective layer, falsework can still be attached on grinding back surface band.Such as, this falsework being attached to grinding back surface band is removed in the lump by the stripping of lapping tape overleaf.Extra band can be segmentation band, metallic plate, semiconductor/ceramic wafers etc.
Fig. 4 a-4c illustrates another embodiment of the technique 400 from wafer cutting semiconductor nude film or chip.This technique 400 can comprise and the such as technique 200 of Fig. 2 a-2e and the similar technical process as described in the technique 300 of Fig. 3 a-3b.For simplicity, mutual component or the feature with same reference numbers can not describe or be not described in detail.Description below mainly concentrates on the difference of technique 400 and technique 200 or technique 300.
As shown in fig. 4 a, at the same phase process wafer 110 that Fig. 3 a describes.In one embodiment, wafer 110, through process, comprises multiple nude film or chip 115.Multiple nude film is formed on wafer, and by scribing road or segmentation passage/road 126 spaced.According to demand, monitoring pattern 135, such as aligned pattern or mark, PCM and/or TEG, can be formed in the segmentation passage/road of wafer.Process wafer 110 is until wherein stage of being formed on the active surface 110a of wafer of final passivating film or layer.In one embodiment, passivation layer 232 is also formed in the mode extended on segmentation passage/road 126, as shown in Figure 3 a.In other embodiments, the mode that passivation layer can not extend on segmentation passage/road 126 is formed, and is similar to passivation layer 132 as shown in Figure 2 a.
In one embodiment, wafer is the wafer with salient point, and its external contacts 170 is formed on the active surface of wafer, as shown in fig. 4 a.Such as, wafer can be arranged in the support platform of such as grinding back surface band (not shown), and performs backgrinding process to reduce the original depth of wafer, is similar to as depicted in fig. 2 a.Backgrinding process relates to and technology as shown in Figure 2 a, and thus its corresponding description does not repeat them here.
Support bracket 430 is provided with the wafer 110 of salient point.Such as, this Support bracket 430 is fixed by ring or framework 432, and with the interim bracket of the wafer dealt with salient point.This bracket should have enough rigidity, to be used as temporary support, and keeps wafer in the removal of lapping tape overleaf.As non-limiting example, Support bracket can be the wafer, metallic plate etc. of semiconductor/pottery.The material of various applicable type also can be used for as Support bracket.Support bracket comprises top main surfaces 430a and bottom major surface 430b.Wafer 110 is arranged on the top surface 430a of Support bracket.As shown, configuration wafer makes second of wafer (or passive) surperficial 110b contact the top surface 430a of Support bracket, and first of wafer (or active) surperficial 110a deviates from Support bracket, as shown in Figure 4 b.Support platform, as grinding back surface band (not shown), utilizes suitable unsticking process removing.
In one embodiment, this technique proceed to remove segmentation passage on passivation layer and monitoring pattern part (if any words), as shown in Figure 4 b.In one embodiment, these passivation layers and monitoring pattern part are removed by non-etched technology, comprise laser ablation, the sawing of slow-speed of revolution machinery etc.Also the technology of other suitable type can be used.These for passivation layer and monitoring pattern part (if any words) non-etched technology can control or reduce the formation of follow-up coarse/uneven side surface or sidewall.Remove these passivation layers and monitoring pattern part exposes the semi-conducting material of wafer below, as silicon.In other embodiments, the removal of these passivation layers and monitoring pattern part also can remove the semiconductive material portion below wafer.
See Fig. 4 c, this technique proceeds to arranges that wafer is in ion(ic) etching chamber.In one embodiment, wafer arrangement on bottom electrode, make its passive surperficial 110b towards and be configured on bottom electrode 254, and its active surface 110a bottom electrode dorsad.Such as, wafer 110 and supporting bracket 430 are arranged on bottom electrode.In this case, be different from the configuration of bottom electrode 254 as shown in Figure 2 d, bottom electrode 254 can have flat top surface, as illustrated in fig. 4 c.An embodiment, perform plasma etching process, the active surface 110a exposed by wafer removes the semi-conducting material not being passivated layer protection.In this situation, the passivating film that main equipment region configures or layer as etching mask, for removing the exposed portion of semi-conducting material in segmentation passage.Plasma etching process is similar to shown in Fig. 2 d, and thus it describes accordingly and does not repeat them here.
Plasma etching process has high selectivity for the silicon materials of wafer.Like this, in one embodiment, when arriving at non-silicon material as strutting piece 430, this plasma etching process stops.Therefore, the wafer substrate material that plasma etching exposes, until silicon materials are removed, with formed to downward-extension until it arrives at space or the groove 145 on the surface of Support bracket.Such as, this space has the width identical with segmentation passage.See Fig. 4 d, each nude film cut off by plasma etching process completely or chip configuration on Support bracket 430, to treat by picking up the instrument (not shown) of putting to pick up for further technique or encapsulation.
Fig. 5 a-5d illustrates an embodiment of the technique 500 from wafer cutting semiconductor nude film or chip.This technique 500 can comprise the similar technical process described in the technique 200 with Fig. 2 a-2e.For simplicity, mutual component or the feature with same reference numbers can not describe or be not described in detail.Description below mainly concentrates on the difference of technique 500 and technique 200.
As shown in Figure 5 a, be similar to shown in Fig. 2 a and process wafer 110.In one embodiment, wafer 110, through process, comprises multiple nude film or chip 115.Multiple nude film is formed on wafer, and by scribing road or segmentation passage/road 126 spaced.According to demand, monitoring pattern 135, such as aligned pattern or mark, PCM and/or TEG, can be formed in the segmentation passage/road of wafer.Process wafer 110 is until wherein stage of being formed on the active surface 110a of wafer of final passivation layer 532.In one embodiment, passivation layer 532 is similar with passivation layer 132 as shown in Figure 3 a, and passivation layer 532 is formed in the mode do not extended on segmentation passage/road 126.
In one embodiment, the opening (not shown) formed by the final passivation layer of configuration on the active surface 110a of wafer substrates exposes die contact pad (not shown).Die contact pad is applicable to hold or receive closing line.Such as, die contact pad is made up of electric conducting material, such as copper, aluminium, gold, nickel or its alloy.The electric conducting material of other type also can be used for die contact pad.
Wafer arrangement in support platform 140, as on grinding back surface band.In one embodiment, wafer is positioned in support platform, makes the active surface 110a of wafer towards support platform.As shown in Figure 5 a, due to the adhesion characteristics of grinding back surface band, active surface 110a and the passivation layer 532 of wafer adhere to grinding back surface band.Describe similar with Fig. 2 a, grinding back surface band does not extend to the edge of wafer, and the end portion of the active surface of wafer is exposed along the edge of wafer.
Technique 500 proceeds to the second surface 110b that process wafer exposes.Such as, utilize as shown in Figure 2 a with described technology, this technique continues to remove part wafer substrates, and the thickness of wafer is reduced to T2 from thickness T1 originally.In one embodiment, as shown in Figure 5 b, the second surface 110b of wafer provide and form nude film junction film 550.Such as, nude film junction film 550 is included in subsequent technique, by the to be used jointing material of the die attach of cutting to lead frame or package substrate.Nude film junction film 550 can be arranged by belt-like form, and is put on second (or passive) surperficial 110b of wafer by laminating technology.Other material be applicable to and technology (comprising some glue, a rolling etc.) also can be used for forming nude film junction film.Such as, nude film junction film 550 comprises the thickness of about 25 μm.Also other suitable thickness sizes can be used.
In one embodiment, this technique proceeds to process nude film junction film 550.As shown in Figure 5 c, optionally remove part nude film junction film, with the part below second (or passive) the surperficial 110b exposing wafer.In one embodiment, part nude film junction film is configured on the region in the segmentation passage/road corresponded on the active surface removing wafer.In one embodiment, this part nude film junction film is by removals such as chemical etching, laser ablation, mechanical sawings.In one embodiment, utilize thermal camera to identify and recorded information, such as position, size etc.The position, size etc. of the segmentation passage on such as active surface, carry out guiding tool (such as laser beam, diamond cut off wheel), with from passive surface removal part nude film junction film.Also can adopt other appropriate technology, the nude film junction film part guaranteeing to cover the region corresponding to segmentation passage is removed.
In other embodiments, the region of the passive surperficial 110b of the wafer on the main equipment region of nude film junction film 550 optionally on the active surface corresponding to wafer is formed, and does not extend to the passive surf zone of the wafer corresponding to segmentation passage.Such as, this under the assistance of template, optionally can form nude film junction film to realize by printing or spraying coating process on main equipment region.Also other appropriate technologies can be adopted to carry out selectivity and to form nude film junction film.
This technique proceeds to the wafer and the semi-conducting material exposed that removal do not protected by nude film junction film.In one embodiment, perform the semi-conducting material that plasma etching process exposes to remove wafer, such as silicon, it is not protected by nude film junction film by the passive surface of exposing, as fig 5d.In this case, in plasma etching process, nude film junction film protects the semi-conducting material of the wafer below it, and is also used as etching mask.Utilize and those reacting gas as similar in Fig. 2 d and technology, in ion(ic) etching chamber 250, perform plasma etching process, thus it describes accordingly and does not repeat them here.
Plasma etching process has high selectivity for the silicon materials of wafer.Like this, in one embodiment, when arriving at non-silicon material, such as strutting piece passivation layer or monitoring pattern (if any words), this plasma etching process stop.Therefore, the backing material that plasma etched wafer in space exposes, until silicon materials are removed, to be formed to downward-extension until its arrive at grinding back surface band and/or monitoring pattern (if any words) surface.Such as, this space has the width identical with segmentation passage.
In one embodiment, this technique 500 proceed to process to describe with Fig. 2 e and corresponding describe in similar additional technique.Such as, utilize the technology that Fig. 2 e describes, technique continues to remove grinding back surface band.The die/chip of being cut by plasma etching process is to wait to pick up the instrument of putting to pick up.Its passive surface has die/chip lead frame to be adhered to or the package substrate of nude film junction film, for subsequent technique or encapsulation.
About the technique 500 that Fig. 5 a-5d describes, illustrate that passivation layer does not extend to segmentation passage.In other embodiments, technique 500 can be revised, make the passivation layer 232 shown in passivation layer and Fig. 3 a similar, cover main equipment region and segmentation passage/road.In this case, reserved category is similar to or is same as the further technique of wafer that Fig. 5 a-5d describes, except such as described by Fig. 3 b in nude film pick process passivation layer can cut off.
Above-mentioned technique 200,300,400 and 500 produces benefit.Such as, described by Fig. 2 a-2e and Fig. 3 a-3b, in the plasma etching process of cutting die chips, electric contact piece 170 is embedded in grinding back surface band, and passivation layer is bonded to grinding back surface band.Therefore, the fluoride pollution on the electric contact piece of chip and passivation layer is avoided.As described, the backing material of plasma etching process to wafer has high selectivity, and this plasma etching process is performed by the passive surface of wafer.Therefore, plasma etching process effectively and intactly cuts off nude film from wafer, even if monitoring pattern is by obtained with the metal material of plasma generation chemical reaction and occur in the wafer, and avoids the deficient etching on passive surface.In addition, the side of smooth planar of the cutting nude film produced when above-described embodiment or sidewall are as the profile of the passivation layer on a chip, and the alignment mark on segmentation passage, the residue of PCM or TEG do not go wrong in the cutting procedure utilizing plasma etch techniques to carry out.
In addition, technique 200,300,400 or 500 provides higher throughput, this is because all chips/nude film is simultaneously from wafer cutting or separation.Owing to utilizing plasma etch techniques, but not mechanical sawing realizes segmentation, and described technique 200,300,400 or 500 can form less or narrower segmentation passage.This allows and forms more multicircuit assembly and the silicon maximized on wafer utilizes.Owing to reducing or avoiding the defect that mechanical stress causes, these embodiments also provide higher output.In addition, described dividing method can utilize existing production facility, and does not need for new or extras or lithographic equipment capital invested.
The present invention can embody in other specific forms and not depart from its spirit or essential characteristic.Thus, above-described embodiment should be regarded as illustrative and non-limiting the present invention in this article.

Claims (20)

1. split a method for wafer, comprising:
There is provided the wafer with the first first type surface and the second first type surface, wherein said wafer preparation has multiple nude film, and described nude film is positioned on main equipment region, and is separated from each other by the segmentation passage on described first first type surface of described wafer;
Described first first type surface or described second first type surface of described wafer provide film, and wherein said film at least covers the region corresponding to main equipment region; And
Utilize described film as etching mask, the semiconductor material plasma exposed by described wafer etches described wafer, to form space, the multiple nude films on described wafer is separated into multiple independent nude film.
2. the method for claim 1, wherein described first first type surface of described wafer is the active surface of definition integrated circuit, and described second first type surface of described wafer is passive surface.
3. method as claimed in claim 2, wherein, processes described wafer, makes it comprise the passivation layer of the described main equipment region formation at least on the described active surface of described wafer.
4. method as claimed in claim 3, comprises and provides support platform and be attached the described active surface of described wafer to described support platform.
5. method as claimed in claim 4, wherein, described passivation layer does not extend on segmentation passage.
6. method as claimed in claim 5, wherein, described wafer is included in the one or more monitoring patterns formed in the segmentation passage of described wafer, when the described active surface of described wafer is attached to described support platform, and support platform described in described one or more monitoring pattern contacts.
7. method as claimed in claim 6, wherein, the described passive surface providing described film to be included in described wafer arranges back-protective layer.
8. method as claimed in claim 7; wherein; described film is provided also to comprise the back-protective layer segment optionally removing the region be configured in corresponding to the segmentation passage on the described active surface of described wafer; wherein handled back-protective layer is used as etching mask, removes by the plasma etching process on passive surface described in described wafer the semi-conducting material that described wafer exposes.
9. method as claimed in claim 8, comprises and removes each nude film from described support platform, and wherein when after removal each nude film described, described monitoring pattern is stayed on the surface of described support platform.
10. method as claimed in claim 3, wherein, described wafer comprises one or more monitoring pattern, and it is formed in the segmentation passage of described wafer.
11. methods as claimed in claim 10, wherein, described passivation layer covers described main equipment region and extends to the described segmentation passage of the described one or more monitoring patterns on the described active surface covering described wafer.
12. methods as claimed in claim 11, wherein, providing described film to comprise provides the layer of the back-protective on the passive surface of described wafer.
13. methods as claimed in claim 12; wherein; described film is provided also to comprise the back-protective layer segment optionally removing the region be configured in corresponding to the segmentation passage/road on the described active surface of described wafer; wherein handled back-protective layer is used as etching mask, removes by the described passive surface plasma etch process of described wafer the semi-conducting material that described wafer exposes.
14. methods as claimed in claim 12, comprise and utilize nude film pick-up process to remove each nude film described from described support platform, and wherein when described nude film is removed by nude film pick-up process, the described passivation layer of described each nude film is cut-off and separate.
15. methods as claimed in claim 12, the described space comprised by being formed in described plasma etching process performs non-etched technique, to cut off and by separate for the passivation layer of each nude film.
16. methods as claimed in claim 15, are wherein performed described non-etched technique and comprise the jet being applied air wind drift or laser beam by described space.
17. methods as claimed in claim 2, the described active surface wherein providing described film to be included in described wafer provides passivation layer, and the main equipment region of wherein said passivation layer on the active surface of described wafer and segmentation passage are formed.
18. methods as claimed in claim 17, wherein, described film is provided also to comprise the passivation layer part optionally removing the region be configured in corresponding to the segmentation passage/road on the described active surface of described wafer, wherein handled passivation layer is used as etching mask, removes by the described active surface plasma etching process of described wafer the semi-conducting material that described wafer exposes.
19. methods as claimed in claim 2, wherein, the described passive surface providing described film to be included in described wafer arrange nude film junction film.
20. methods as claimed in claim 19, wherein, described film is provided also to comprise the nude film junction film part optionally removing the region be configured in corresponding to the segmentation passage/road on the described active surface of described wafer, wherein handled nude film junction film is used as etching mask, removes by the described passive surface plasma etch process of described wafer the semi-conducting material that described wafer exposes.
CN201510669938.7A 2014-10-13 2015-10-13 Method for cutting semiconductor wafer Active CN105514038B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462062967P 2014-10-13 2014-10-13
US62/062,967 2014-10-13

Publications (2)

Publication Number Publication Date
CN105514038A true CN105514038A (en) 2016-04-20
CN105514038B CN105514038B (en) 2020-08-11

Family

ID=55655953

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510669938.7A Active CN105514038B (en) 2014-10-13 2015-10-13 Method for cutting semiconductor wafer

Country Status (4)

Country Link
US (2) US9570314B2 (en)
CN (1) CN105514038B (en)
SG (2) SG10201508477VA (en)
TW (1) TWI664668B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111433597A (en) * 2017-11-16 2020-07-17 奥斯通医疗有限公司 Method of manufacturing ion transfer filter
CN112992760A (en) * 2019-12-12 2021-06-18 Spts科技有限公司 Semiconductor wafer cutting process

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150147850A1 (en) * 2013-11-25 2015-05-28 Infineon Technologies Ag Methods for processing a semiconductor workpiece
US9570314B2 (en) * 2014-10-13 2017-02-14 UTAC Headquarters Pte. Ltd. Methods for singulating semiconductor wafer
JP6467592B2 (en) * 2016-02-04 2019-02-13 パナソニックＩｐマネジメント株式会社 Device chip manufacturing method, electronic component mounting structure manufacturing method, and electronic component mounting structure
DE102016109693B4 (en) 2016-05-25 2022-10-27 Infineon Technologies Ag Process for separating semiconductor dies from a semiconductor substrate and semiconductor substrate arrangement
US9905466B2 (en) * 2016-06-28 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer partitioning method and device formed
GB201611652D0 (en) * 2016-07-04 2016-08-17 Spts Technologies Ltd Method of detecting a condition
CN106098535A (en) * 2016-07-12 2016-11-09 武汉新芯集成电路制造有限公司 Bonding wafer manufacturing method
JP6735653B2 (en) * 2016-10-24 2020-08-05 株式会社ディスコ Wafer division method
DE102017212858A1 (en) * 2017-07-26 2019-01-31 Disco Corporation Method for processing a substrate
JP6994646B2 (en) * 2018-01-17 2022-01-14 パナソニックＩｐマネジメント株式会社 Method of manufacturing element chips
US10916474B2 (en) * 2018-06-25 2021-02-09 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
CN110634796A (en) * 2018-06-25 2019-12-31 半导体元件工业有限责任公司 Method for processing electronic die and semiconductor wafer and singulation method of die
KR20200034503A (en) * 2018-09-21 2020-03-31 삼성전자주식회사 Method of sawing substrate and method of singulating semiconductor chips
JP7139065B2 (en) * 2018-12-03 2022-09-20 株式会社ディスコ Wafer processing method
JP7210100B2 (en) * 2018-12-03 2023-01-23 株式会社ディスコ Wafer processing method
TWI689980B (en) * 2019-03-20 2020-04-01 華邦電子股份有限公司 Method of wafer dicing and die
WO2022015245A1 (en) * 2020-07-15 2022-01-20 Pep Innovation Pte. Ltd. Semiconductor device with buffer layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW559876B (en) * 2001-10-19 2003-11-01 Applied Materials Inc Method and apparatus for dicing a semiconductor wafer
US20130115756A1 (en) * 2011-11-08 2013-05-09 Disco Corporation Processing method for semiconductor wafer having passivation film on the front side thereof
US20130267076A1 (en) * 2012-04-10 2013-10-10 Wei-Sheng Lei Wafer dicing using hybrid multi-step laser scribing process with plasma etch
CN103426721A (en) * 2012-05-24 2013-12-04 英飞凌科技股份有限公司 Method for processing a wafer at unmasked areas and previously masked areas

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4387007B2 (en) 1999-10-26 2009-12-16 株式会社ディスコ Method for dividing semiconductor wafer
US6686225B2 (en) * 2001-07-27 2004-02-03 Texas Instruments Incorporated Method of separating semiconductor dies from a wafer
JP2003257896A (en) 2002-02-28 2003-09-12 Disco Abrasive Syst Ltd Method for dicing semiconductor wafer
US7781310B2 (en) 2007-08-07 2010-08-24 Semiconductor Components Industries, Llc Semiconductor die singulation method
US7989319B2 (en) 2007-08-07 2011-08-02 Semiconductor Components Industries, Llc Semiconductor die singulation method
US8012857B2 (en) 2007-08-07 2011-09-06 Semiconductor Components Industries, Llc Semiconductor die singulation method
KR101094450B1 (en) 2009-06-05 2011-12-15 에스티에스반도체통신 주식회사 Dicing method using a plasma etching
US9252057B2 (en) * 2012-10-17 2016-02-02 Applied Materials, Inc. Laser and plasma etch wafer dicing with partial pre-curing of UV release dicing tape for film frame wafer application
US9041198B2 (en) * 2013-10-22 2015-05-26 Applied Materials, Inc. Maskless hybrid laser scribing and plasma etching wafer dicing process
US8912078B1 (en) * 2014-04-16 2014-12-16 Applied Materials, Inc. Dicing wafers having solder bumps on wafer backside
US9390993B2 (en) * 2014-08-15 2016-07-12 Broadcom Corporation Semiconductor border protection sealant
US9570314B2 (en) * 2014-10-13 2017-02-14 UTAC Headquarters Pte. Ltd. Methods for singulating semiconductor wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW559876B (en) * 2001-10-19 2003-11-01 Applied Materials Inc Method and apparatus for dicing a semiconductor wafer
US20130115756A1 (en) * 2011-11-08 2013-05-09 Disco Corporation Processing method for semiconductor wafer having passivation film on the front side thereof
US20130267076A1 (en) * 2012-04-10 2013-10-10 Wei-Sheng Lei Wafer dicing using hybrid multi-step laser scribing process with plasma etch
CN103426721A (en) * 2012-05-24 2013-12-04 英飞凌科技股份有限公司 Method for processing a wafer at unmasked areas and previously masked areas

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111433597A (en) * 2017-11-16 2020-07-17 奥斯通医疗有限公司 Method of manufacturing ion transfer filter
CN112992760A (en) * 2019-12-12 2021-06-18 Spts科技有限公司 Semiconductor wafer cutting process
CN112992760B (en) * 2019-12-12 2024-01-30 Spts科技有限公司 Semiconductor wafer dicing process

Also Published As

Publication number Publication date
US20160104626A1 (en) 2016-04-14
CN105514038B (en) 2020-08-11
TWI664668B (en) 2019-07-01
SG10201903242QA (en) 2019-05-30
US9570314B2 (en) 2017-02-14
US20170117185A1 (en) 2017-04-27
TW201621996A (en) 2016-06-16
SG10201508477VA (en) 2016-05-30
US9741619B2 (en) 2017-08-22

Similar Documents

Publication Publication Date Title
CN105514038A (en) Methods for dicing semiconductor wafer
CN102163559B (en) Manufacturing method of stack device and device chip process method
TWI529887B (en) Chip package and method for forming the same
US9847258B2 (en) Plasma dicing with blade saw patterned underside mask
TWI512930B (en) Chip package and method for forming the same
TWI575779B (en) Chip package and method for forming the same
US9165890B2 (en) Chip package comprising alignment mark and method for forming the same
US8810012B2 (en) Chip package, method for forming the same, and package wafer
US9972580B2 (en) Semiconductor package and method for fabricating the same
US8643070B2 (en) Chip package and method for forming the same
TW201227937A (en) Image sensor chip package and method for forming the same
US9024437B2 (en) Chip package and method for forming the same
CN111199951B (en) Semiconductor device, manufacturing method thereof and manufacturing method of alignment mark
US20100081257A1 (en) Dice by grind for back surface metallized dies
US20170186712A1 (en) Chip package and method for forming the same
US9064950B2 (en) Fabrication method for a chip package
US9209047B1 (en) Method of producing encapsulated IC devices on a wafer
JP2008120947A (en) Transcription tape and method for producing semiconductor device using the transcription tape
CN113809006A (en) Protecting die corners using polymer deposition techniques
CN113436971A (en) Structure and method for electronic die singulation using alignment structures and multi-step singulation
TWI726279B (en) Semiconductor package device
US8563405B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant