CN102244509B

CN102244509B - Digital timer

Info

Publication number: CN102244509B
Application number: CN 201110184210
Authority: CN
Inventors: 黄华道; 陆华洋
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-07-01
Filing date: 2011-07-01
Publication date: 2012-12-12
Anticipated expiration: 2031-07-01
Also published as: CN102244509A

Abstract

The invention provides a digital timer, comprising a power input end, a timing output end and a common earth terminal. AC (alternating current) voltages loaded on the power input end are subjected to reduction voltage and rectification and then output to an input end of a coding circuit by a collector electrode of a pulse wave shaping crystal triode; coding signals are output to a timing output triode by a diode decoding circuit; active high timing output signals are output to a timing output end from an emitting electrode of the timing output triode; and an output end of a counting chip is connected with a diode at a corresponding position on the decoding circuit in accordance with a binary number at a preset period. The digital timer also comprises a state locking circuit and an automatic reset circuit. The digital timer has the beneficial effects that the pulse signals formed by rectifying and shaping an AC power supply directly are counted, thus the counting accuracy is high and the circuit structure is simple; and a counting chip coding circuit is matched with a diode array decoding circuit to output the counts, thus the optional range of the timing period is wide and the regulation is convenient.

Description

Digital clock

Technical field

The present invention relates to a kind of digital clock, be specifically related to a kind of digital clock that cooperates counting through coding chip and diode decoding array.

Background technology

At present, electrical equipment such as some earth leakage protective sockets are provided with regularly power cutoff mechanism for saving electric energy, when predetermined period arrives, cut off the electricity supply or the detection of the creepage protection function of timing is set.There is complex structure in existing timer or cost is too high or timing cycle can not be adjusted or adjustment process defective such as complicacy too, thereby designs a kind of timer simple in structure, with low cost and become the urgent task that low-voltage electrical apparatus is made the field.

Summary of the invention

To above-mentioned technical problem, the present invention provides a kind of digital clock.

The technical scheme that realizes the object of the invention is:

Digital clock; Comprise power input Vcc, timing output OUT and common ground end GND; The alternating voltage that is carried in power input Vcc exports the coding circuit input of being made up of a slice counting chip at least

to through step-down, rectification through pulse waveform shaper transistor V1 collector electrode; The counting chip code signal exports regularly output triode V2 to through binary system all-key diode decoding circuit, and regularly output triode V2 emitter is to the effective timing output signal of timing output OUT output high level; The counting chip output links to each other according to the diode on the corresponding position with binary system all-key diode decoding circuit of binary number of preset timing cycle; The automatic reset circuit that state lock-in circuit that said digital clock starts when also being included in timing output OUT output timing output signal and power input Vcc make digital clock reset and count automatically when regaining the power supply input; Said state lock-in circuit comprises state locking triode V3; State locking triode V3 base stage links to each other through the emitter of resistance R 8 with timing output triode V2; State locking triode V3 collector electrode links to each other with pulse waveform shaper transistor V1 collector electrode; When regularly the emitter of output triode V2 is exported high level, state locking triode V3 collector electrode saturation conduction.

Further, said power input Vcc links to each other with halfwave rectifier diode D4 anode through dropping resistor R1, the dropping resistor R2 of series connection, and halfwave rectifier diode D4 negative electrode links to each other with common ground end GND through filter capacitor C1.

Further, said pulse waveform shaper transistor V1 base stage links to each other with power input Vcc through current-limiting resistance R3, resistance R 1; Emitter links to each other with the common ground end; Collector electrode links to each other with the first counting chip input in two counting chips, and collector electrode also provides DC power supply through a dropping resistor R4 for all the other active elements.

Further, be connected with diode D1, the D2 of pair of series between the base stage of said pulse waveform shaper transistor V1 and the emitter, this is to diode parallel connection one resistance R 5.

Further; Said pulse waveform shaper transistor V1 collector electrode provides the tap of DC power supply to link to each other with the common ground end through a voltage stabilizing didoe D3; Voltage stabilizing didoe D3 negative electrode links to each other with triode V1 collector electrode through resistance R 4, and voltage stabilizing didoe D3 anode links to each other with the common ground end.

Further; Said automatic reset circuit comprises and is series at tap and the capacitor C between the common ground end GND 2 and resistance R 6 that pulse waveform shaper transistor V1 collector electrode provides DC power supply, draws a tap between capacitor C 2 and the resistance R 6 and links to each other with the reset terminal of two counting chips respectively.

Further, said coding circuit is made up of the cascade of at least two CMOS counting chips.

Further; Said binary system all-key diode decoding circuit is made up of the diode connected in parallel array; All diode anodes provide the tap of DC power supply to link to each other through a resistance R 7 with pulse waveform shaper transistor V1 collector electrode; The binary number of corresponding preset timing cycle be that the position end of " 1 " links to each other with the respective diode negative electrode in the counting chip output, and it is unsettled to remain negative electrode position end in the diode array.

Beneficial effect of the present invention mainly shows: directly through the pulse signal that forms after AC power rectification and the shaping is counted, counting precision height and circuit structure are simple; Cooperate counting output through counting chip coding circuit and diode array decoding circuit, the optional scope of timing cycle is big, and is easy to adjust.

Description of drawings

Fig. 1 is a circuit structure diagram of the present invention;

Fig. 2 is the enlarged drawing of diode decoding circuit among Fig. 1;

Fig. 3 is the enlarged drawing of counting chip coding circuit among Fig. 1;

Fig. 4 is the oscillogram of TP1 position among Fig. 1;

Fig. 5 is the oscillogram of TP2 position among Fig. 1;

Fig. 6 is the oscillogram of TP3 position among Fig. 1.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the present invention is done and to describe in further detail:

Referring to figs. 1 through Fig. 3; Digital clock; Comprise power input Vcc, timing output OUT and common ground end GND; The alternating voltage that is carried in power input Vcc exports the coding circuit input of being made up of the counting chip of a slice counting chip or two and above cascade

to through step-down, rectification through pulse waveform shaper transistor V1 collector electrode; The counting chip code signal exports regularly output triode V2 to through binary system all-key diode decoding circuit, and regularly output triode V2 emitter is to the effective timing output signal of timing output OUT output high level; The counting chip output links to each other according to the diode on the corresponding position with binary system all-key diode decoding circuit of binary number of preset timing cycle; The automatic reset circuit that state lock-in circuit that digital clock starts when also being included in timing output OUT output timing output signal and power input Vcc make digital clock reset and count automatically when regaining the power supply input.

Power input Vcc links to each other with halfwave rectifier diode D4 anode through dropping resistor R1, the dropping resistor R2 of series connection, and halfwave rectifier diode D4 negative electrode links to each other with common ground end GND through filter capacitor C1.

Pulse waveform shaper transistor V1 base stage links to each other with power input Vcc through current-limiting resistance R3, resistance R 1; Emitter links to each other with the common ground end; Collector electrode links to each other with the first counting chip input in two counting chips, and collector electrode also provides DC power supply through a dropping resistor R4 for all the other active elements.The collector electrode of transistor V1 is exported positive square-wave pulse (TP3) when the negative half period of alternating current, its frequency equals the mains frequency of power input Vcc alternating current, and the timing accuracy of this timer depends on the stability of mains frequency.Positive square-wave pulse is added to the pulse input end

of counting chip IC1; Through Q1, Q4, Q5 ..., Q12, Q13, Q14 ..., Q24, Q25, Q26, Q27, Q28 each output; The code that selection needs is connected with diode decoding; All are during with the equal conducting of diode that the counting chip output links to each other; Regularly output triode V2 exports high level, and timing output OUT also exports high level.The waveform of the crux point TP1 of pulse waveform shaper circuit, TP2, TP3 is seen Fig. 5, Fig. 6, shown in Figure 7.

Be connected with diode D1, the D2 of pair of series between the base stage of pulse waveform shaper transistor V1 and the emitter, this is to diode parallel connection one resistance R 5.Pulse waveform shaper transistor V1 collector electrode provides the tap of DC power supply to link to each other with the common ground end through a voltage stabilizing didoe D3; Voltage stabilizing didoe D3 negative electrode links to each other with triode V1 collector electrode through resistance R 4, and voltage stabilizing didoe D3 anode links to each other with the common ground end.

The state lock-in circuit comprises state locking triode V3; State locking triode V3 base stage links to each other through the emitter of resistance R 8 with timing output triode V2; State locking triode V3 collector electrode links to each other with pulse waveform shaper transistor V1 collector electrode; When regularly the emitter of output triode V2 is exported high level, state locking triode V3 collector electrode saturation conduction.

Automatic reset circuit comprises and is series at tap and the capacitor C between the common ground end GND 2 and resistance R 6 that pulse waveform shaper transistor V1 collector electrode provides DC power supply, draws a tap between capacitor C 2 and the resistance R 6 and links to each other with the reset terminal of two counting chips respectively.Inserting power supply behind the deenergization once more can automatically reset and count again.

Be to save the timer cost and set comparatively suitable timing cycle (week is preferable), coding circuit is formed by 12 CMOS counting chips of a slice and a slice 14 CMOS counting chips cascade or by two 14 CMOS counting chips cascades.Get 12 counting chips of a slice (model is CD4020BC) and 14 counting chips of a slice (model is CD4040BM) cascade in the present embodiment.

Binary system all-key diode decoding circuit is made up of the diode connected in parallel array; All diode anodes provide the tap of DC power supply to link to each other through a resistance R 7 with pulse waveform shaper transistor V1 collector electrode; The binary number of corresponding preset timing cycle be that the position end of " 1 " links to each other with the respective diode negative electrode in the counting chip output, and it is unsettled to remain negative electrode position end in the diode array.

With timing one all automatic shutoff circuits is example, when power supply 50Hz frequency: umber of pulse=7*24*3600*50 umber of pulse=30240000 (1 1,100 1,101 0,110 1,101 0,000 0000 binary system) umber of pulse in 1 week.

When power supply 60Hz frequency: umber of pulse=7*24*3600*60 umber of pulse=36288000 (10 0,010 1,001 1,011 0,110 0,000 0000 binary system) umber of pulse in 1 week

Maximum pulse numbers that this timer can write down: 67108849 umber of pulses=(11 1,111 1,111 1,111 1,111 1,111 0001 binary system) umber of pulse.The minimum pulse number that can offer an explanation: 16 umber of pulses=(1 0001 binary system) umber of pulse.Timing range when power supply 50Hz frequency: 1 hour=3600 seconds * 50=180000 (101011111100100000 binary system) umber of pulses.Can setting range be regularly promptly from the longest 15.53 days--by 0.32 second.

Timing range when power supply 60Hz frequency: 1 hour=3600 seconds * 60=216000 (110100101111000000 binary system) umber of pulses.Can setting range be regularly from the longest 12.94 days--by 0.2 second.

Though the present invention is through illustrating and describe with reference to preferred embodiment,, those of ordinary skills should understand, and can be not limited to the description of the foregoing description, in the scope of claims, can do the various variations on form and the details.

Claims

1. digital clock; Comprise power input Vcc, timing output OUT and common ground end GND; It is characterized in that: the alternating voltage that is carried in power input Vcc exports the coding circuit input of being made up of a slice counting chip at least

2. digital clock according to claim 1; It is characterized in that: said power input Vcc links to each other with halfwave rectifier diode D4 anode through dropping resistor R1, the dropping resistor R2 of series connection, and halfwave rectifier diode D4 negative electrode links to each other with common ground end GND through filter capacitor C1.

3. digital clock according to claim 1 is characterized in that: said pulse waveform shaper transistor V1 base stage links to each other with power input Vcc through current-limiting resistance R3, resistance R 1; Emitter links to each other with the common ground end; Collector electrode links to each other with the first counting chip input in two counting chips, and collector electrode also provides DC power supply through a dropping resistor R4 for all the other active elements.

4. digital clock according to claim 3 is characterized in that: be connected with diode D1, the D2 of pair of series between the base stage of said pulse waveform shaper transistor V1 and the emitter, this is to diode parallel connection one resistance R 5.

5. digital clock according to claim 3; It is characterized in that: said pulse waveform shaper transistor V1 collector electrode provides the tap of DC power supply to link to each other with the common ground end through a voltage stabilizing didoe D3; Voltage stabilizing didoe D3 negative electrode links to each other with triode V1 collector electrode through resistance R 4, and voltage stabilizing didoe D3 anode links to each other with the common ground end.

6. digital clock according to claim 3; It is characterized in that: said automatic reset circuit comprises and is series at tap and the capacitor C between the common ground end GND 2 and resistance R 6 that pulse waveform shaper transistor V1 collector electrode provides DC power supply, draws a tap between capacitor C 2 and the resistance R 6 and links to each other with the reset terminal of two counting chips respectively.

7. according to each described digital clock of claim 3 to 6, it is characterized in that: said coding circuit is made up of the cascade of at least two CMOS counting chips.

8. digital clock according to claim 7 is characterized in that: said coding circuit is made up of 12 CMOS counting chips of a slice and 14 CMOS counting chips of a slice or two 14 CMOS counting chips cascades.

9. according to each described digital clock of claim 1 to 6; It is characterized in that: said binary system all-key diode decoding circuit is made up of the diode connected in parallel array; All diode anodes provide the tap of DC power supply to link to each other through a resistance R 7 with pulse waveform shaper transistor V1 collector electrode; The binary number of corresponding preset timing cycle be that the position end of " 1 " links to each other with the respective diode negative electrode in the counting chip output, and it is unsettled to remain negative electrode position end in the diode array.