CN102231809B - Electronic multiplying charge coupled device (CCD) sine wave driving method - Google Patents

Abstract

The invention discloses an electronic multiplying charge coupled device (CCD) sine wave driving method. A series of adjustment is performed on a sine wave code stream to obtain relations between phase differences and CCD image data mean values, and an optimal phase difference is determined by a fitted curve to correct an initial sine wave code stream. In the method, rough adjustment and fine adjustment are performed on sine wave phases to obtain a relation curve for the phase differences and the CCD image data mean values, thereby determining the phase difference corresponding to a maximum CCD image data mean value to accurately correct sine waves to obtain an optimized electronic multiplying CCD driving signal and finally fulfill the aims of optimizing system imaging and improving imaging quality; and a direct-digital-synthesizer (DDS)-based digital/analogue hybrid circuit technology is adopted, and the linear amplification of the sine waves is realized by a high frequency high voltage amplification circuit.

Description

A kind of electron multiplication CCD sine wave drive method

Technical field

The present invention relates to a kind of electron multiplication CCD sine wave drive method, belong to electron multiplication CCD low-light level imaging technical field.

Background technology

Electron multiplication CCD is the core devices of low-light level imaging, utilizes the multiplier effect of electron multiplication CCD can get rid of the impact of reading noise, realizes the imaging under the faint light environment, or even the photon counting function.The realization of electron multiplication need high-frequency and high-voltage (the driving signal of frequency 〉=10MHz, voltage 〉=50Vpp), existing driving method has following two kinds:

The first is the square wave driving method, as shown in Figure 1, the low pressure square wave is become square wave driving signal by high-pressure buffer, and signal amplitude has the high voltage supply device to determine.Simultaneously, for guaranteeing the stable of amplitude, the square-wave signal that produces is fed back to sampling/retainer by voltage divider, and control voltage and control together and proofread and correct the high voltage supply device.The advantage of the method is that the phase place that drives signal is easy to adjust, and can satisfy the roughly demand of electron multiplication CCD; Shortcoming is that circuit is complicated, debugging difficulty is large, and square wave driving signal is larger to the burn-in effects of the doubling register of CCD.

The second is the sine wave drive method, as shown in Figure 2, adopt the principle of resonance, under the switch of controlling sequential is controlled, motivate the resonance wave of low pressure in low-pressure side by transformer, the another high-pressure side of transformer produces the sine wave drive signal simultaneously, for guaranteeing the stable of amplitude, also output signal is fed back to the control voltage end by voltage divider, through error integrator, the amplitude of resonance wave is proofreaied and correct.The advantage of the method is that circuit form is simple, energy consumption is little; Shortcoming is that amplitude and phase place are difficult to carry out linearity adjustment and control, and debugging difficulty is large.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of realize linear adjust control, debugging is convenient, circuit simple, controlled optimization system imaging flexibly, improve the electron multiplication CCD sine wave drive method of image quality.

Technical solution of the present invention is: a kind of electron multiplication CCD sine wave drive method, realize by following steps:

The first step produces one group of sinusoidal wave code stream V that is comprised of the normalized value of N point ₀, wherein

I=0,1,2 ... N, N 〉=16;

Second step is with the sinusoidal wave code stream V of first step generation ₀Synchronize with the clock signal Sig1 of electron multiplication CCD after the conversion of laggard line number mould, low-pass filtering and amplification, the sine wave drive signal V that is amplified ₀" ';

The 3rd step is with the sine wave drive signal V that amplifies ₀" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains ₀" ' with the phase difference that drives signal R φ 1

The 4th step, the sine wave drive signal that amplifies is sent in electron multiplication CCD with driving signal R φ 1, obtain ccd image data mean value D _A0

The 5th step is with the sinusoidal wave code stream V of first step generation ₀Carry out the coarse adjustment of phase place, obtain sinusoidal wave code stream V _1jAnd V _2j, wherein

J=1,2;

The 6th step is with the sinusoidal wave code stream V of coarse adjustment _1jAnd V _2jAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified _1j" ' and V _2j" ';

The 7th step is with the sine wave drive signal V that amplifies _1j" ' and V _2j" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains _1j" ' and V _2j" ' with the phase difference that drives signal R φ 1

With

The 8th step is with the sine wave drive signal V that amplifies _1j" ' and V _2j" ' send in electron multiplication CCD with driving signal R φ 1 obtains ccd image data mean value D _A1jAnd D _A2j

The 9th step is with the sinusoidal wave code stream V of first step generation ₀Carry out the fine tuning of phase place, obtain sinusoidal wave code stream V _3mAnd V _4m, wherein

M=1,2 ... M, M 〉=5;

The tenth step is with the sinusoidal wave code stream V of accurate adjustment _3mAnd V _4mAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified _3m" ' and V _4m" ';

The 11 step is with the sine wave drive signal V that amplifies _3m" ' and V _4m" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains _3m" ' and V _4m" ' with the phase difference that drives signal R φ 1

With

The 12 step is with the sine wave drive signal V that amplifies _3m" ' and V _4m" ' send in electron multiplication CCD with driving signal R φ 1 obtains ccd image data mean value D _A3mAnd D _A4m

The 13 step is with the sinusoidal wave code stream V of the 9th step generation _3mAnd V _4mCarry out the coarse adjustment of phase place, obtain sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mj, wherein

The 14 step is with sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mjAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mj

The 15 step is with the sine wave drive signal V that amplifies " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjCompare the sine wave drive signal V that is amplified through the driving signal R φ 1 that overdrive circuit obtains with the clock signal Sig1 of electron multiplication CCD " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjWith the phase difference that drives signal R φ 1

With

The 16 step is with the sine wave drive signal V that amplifies " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjSend in electron multiplication CCD with driving signal R φ 1, obtain ccd image data mean value D _A31m, D _A32mj, D _A41mjAnd D _A42mj

The 17 step is with phase difference

V _31mj, V _32mj, V _41mjAnd V _42mjWith ccd image data mean value D _A0, D _A1j, D _A2j, D _A3m, D _A4m, D _A31m, D _A32mj, D _A41mjAnd D _A42mjCarry out match, obtain the relation curve of phase difference and ccd image data mean value, obtain ccd image data mean value corresponding phase difference when maximum according to phase difference and the relation curve of ccd image data mean value

In the 18 step, go on foot with the 17 the phase difference that obtains

Revise the sinusoidal wave code stream V of the first step ₀, the sinusoidal wave code stream that obtains

Offset of sinusoidal ripple code stream

Carry out sending into after digital-to-analogue conversion, low-pass filtering and amplification and carry out imaging in electron multiplication CCD.

described second, six, ten, amplify in 14 and 18 and adopt the high-frequency and high-voltage amplifying circuit, the high-frequency and high-voltage amplifying circuit comprises resistance R 1, resistance R 2, resistance R a, resistance R F, amplifier A, capacitor C 2 and capacitor C F, in parallel with resistance R 1 after resistance R 2 and capacitor C 2 series connection, in parallel with resistance R F after resistance R a and capacitor C F series connection, the common port of resistance R 1 and resistance R 2 is level and smooth sine wave signal input, the inverting input of amplifier A respectively with the common port of resistance R 1 and capacitor C 2, resistance R a is connected common port and is connected with resistance R F, the positive input end grounding of amplifier A, the output of amplifier A is connected with capacitor C F common port with resistance R F, the sinewave output end of the output of amplifier A for amplifying.

The present invention compared with prior art beneficial effect is:

(1) the present invention carries out coarse adjustment and accurate adjustment by the offset of sinusoidal wave phase, obtain the relation curve of phase difference and ccd image data mean value, thereby determined the phase difference when the ccd image data mean value is maximum, accurately revise by this phase difference offset of sinusoidal ripple, obtain optimized electron multiplication CCD and driven signal, finally reached the purpose of optimization system imaging, raising image quality;

(2) numeral based on DDS, the analog hybrid technology of the present invention's employing, and realize sinusoidal wave linearity amplification by the high-frequency and high-voltage amplifying circuit;

(3) circuit theory of the present invention simple, be easy to realize, the sine wave drive signal is easily adjusted, the convenient electron multiplication CCD that need to repeatedly adjust phase place debugs;

(4) the present invention produce sinusoidal wave amplitude can Linear Control, phase place can linearly be adjusted, amplitude is adjusted step-length mV magnitude (less than 4mV);

(5) the sinusoidal wave amplitude of the present invention's generation can cover 0-50Vpp, and frequency can cover 1MHz-10MHz, has satisfied the driving demand of most electron multiplication CCD, has good versatility and practicality.

Description of drawings

Fig. 1 is existing square wave Driving technique theory diagram;

Fig. 2 is existing sine wave drive know-why block diagram;

Fig. 3 is theory diagram of the present invention;

Fig. 4 is the sinusoidal wave amplifying circuit of high-frequency and high-voltage of the present invention.

Embodiment

The present invention realizes by following steps:

1, produce the sinusoidal wave code stream V of the normalized value composition of one group N point ₀, wherein

I=0,1,2 ... N, N 〉=16.

2, with sinusoidal wave code stream V ₀Synchronize the conversion of laggard line number mould with the clock signal Sig1 of electron multiplication CCD, obtain sinusoidal wave analog signal V ₀'.

3, offset of sinusoidal wave simulation signal V ₀' carry out low-pass filtering to obtain level and smooth sine wave signal V ₀".

4, to level and smooth sine wave signal V ₀" amplify the sine wave drive signal V that is amplified ₀" '.

5, with the sine wave drive signal V that amplifies ₀" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains ₀" ' with the phase difference that drives signal R φ 1

6, the sine wave drive signal that amplifies is sent in electron multiplication CCD with driving signal R φ 1, obtained ccd image data mean value D _A0

The sinusoidal wave code stream V that 7, will initially produce ₀Carry out the coarse adjustment of phase place, obtain sinusoidal wave code stream V _1jAnd V _2j, wherein

J=1,2

8, with the sinusoidal wave code stream V of coarse adjustment _1jAnd V _2jCarry out digital-to-analogue conversion, obtain sinusoidal wave analog signal V _1j' and V _2j'.

9, offset of sinusoidal wave simulation signal V _1j' and V _2j' carry out low-pass filtering to obtain level and smooth sine wave signal V _1j" and V _2j".

10, to level and smooth sine wave signal V _1j" and V _2j" amplify the sine wave drive signal V that is amplified _1j" ' and V _2j" '.

11, with the sine wave drive signal V that amplifies _1j" ' and V _2j" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains _1j" ' and V _2j" ' with the phase difference that drives signal R φ 1

With

12, with the sine wave drive signal V that amplifies _1j" ' and V _2j" ' send in electron multiplication CCD with driving signal R φ 1 obtains ccd image data mean value D _A1jAnd D _A2j

The sinusoidal wave code stream V that 13, will initially produce ₀Carry out the fine tuning of phase place, obtain sinusoidal wave code stream V _3mAnd V _4m, wherein

M=1,2 ... M, M 〉=5.

14, with the sinusoidal wave code stream V of accurate adjustment _3mAnd V _4mCarry out digital-to-analogue conversion, obtain sinusoidal wave analog signal V _3m' and V _4m'.

15, offset of sinusoidal wave simulation signal V _3m' and V _4m' carry out low-pass filtering to obtain level and smooth sine wave signal V _3m" and V _4m".

16, to level and smooth sine wave signal V _3m" and V _4m" amplify the sine wave drive signal V that is amplified _3m" ' and V _4m" '.

17, with the sine wave drive signal V that amplifies _3m" ' and V _4m" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains _3m" ' and V _4m" ' with the phase difference that drives signal R φ 1

With

18, with the sine wave drive signal V that amplifies _3m" ' and V _4m" ' send in electron multiplication CCD with driving signal R φ 1 obtains ccd image data mean value D _A3mAnd D _A4m

19, with the sinusoidal wave code stream V that produces after the phase place fine tuning _3mAnd V _4mCarry out the coarse adjustment of phase place, obtain sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mj, wherein

20, with sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mjAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mj

21, with the sine wave drive signal V that amplifies " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjCompare the sine wave drive signal V that is amplified through the driving signal R φ 1 that overdrive circuit obtains with the clock signal Sig1 of electron multiplication CCD " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjWith the phase difference that drives signal R φ 1

With

22, with the sine wave drive signal V that amplifies " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjSend in electron multiplication CCD with driving signal R φ 1, obtain ccd image data mean value D _A31m, D _A32mj, D _A41mjAnd D _A42mj

23, with phase difference

V _31mj, V _32mj, V _41mjAnd V _42mjWith ccd image data mean value D _A0, D _A1j, D _A2j, D _A3m, D _A4m, D _A31m, D _A32mj, D _A41mjAnd D _A42mjCarry out match, obtain the relation curve of phase difference and ccd image data mean value, obtain ccd image data mean value corresponding phase difference when maximum according to phase difference and the relation curve of ccd image data mean value

24, use phase difference

Revise the initial sinusoidal wave code stream V that produces ₀, the sinusoidal wave code stream that obtains

Offset of sinusoidal ripple code stream

Carry out sending into after digital-to-analogue conversion, low-pass filtering and amplification and carry out imaging in electron multiplication CCD.

The present invention is described in detail below in conjunction with accompanying drawing and instantiation, produces sine wave as example take FPGA, but not as limit.Sinusoidal wave production process as shown in Figure 3, formed by DDS module, DAC D/A converter module, low-pass filtering module and the cascade of high-frequency and high-voltage amplification module, produce sinusoidal wave code stream in the DDS module, be converted to the low pressure stairstepping by the DAC D/A converter module sinusoidal wave, the low-pass filtering module that passes through again low pressure obtains level and smooth sine wave, obtains the sine wave drive signal of high-frequency and high-voltage finally by mistake high frequency high pressure amplifying.

One, code stream produces

In the present invention, the online method of adjusting sinusoidal wave amplitude and phase place is to send instruction code to FPGA, issues the DDS module after the FPGA decoding, carries out online instruction code.

The explanation as an example of 16 point coding flow valuves example (determine precision of the selective basis actual requirement of code stream value number is counted more, sinusoidal wave produce more accurate, but in general 16 count just can satisfy required precision), all the other principles are identical.

If sinusoidal wave frequency is f _sin, DDS module clock adopts the f of 16 times _sin, i.e. f=16*f _sinLike this, can adopt 16 point values to describe a sine waveform, therefore in the code stream value of 16 point values of FPGA storage inside as a sine wave, circulation is sent to the sine wave that the DAC D/A converter module makes it to produce.Code stream is one group of normalized value, is made as V0={V000, V001 ... V015}, its amplitude is 1.Sending out DDS module external reservoir with a range coefficient KA, so, the sinusoidal wave amplitude that obtains at last is

V _pp＝G·K _A

Wherein, G is the cascade gain of DAC D/A converter module, low-pass filtering module and high-frequency and high-voltage amplification module; KA is the coefficient of 14 quantifications, and value is 0-16383.Concerning nearly all electron multiplication CCD, 50Vpp is enough, for the sake of assurance, obtain the sine wave of 50Vpp, and the maximum obtainable sinusoidal wave amplitude of sense circuit system is 60Vpp, can regulate step-length and be

$\mathrm{\Δ}{V}_{\mathrm{pp}}=\frac{60}{16384}=3.7\mathrm{mV}$

This step-length can satisfy the accurate adjustment of CCD gain under height multiplication gain.

In the present invention, phase place be adjusted into the coarse adjustment mode and the fine tuning mode combines.

The coarse adjustment mode is undertaken by the initial transmission data of specifying a group code stream, as code stream V ₀, I=0,1,2 ... N, the value of N is 16 herein, code stream V ₀Initial phase be 0, namely data are from its first value { V ₀₀₀Beginning to circulate sends.The step-length of this mode control phase is

As need time-delay or super previous step-length, just specify from { V ₀₁₅Or { V ₀₀₁Begin the circulation transmission, obtain code stream V ₁₁And V ₂₁,

General coarse adjustment adopts 2 step-lengths to get final product, and 2 step-length adjustment obtain code stream V ₁₂And V ₂₂,

To adjust a step-length as example, concrete numerical value is as shown in table 1,

Table 1

For adjusting more accurately step-length, the present invention carries out accurate adjustment to phase place, adopts many group sinusoidal wave code stream value, i.e. offset of sinusoidal ripple code stream V ₀Carry out the fine tuning of phase place, obtain sinusoidal wave code stream V _3mAnd V _4m, wherein

M=1,2 ... M, M 〉=5.

This example is got M=5, and the M value more arrives, and the result that obtains is more accurate, but in general, M=5 just can satisfy required precision.

Concrete data selected parts are as shown in table 2:

Table 2

In table, code stream V ₀, V ₃₁, V ₃₂, V ₃₃, V ₃₄Initial phase increase successively 4.5 °, being reacted on sine wave is exactly leading 4.5 ° successively.By selecting not code stream on the same group, can realize the phase place adjustment of 4.5 ° of step-lengths, when adjustable range surpasses or during near 22.5 °, need first adopt aforesaid coarse adjustment mode, then carry out fine tuning.If need more accurate phase place adjustment, can suitably increase the group number of code stream.

To the code stream V after the phase place fine tuning _3mAnd V _4mCarry out again a coarse adjustment, obtain sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mj, wherein

The method of concrete coarse adjustment is the same.

From the above, suppose to need to produce the sine wave of 10MHz, need the code stream clock of 160MHz, the clock cycle is 6.25ns, that is to say the time step of coarse adjustment.When adopting 5 group code stream, step-length can be subdivided into 5 parts, i.e. the time step of fine tuning is 6.25ns/5=1.25ns, can satisfy the practical application request of electron multiplication CCD fully.

Two, digital-to-analogue conversion, low-pass filtering

In this example the DAC D/A converter module be at a high speed a digital signal to the modular converter of analog signal, it is converted to step-like sinusoidal wave analog signal to sinusoidal wave code stream.Can select according to sinusoidal wave frequency the operating frequency of DAC device, its operating frequency to be greater than 16 times of sine wave freuqency.Low-pass filtering module is the second order Butterworth LPF, is responsible for the higher harmonic components elimination of stairstepping sine wave analog signal is obtained level and smooth sine wave signal, it-the 3dB cut-off frequency is set as 2 times of sine wave freuqency.Can select as required DAC and low pass filter in concrete reality.

Three, high-frequency and high-voltage amplifies

This example medium-high frequency high pressure amplifying is the high-frequency and high-voltage amplifier with the phasing link, more than it is amplified to 50Vpp to the analog signal of low pressure linearly.as shown in Figure 4, the high-frequency and high-voltage amplification module comprises resistance R 1, resistance R 2, resistance R a, resistance R F, amplifier A, capacitor C 2 and capacitor C F, in parallel with resistance R 1 after resistance R 2 and capacitor C 2 series connection, in parallel with resistance R F after resistance R a and capacitor C F series connection, the common port of resistance R 1 and resistance R 2 is level and smooth sine wave signal input, the inverting input of amplifier A respectively with the common port of resistance R 1 and capacitor C 2, resistance R a is connected common port and is connected with resistance R F, the positive input end grounding of amplifier A, the output of amplifier A is connected with capacitor C F common port with resistance R F, the sinewave output end of the output of amplifier A for amplifying.

When supposing high speed amplifier A (being amplifier A) for ideal operational amplifier, system transter is

Wherein, Z _FAnd Z ₁Respectively the equiva lent impedance of feedback fraction circuit (circuit that resistance R a, capacitor C F and resistance R F form) and the equiva lent impedance of importation circuit (circuit that resistance R 2, capacitor C 2 and resistance R 1 form).Its expression formula is as follows respectively:

$Z_F=\frac{R_F(1+s{R}_a{C}_F)}{1+s(R_F+R_a)C_F}$

$Z_1=\frac{R_1(1+s{R}_2{C}_2)}{1+s(R_2+R_1)C_2}$

With above three formulas, can get

$H\left(s\right)=\frac{R_F(1+s{R}_a{C}_F)\·[1+s(R_1+R_2)C_2]}{R_1[1+s(R_F+R_a)C_F]\·(1+s{R}_2{C}_2)}$

By following formula as can be known: the 1. low-frequency gain G=R of circuit _F/ R ₁, can determine R according to the circuit multiplication factor thus _F, R ₁Relativeness.2. this Circuits System is by 2 zero points and 2 second-order systems that limit consists of, and the frequency at zero point, limit place is as follows:

$f_{z1}=\frac{1}{2\mathrm{\π}(R_2+R_1)C_2},$ $f_{z2}=\frac{1}{2\mathrm{\π}{R}_a{C}_f},$ $f_{p1}=\frac{1}{2\mathrm{\π}(R_F+R_a)C_f},$ $f_{p2}=\frac{1}{2\mathrm{\π}{R}_2{C}_2}.$

Wherein, zero point f _z2＞f _z1, limit f _p2＞f _p1Due to high speed amplifier A and imperfect, especially phase margin is little under high-frequency and high-voltage amplifies, closed-loop characteristic is unstable, easily produce vibration, and the parasitic parameter of circuit printing plate also has considerable influence to the stability of a system, here need repeatedly to test, the zero limit relation of adjustment System to be to proofread and correct phase place, make it larger phase margin, reliable and stable work.According to zero limit relation, can determine R ₁, R ₂, R _F, R _aFour resistance and C ₂, C _FThe design parameter of two electric capacity.

When the selection of high speed amplifier, need the sine wave freuqency concrete according to electron multiplication CCD and the requirement of amplitude to select, at first amplifier is wanted enough large sine waves of the amplitude that can export; Secondly amplifier will have enough large slew rate SR or full power bandwidth f _ull, its relational expression is as follows:

SR＝π·f _full·V _pp

Usually full power bandwidth is larger than sine wave freuqency, can work under sine wave freuqency guaranteeing, when being 10MHz as sine wave, the full power bandwidth that can select amplifier is 15MHz, the amplitude of obtaining is the sine wave of 50Vpp, and its slew rate should be not less than 2355V/ μ s.

Design principle: DDS module, DAC D/A converter module, low-pass filtering module and high-frequency and high-voltage amplification module are linear time invariant systems in the signal passband scope, are linear to the reaction of source signal.And can be easy to produce arbitrary sequence, the sinusoidal wave code stream of amplitude arbitrarily based on the DDS module of FPGA, thereby the amplitude and the phase place that are easy to the offset of sinusoidal ripple are accurately adjusted.With the high-frequency and high-voltage amplification module of phasing link, can make amplifier carry out linearity to the sine wave signal of 10MHz and stably amplify work.

Four, composes curve, obtain optimum phase adjustment amount modified sine wave code stream

The sine wave drive signal of amplification and the clock signal Sig1 of electron multiplication CCD are compared through the driving signal R φ 1 that overdrive circuit obtains, obtain the sine wave drive signal and the phase difference that drives signal R φ 1 of a series of amplifications; And the sine wave drive signal that amplifies is sent in electron multiplication CCD with driving signal R φ 1, obtain with it for a series of ccd image data mean value D _AWith a series of phase differences and ccd image data mean value D _ACarry out match, obtain the relation curve of phase difference and ccd image data mean value, obtain ccd image data mean value corresponding phase difference when maximum according to phase difference and the relation curve of ccd image data mean value (being optimum phase difference).

The optimum phase difference that utilizes composes curve to obtain

Remove modified sine wave code stream V ₀, the sinusoidal wave code stream that obtains

Offset of sinusoidal ripple code stream Carry out sending into after digital-to-analogue conversion, low-pass filtering and amplification and carry out imaging in electron multiplication CCD.

The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.

Claims (2)

1. electron multiplication CCD sine wave drive method is characterized in that realizing by following steps:

The first step produces one group of sinusoidal wave code stream V that is comprised of the normalized value of N point ₀, wherein $V_0=\left\{\sin \frac{2\mathrm{\π}}{N}i\right\},i=\mathrm{0,1,2}...N,N\≥16;$

Second step is with the sinusoidal wave code stream V of first step generation ₀Synchronize with the clock signal Sig1 of electron multiplication CCD after the conversion of laggard line number mould, low-pass filtering and amplification, the sine wave drive signal V that is amplified ₀" ';

The 3rd step is with the sine wave drive signal V that amplifies ₀" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains ₀" ' with the phase difference that drives signal R φ 1

The 4th step, the sine wave drive signal that amplifies is sent in electron multiplication CCD with driving signal R φ 1, obtain ccd image data mean value D _A0

The 5th step is with the sinusoidal wave code stream V of first step generation ₀Carry out the coarse adjustment of phase place, obtain sinusoidal wave code stream V _1jAnd V _2j, wherein $V_{1j}=\left\{\sin (\frac{2\mathrm{\π}}{N}i+\frac{2\mathrm{\π}}{N}j)\right\},$ $V_{2j}=\left\{\sin (\frac{2\mathrm{\π}}{N}i-\frac{2\mathrm{\π}}{N}j)\right\},j=\mathrm{1,2};$

The 6th step is with the sinusoidal wave code stream V of coarse adjustment _1jAnd V _2jAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified _1j" ' and V _2j" ';

The 7th step is with the sine wave drive signal V that amplifies _1j" ' and V _2j" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains _1j" ' and V _2j" ' with the phase difference that drives signal R φ 1

With

The 8th step is with the sine wave drive signal V that amplifies _1j" ' and V _2j" ' send in electron multiplication CCD with driving signal R φ 1 obtains ccd image data mean value D _A1jAnd D _A2j

The 9th step is with the sinusoidal wave code stream V of first step generation ₀Carry out the accurate adjustment of phase place, obtain sinusoidal wave code stream V _3mAnd V _4m, wherein $V_{3m}=\left\{\sin (\frac{2\mathrm{\π}}{N}i+\frac{2\mathrm{\π}}{\mathrm{NM}}m)\right\},$ $V_{4m}=\left\{\sin (\frac{2\mathrm{\π}}{N}i+\frac{2\mathrm{\π}}{\mathrm{NM}}m-\frac{2\mathrm{\π}}{N})\right\},m=\mathrm{1,2},...M,$ M≥5；

The tenth step is with the sinusoidal wave code stream V of accurate adjustment _3mAnd V _4mAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified _3m" ' and V _4m" ';

The 11 step is with the sine wave drive signal V that amplifies _3m" ' and V _4m" ' compare the sine wave drive signal V that is amplified with the clock signal Sig1 of electron multiplication CCD through the driving signal R φ 1 that overdrive circuit obtains _3m" ' and V _4m" ' with the phase difference that drives signal R φ 1

With

The 12 step is with the sine wave drive signal V that amplifies _3m" ' and V _4m" ' send in electron multiplication CCD with driving signal R φ 1 obtains ccd image data mean value D _A3mAnd D _A4m

The 13 step is with the sinusoidal wave code stream V of the 9th step generation _3mAnd V _4mCarry out the coarse adjustment of phase place, obtain sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mj, wherein $V_{31\mathrm{mj}}=\left\{\sin (\frac{2\mathrm{\π}}{N}i+\frac{2\mathrm{\π}}{N}j+\frac{2\mathrm{\π}}{\mathrm{NM}}m)\right\},$ $V_{32\mathrm{mj}}=\left\{\sin (\frac{2\mathrm{\π}}{N}i-\frac{2\mathrm{\π}}{N}j+\frac{2\mathrm{\π}}{\mathrm{NM}}m)\right\},$ $V_{41\mathrm{mj}}=\left\{\sin (\frac{2\mathrm{\π}}{N}i+\frac{2\mathrm{\π}}{N}j-\frac{2\mathrm{\π}}{\mathrm{NM}}m)\right\},$ $V_{42\mathrm{mj}}=\left\{\sin (\frac{2\mathrm{\π}}{N}i-\frac{2\mathrm{\π}}{N}j-\frac{2\mathrm{\π}}{\mathrm{NM}}m)\right\};$

The 14 step is with sinusoidal wave code stream V _31mj, V _32mj, V _41mjAnd V _42mjAfter carrying out digital-to-analogue conversion, low-pass filtering and amplification, the sine wave drive signal V that is amplified " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mj

The 15 step is with the sine wave drive signal V that amplifies " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjCompare the sine wave drive signal V that is amplified through the driving signal R φ 1 that overdrive circuit obtains with the clock signal Sig1 of electron multiplication CCD " ' _31mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjWith the phase difference that drives signal R φ 1 With

The 16 step is with the sine wave drive signal V that amplifies " ' _32mj, V " ' _32mj, V " ' _41mjAnd V " ' _42mjSend in electron multiplication CCD with driving signal R φ 1, obtain ccd image data mean value D _A31m, D _A32mj, D _A41mjAnd D _A42mj

The 17 step is with phase difference

With

With ccd image data mean value D _A0, D _A1j, D _A2j, D _A3m, D _A4m, D _A31m, D _A32mj, D _A41mjAnd D _A42mjCarry out match, obtain the relation curve of phase difference and ccd image data mean value, obtain ccd image data mean value corresponding phase difference when maximum according to phase difference and the relation curve of ccd image data mean value

In the 18 step, go on foot with the 17 the phase difference that obtains

Revise the sinusoidal wave code stream V of the first step ₀, the sinusoidal wave code stream that obtains

Offset of sinusoidal ripple code stream

Carry out sending into after digital-to-analogue conversion, low-pass filtering and amplification and carry out imaging in electron multiplication CCD.

2. a kind of electron multiplication CCD sine wave drive method according to claim 1, it is characterized in that: described second, six, ten, amplify in 14 and 18 steps and adopt the high-frequency and high-voltage amplifying circuit, the high-frequency and high-voltage amplifying circuit comprises resistance R 1, resistance R 2, resistance R a, resistance R F, amplifier A, capacitor C 2 and capacitor C F, in parallel with resistance R 1 after resistance R 2 and capacitor C 2 series connection, in parallel with resistance R F after resistance R a and capacitor C F series connection, the common port of resistance R 1 and resistance R 2 is level and smooth sine wave signal input, the inverting input of amplifier A respectively with the common port of resistance R 1 and capacitor C 2, resistance R a is connected common port and is connected with resistance R F, the positive input end grounding of amplifier A, the output of amplifier A is connected with capacitor C F common port with resistance R F, the sinewave output end of the output of amplifier A for amplifying.

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