CN102214784B - Thermoelectric device and forming method thereof - Google Patents
Thermoelectric device and forming method thereof Download PDFInfo
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- CN102214784B CN102214784B CN201010144277.3A CN201010144277A CN102214784B CN 102214784 B CN102214784 B CN 102214784B CN 201010144277 A CN201010144277 A CN 201010144277A CN 102214784 B CN102214784 B CN 102214784B
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Abstract
The invention provides a thermoelectric device and a forming method thereof. The thermoelectric device comprises a semiconductor substrate, a plurality of isolation structures, n-type thermoelectric structures, p-type thermoelectric structures, a plurality of first conducting electrodes and a plurality of second conducting electrodes, wherein the plurality of isolation structures run through the semiconductor substrate; the n-type thermoelectric structure and the p-type thermoelectric structure are arranged at two sides of each isolation structure respectively; the p-type thermoelectric structures and the n-type thermoelectric structures are arranged at intervals; the plurality of first conducting electrodes are arranged on the upper surface of the semiconductor substrate; the plurality of second conducting electrodes are arranged on the lower surface of the semiconductor substrate; the first conducting electrodes are electrically connected with the adjacent n-type thermoelectric structures and the adjacent p-type thermoelectric structures respectively, and the second conducting electrodes are electrically connected with the adjacent n-type thermoelectric structures and the adjacent p-type thermoelectric structures respectively; and the first conducting electrodes and the second conducting electrodes are used for connecting all the n-type thermoelectric structures with all the p-type thermoelectric structures in series. The thermoelectric device has the advantage of good cooling effect.
Description
Technical field
The present invention relates to the cooling application of integrated circuit (IC) chip, particularly thermoelectric device and forming method thereof.
Background technology
Along with integrated circuit (IC) chip function from strength to strength, its circuit structure comprising is also more and more huger.Correspondingly, the heat producing when integrated circuit (IC) chip is moved also continues to increase.Integrated circuit (IC) chip is overheated will cause its hydraulic performance decline.Therefore, how integrated circuit (IC) chip is carried out to the cooling important topic of paying close attention to now that just becomes.
It is to adopt fan and the fin of heat loss through convection to carry out air-cooled cooling that integrated circuit (IC) chip is carried out to cooling a kind of conventional method.But air-cooled cooling working method can be subject to many restrictions of integrated circuit (IC) chip practical application.For example, in vacuum chamber or clean room etc., air conditions is required under stricter environment, integrated circuit (IC) chip is carried out air-cooled cooling just not too applicable.The another kind of cooling means that prior art also often adopts is liquid cools.It is cooling that liquid cools is often applied to integrated circuit (IC) chip in large-scale or superhuge computer.But liquid cools is because its equipment needed thereby is huge and cost is higher, be not suitable for integrated circuit (IC) chip in portable computer for example cooling yet.
For overcoming air-cooled and defect liquid cools, prior art has been developed a kind of thermoelectric cooling module (thermal electric cooling).Thermoelectric cooling module based on operation principle be Po Er paste (Peltier) effects.In peltier effect, apply direct current at two different storerooms and fail to be convened for lack of a quorum heat is absorbed in the junction of this bi-material.
A kind of thermoelectric cooling module application examples of prior art, as US Patent No. 7022553B2 discloses, can be used in the encapsulating structure of laminated chips (chip-on-chip).Shown in Fig. 1, thermoelectric cooling module 160 comprises the semiconductor material layer 128 of the first metal layer 127, the second metal level 129 and first, second metal interlevel.Semiconductor material layer 128 is the thermocouple that multiple N-types and/or P type semiconductor form.It is upper that thermoelectric cooling module 160 is connected in chip 125A by connecting line 133, its with chip 125A between carry out electricity by insulating barrier 126 and isolate.If the thermocouple that semiconductor material layer 128 forms for P type semiconductor, in the time that thermoelectric cooling module 160 transmits along arrow 170 directions via the electric current of chip 125A acquisition, thermoelectric cooling module 160 absorbs heat to carry out cooling to chip 125A.And in the time that electric current transmits along arrow 172 directions, 160 of thermoelectric cooling modules can absorb heat chip 125A is heated.
But above-mentioned thermoelectric cooling module is by single thermocouple, chip to be carried out coolingly, need connect chip to obtain direct current by extra connecting line 133, the wiring difficulty and the cooling effect that have so just increased encapsulating structure are not good.
Summary of the invention
The invention provides a kind of thermoelectric device, increase the defect of the wiring difficulty of encapsulating structure to overcome prior art thermoelectric cooling module poor effect and need obtain electric current by extra connecting line.
For addressing the above problem, the invention provides a kind of thermoelectric device, comprising: Semiconductor substrate; Run through multiple isolation structures of Semiconductor substrate and lay respectively at N-shaped thermoelectric structure, the p-type thermoelectric structure of isolation structure both sides, and described p-type thermoelectric structure and N-shaped thermoelectricity are spaced; Be positioned at multiple first conductive electrodes of Semiconductor substrate upper surface, be positioned at multiple second conductive electrodes of Semiconductor substrate lower surface; Wherein the first conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, the second conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, and the first conductive electrode and the second conductive electrode are by all N-shaped thermoelectric structures, and p-type thermoelectric structure is connected.
Optionally, the material of described N-shaped thermoelectric structure is N-shaped SiGe, and the material of described p-type thermoelectric structure is p-type SiGe.
Optionally, the material of described N-shaped thermoelectric structure comprises the superlattice of two kinds of N-shaped thermoelectric materials, and the material of described p-type thermoelectric structure comprises the superlattice of two kinds of p-type thermoelectric materials.
Optionally, the material of described two kinds of N-shaped thermoelectric structures comprises N-shaped Si and N-shaped SiGe.
Optionally, the material of described two kinds of p-type thermoelectric structures comprises p-type Si and p-type SiGe.
Optionally, described two kinds of P type thermoelectric materials comprise B
4c and B
9c.
Optionally, described isolation structure material is Al
2o
3, SiO
2, Si
3n
4in any one.
Optionally, described thermoelectric device also comprises the separator that covers described the first conductive electrode or the second conductive electrode.
Optionally, described insulation surface extension has the semiconductor base or the described insulation surface extension that form chip to be cooled to have semiconductor base.
Optionally, described semiconductor base is silicon substrate, SOI substrate, gallium nitride substrate or gallium arsenide substrate.
The present invention also provides a kind of formation method of thermoelectric device, comprising: Semiconductor substrate is provided; Formation runs through multiple isolation structures of described Semiconductor substrate; Form and run through Semiconductor substrate N-shaped thermoelectric structure in isolation structure both sides, p-type thermoelectric structure, and described p-type thermoelectric structure and N-shaped thermoelectricity are spaced; Form multiple the first conductive electrodes at Semiconductor substrate upper surface, the first conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure; Form multiple the second conductive electrodes at Semiconductor substrate lower surface, the second conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, and the first conductive electrode and the second conductive electrode be all N-shaped thermoelectric structures, the series connection of p-type thermoelectric structure.
Optionally, the formation step of isolation structure comprises: form the groove array that runs through described Semiconductor substrate, adopt spacer medium to fill and lead up the groove of groove array.
Optionally, described spacer medium material is Al
2o
3, SiO
2, Si
3n
4in any one.
Optionally, the formation step of described N-shaped thermoelectric structure comprises: form the groove array that runs through described Semiconductor substrate, adopt N-shaped thermoelectric material to fill and lead up the groove of groove array.
Optionally, described N-shaped thermoelectric material is N-shaped SiGe or N-shaped Si.
Optionally, described N-shaped thermoelectric material comprises the superlattice of two kinds of N-shaped thermoelectric materials.
Optionally, in the time that N-shaped thermoelectric material comprises the superlattice of two kinds of N-shaped thermoelectric materials, the superlattice rete of two kinds of N-shaped thermoelectric materials is parallel to trenched side-wall.
Optionally, the formation step of described p-type thermoelectric structure comprises: form the groove array that runs through described Semiconductor substrate, adopt p-type thermoelectric material to fill and lead up the groove of groove array.
Optionally, described p-type thermoelectric material is p-type SiGe, p-type Si, p-type B
4c or p-type B
9c.
Optionally, described p-type thermoelectric material comprises the superlattice of two kinds of p-type thermoelectric materials.
Optionally, in the time that p-type thermoelectric material comprises the superlattice of two kinds of p-type thermoelectric materials, the superlattice rete of two kinds of p-type thermoelectric materials is parallel to trenched side-wall.
Compared with prior art, the present invention has the following advantages: the invention provides a kind of thermoelectric device and forming method thereof, wherein thermoelectric device forms by conventional semiconductor technology, and can realize driving by metal plug, do not need extra connecting line to be connected with integrated circuit (IC) chip, simple in structure; And this thermoelectric device can be placed in chip thermoelectric device cooling effect optimum position, improve the operating efficiency of thermoelectric device, thermoelectric device of the present invention is connected multiple N-shaped thermoelectric structures with p-type thermoelectric structure, further improve refrigeration, and can apply in a flexible way N-shaped thermoelectric structure and p-type thermoelectric structure number, realize cooling or cooling among a small circle on a large scale.Further, the N-shaped thermoelectric structure of thermoelectric device of the present invention and p-type thermoelectric structure have been selected N-shaped superlattice structure and p-type superlattice structure, improve cooling effectiveness.Formation method of the present invention can adopt more excellent technique to form above-mentioned thermoelectric structure.
Brief description of the drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the schematic diagram of a kind of thermoelectric cooling module of prior art;
Fig. 2 is thermoelectric device one embodiment schematic diagram of the present invention;
Fig. 3 is a kind of embodiment schematic diagram that thermoelectric device of the present invention is applied to integrated circuit (IC) chip refrigeration;
Fig. 4 is thermoelectric device formation method one embodiment schematic flow sheet provided by the invention;
Fig. 5 to Figure 16 is thermoelectric device formation method one embodiment process schematic diagram provided by the invention.
Embodiment
A lot of details are set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, in the time that the embodiment of the present invention is described in detail in detail; for ease of explanation; represent that the profile of device architecture can disobey general ratio and do local amplification, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
Can find by the research to prior art thermoelectric cooling module application, prior art, in the time of ic chip package, is attached in integrated circuit (IC) chip to realize cooling to integrated circuit (IC) chip by type thermoelectric cooling module.Thermoelectric cooling module can only be connected with integrated circuit (IC) chip by extra connecting line, obtains and realizes cooling required direct current.So, need to connect chip to obtain direct current by extra connecting line, so just increase the wiring difficulty of encapsulating structure, further, the operation principle of existing thermoelectric cooling module is peltier effect, but in existing thermoelectric cooling module, chip is not located immediately at the side of the thermoelectric cooling module that cooling effect is the strongest, therefore cooling effect is not good yet.
For this reason, the present inventor considers and has occurred now replacing pcb board to carry out the technology of ic chip package with silicon substrate, expected forming thermoelectric device in silicon substrate, and connect thermoelectric device and integrated circuit (IC) chip by the silicon trench of silicon substrate inside, and integrated circuit (IC) chip is positioned at the top of the thermoelectric cooling module that cooling effect is the strongest, the present invention also, by multiple thermoelectric structure series connection, selects thermoelectric structure number flexibly, makes thermoelectric device adaptive faculty provided by the invention strong.
Fig. 2 shows thermoelectric device one embodiment of the present invention, comprising: Semiconductor substrate 100; Run through multiple isolation structures 203 of Semiconductor substrate 100 and lay respectively at N-shaped thermoelectric structure 201, the p-type thermoelectric structure 202 of isolation structure 203 both sides, and described p-type thermoelectric structure 202 is spaced with N-shaped thermoelectric structure 201; Be positioned at multiple first conductive electrodes 140 of Semiconductor substrate 100 upper surfaces, be positioned at multiple second conductive electrodes 170 of Semiconductor substrate 100 lower surfaces; Wherein the first conductive electrode 140 is electrically connected adjacent N-shaped thermoelectric structure 201 and p-type thermoelectric structure 202, the second conductive electrode 170 is electrically connected adjacent N-shaped thermoelectric structure 201 and p-type thermoelectric structure 202, and the first conductive electrode 140 and the second conductive electrode 170 are by all N-shaped thermoelectric structures 201, and p-type thermoelectric structure 202 is connected.
Particularly, described p-type thermoelectric structure 202 can be single coating, two-layer stacked structure or superlattice structure with N-shaped thermoelectric structure 201.
In one embodiment, when p-type thermoelectric structure 202 is single coating with N-shaped thermoelectric structure 201, the material of described N-shaped thermoelectric structure 201 is N-shaped SiGe, N-shaped Si; The material of described p-type thermoelectric structure 202 is p-type SiGe, p-type Si, p-type B
4c or B
9c.
In another embodiment, when p-type thermoelectric structure 202 is double-layer films stacked structure with N-shaped thermoelectric structure 201, the material of described N-shaped thermoelectric structure 201 is N-shaped SiGe, N-shaped Si; The material of described p-type thermoelectric structure 202 is p-type SiGe, p-type Si, p-type B
4c or B
9c, wherein stacked structure film is all perpendicular to Semiconductor substrate 100.
In a preferred embodiment, when p-type thermoelectric structure 202 is superlattice structure with N-shaped thermoelectric structure 201, N-shaped thermoelectric structure 202 is N-shaped Si and N-shaped SiGe superlattice structure; P-type thermoelectric structure 202 is p-type Si and p-type SiGe superlattice structure, or p-type thermoelectric structure 202 is p-type B
4c or B
9the superlattice structure of C, the film of described superlattice structure is all perpendicular to Semiconductor substrate 100, in a preferred embodiment, adopt superlattice structure can improve the cooling effect of thermoelectric device, in order further to obtain preferably cooling effect, described N-shaped Si film, N-shaped SiGe film, p-type Si film, p-type SiGe film, p-type B
4c film and p-type B
9the thickness of C film is less than 100nm.
Still, with reference to figure 2, the material of described isolation structure 203 is Al
2o
3, SiO
2, Si
3n
4in any one, described isolation structure 203 is for will be between p-type thermoelectric structure 202 and N-shaped thermoelectric structure 201 forming electricity isolation.
Particularly, described the first conductive electrode 140 and the second conductive electrode 170 are for multiple p-type thermoelectric structures 202 are connected successively with N-shaped thermoelectric structure 201, and described the first conductive electrode 140 and the second conductive electrode 170 materials are metal material, polysilicon or doped polycrystalline silicon.
In other embodiments, described the first conductive electrode 140 is or/and the second conductive electrode 170 surface coverage have separator (150 or/and 180), have semiconductor base (not shown) in described insulation surface extension, described semiconductor base is silicon substrate, SOI substrate, gallium nitride substrate or gallium arsenide substrate.Described semiconductor base is formed with chip to be cooled or is not formed with chip, and as not being formed with chip in semiconductor base, extension can form chip by existing semiconductor technology behind separator (150 or/and 180) surface.
In other embodiments, described thermoelectric device also comprise run through separator (150 or/and 180) and with described the first conductive electrode 140 or/and the conductive plunger that the second conductive electrode 170 is electrically connected.
Shown in Fig. 3, for thermoelectric device provided by the invention is applied to a kind of execution mode of chip refrigeration.Taking integrated circuit (IC) chip as example, on ic chip package silicon substrate 10 used, there is multiple integrated circuit (IC) chip 20a, 20b, 20c and 20d.In silicon substrate 10 under integrated circuit (IC) chip 20b, 20c, there is thermoelectric device 30a, 31a.Described thermoelectric device 30a, 31a are communicated with related circuit in integrated circuit (IC) chip 20b, 20c by silicon trench 30b, 31b in silicon substrate 10 respectively, the direct current providing to obtain described circuit.
For example, suppose that described multiple integrated circuit (IC) chip comprises logic circuit chip, high-tension circuit chip, field programmable gate array (FPGA) chip and memory chip, wherein logic circuit chip, high-tension circuit chip be owing to can producing amount of heat when the operation, thereby need to be undertaken cooling by thermoelectric device.Now, just can in silicon substrate, thermoelectric device be set respectively the position of counterlogic circuit chip, high-tension circuit chip, and by silicon trench, described two thermoelectric devices be communicated with logic circuit chip, high-tension circuit chip respectively.In the time that described two thermoelectric devices obtain the direct current that logic circuit chip, high-tension circuit chip provide, just can realize cooling to logic circuit chip, high-tension circuit chip.
More particularly, comprise respectively the thermoelectric device control circuit being connected by silicon trench with described thermoelectric device in described logic circuit chip, high-tension circuit chip, described thermoelectric device control circuit is controlled the switch of thermoelectric device based on chip temperature.In one embodiment, described thermoelectric device control circuit comprises temperature sensor and thermoelectric device switching circuit, and the corresponding signal that described thermoelectric device switching circuit provides based on variations in temperature according to temperature sensor is realized the switch control to thermoelectric device.
The explanation that is applied to ic chip package by above-mentioned thermoelectric device can be seen, because thermoelectric device is without being connected with integrated circuit (IC) chip by extra connecting line again, has therefore reduced the wiring difficulty of encapsulating structure.
And known in conjunction with Fig. 2 and Fig. 3, integrated circuit (IC) chip can be arranged on the first conductive electrode 140 or/and the second conductive electrode 170 tops, paste (Peltier) effect from Po Er, applying direct current at two different storerooms fails to be convened for lack of a quorum heat is absorbed in the junction of this bi-material, thermoelectric device cooling effect provided by the invention optimum position is to connect the first conductive electrode 140 of p-type thermoelectric structure 202 and N-shaped thermoelectric structure 201 or/and the second conductive electrode 170 tops, by follow-up integrated circuit (IC) chip preparation or ic chip package, can make integrated circuit (IC) chip be positioned at the strongest position of cooling effect of thermoelectric device, therefore improved cooling effect.
In addition, can also be easy to push away by above explanation, when above-mentioned thermoelectric device also can be applicable to one chip encapsulation, cooling to described chip regional area.Specifically, only need in silicon substrate, need the position of cooled region that thermoelectric device is set by corresponding described chip, just can carry out Local cooling to the described cooled region that needs.
Further, thermoelectric device of the present invention can also by described the first conductive electrode 140 or/and the conductive plunger that the second conductive electrode 170 is electrically connected control described thermoelectric device some work or work completely, thereby make integrated circuit (IC) chip Local cooling or completely cooling, not only control integration circuit chip cooled region flexibly, but also can energy efficient.
The present invention also provides a kind of thermoelectric device formation method, with reference to figure 4, comprises the steps:
Step S11, provides Semiconductor substrate;
Step S12, forms the multiple isolation structures that run through described Semiconductor substrate;
Step S13, forms and runs through Semiconductor substrate N-shaped thermoelectric structure in isolation structure both sides, p-type thermoelectric structure, and described p-type thermoelectric structure and N-shaped thermoelectricity are spaced;
Step S14, forms multiple the first conductive electrodes at Semiconductor substrate upper surface, and the first conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure; Form multiple the second conductive electrodes at Semiconductor substrate lower surface, the second conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, and the first conductive electrode and the second conductive electrode be all N-shaped thermoelectric structures, the series connection of p-type thermoelectric structure.
The formation order that it is pointed out that isolation structure, N-shaped thermoelectric structure and p-type thermoelectric structure in above-mentioned steps can change sequencing with technique change.
Below in conjunction with a specific embodiment, thermoelectric device formation method of the present invention is elaborated.
Fig. 5 is thermoelectric device formation method one embodiment schematic flow sheet provided by the invention, Fig. 6 to Figure 16 is thermoelectric device formation method one embodiment process schematic diagram provided by the invention, below in conjunction with Fig. 5 to Figure 16, thermoelectric device formation method of the present invention is elaborated.
Step S101, provides Semiconductor substrate, and described Semiconductor substrate has first surface and second surface.
With reference to figure 6, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 can be N-shaped silicon substrate, p-type silicon substrate or silicon-on-insulator (SOI), described Semiconductor substrate is generally disc-shaped, there is upper surface and lower surface, here upper surface is the first surface in this step, and lower surface is the second surface in this step.In the present embodiment as an example of silicon-on-insulator (SOI) example exemplary illustration in addition, described Semiconductor substrate 100 comprises silicon substrate 100a, buried oxide layer 100b, top layer silicon 100c; Described buried oxide layer 100b thickness is that 200 dusts are to 3000 dusts.Described Semiconductor substrate 10b can adopt known SOI technology to prepare, such as bonding, note oxygen isolation (SIMOX) etc.In the time that Semiconductor substrate is selected silicon-on-insulator, described first surface and second surface are first surface I and the second surface II of top layer silicon 100c, and corresponding definition equally can be with reference to the definition of Semiconductor substrate 100.
Step S102 forms the first groove array along first surface in described Semiconductor substrate;
With reference to figure 7, described the first groove array 101 is for forming a step of N-shaped thermoelectric structure, and follow-up N-shaped thermoelectric structure is filled in the groove of described the first groove array 101.
Described the first groove array 101 comprises that quantity is the groove (n is natural number) of n, at least comprise 1 groove, do exemplary illustrated with two groove 101a and 101b in the present embodiment, it needs to be noted, in other embodiments, described the first groove array 101 can be 1 groove, 3 grooves, 4 grooves, 7 grooves, 16 grooves ...
It can be plasma etch process that described the first groove array 101 forms technique, specifically comprises: on described Semiconductor substrate 100 first surface I, form photoresist layer (not shown); Adopt exposure technology to transfer on photoresist layer in the figure on the mask plate corresponding with described the first groove array 101, and the photoresist layer after described exposure is developed, form photoetching offset plate figure (not shown); Taking described photoetching offset plate figure as mask, Semiconductor substrate 100 forms the first groove array 101 described in using plasma etching technics etching, and described plasma etch process etch period can be measured in advance the method for etch-stop stop and determine; After etching technics completes, can adopt ashing method to remove photoetching offset plate figure or adopt chemical reagent to remove photoetching offset plate figure.
In the present embodiment, because the Semiconductor substrate 100 adopting is silicon-on-insulators, 101 need of described the first groove array run through top layer silicon 100c, in etching, do not need to adopt etching stopping point methods to determine etch period, but the method that adopts selective plasma etching is directly along the first surface I etching top layer silicon 100c of top layer silicon 100c until expose buried oxide layer 100b, described selective plasma etching can select to silicon etching strong and to silica the etch technological condition without etching effect, form the first groove array 101.
Step S103 forms N-shaped thermoelectric structure in the groove of the first groove array.
With reference to figure 8, in the present embodiment, described N-shaped thermoelectric structure 201 is N-shaped superlattice structure, described N-shaped superlattice structure comprises two kinds of N-shaped super crystal lattice materials, wherein N-shaped superlattice structure comprises at least Si/SiGe membrane structure of one deck N-shaped, and the plane parallel of the sidewall of described N-shaped Si film and SiGe film and the first groove array.
Understand for convenience this step, do exemplary illustrated with the Si/SiGe membrane structure of one deck N-shaped, employing chemical vapor deposition method forms the N-shaped Si film that covers top layer silicon 100c first surface I and fill described groove 101a and 101b; Adopt the N-shaped Si film of photoetching process removal groove 101a and 101b mono-side until expose buried oxide layer 100b; Adopt chemical vapor deposition method to form the N-shaped SiGe film of filling groove 101a and 101b; Adopt flatening process to remove unnecessary N-shaped Si film and N-shaped SiGe until expose top layer silicon 100c surface, form the Si/SiGe structure that comprises N-shaped Si film 110a and N-shaped SiGe film 110b.
It is pointed out that, in order to form effective superlattice structure, the thickness a1 of described N-shaped Si film 110a is less than 100nm, N-shaped SiGe film 110b thickness a2 is less than 100nm.
The Si/SiGe structure of two-layer or two-layer above N-shaped forms technique can form technique with reference to the Si/SiGe structure of one deck N-shaped, adopts multiple etching depositing operation, until form the Si/SiGe structure of two-layer or two-layer above N-shaped.
Certainly, N-shaped thermoelectric structure 201 structures can be also N-shaped SiGe or the N-shaped Si of single coating, it is simple that the N-shaped thermoelectric structure 201 of single structure forms technique, only need in the groove of the first groove array 101, adopt N-shaped SiGe or N-shaped Si to fill and lead up the groove of described the first groove array 101, but adopt the thermoelectric structure refrigeration of superlattice structure better.
Step S104 forms the second groove array in described Semiconductor substrate, and described the second groove array is corresponding alternate with the first groove array.
With reference to figure 9, described the second groove array 103 comprises that quantity is the groove (n is natural number) of n, at least comprise 1 groove, do exemplary illustrated with two groove 103a and 103b in the present embodiment, incorporated by reference to reference to figure 7, described groove 103a is between groove 101a and groove 101b, and groove 101b is between groove 103a and groove 103b.It needs to be noted, in other embodiments, described the second groove array 103 can be 1 groove, 3 grooves, 4 grooves, 7 grooves, 16 grooves ..., but the groove number of described the second groove array 103 should be corresponding with the first groove array 101 groove number, it is identical with the first groove array 101 groove number being specifically as follows, or the first groove array 101 groove number ± 1.
The formation technique of the second groove array 103 can, with reference to the formation technique of the first groove array 101, here repeat no more.
For fear of the process-induced damage N-shaped thermoelectric structure 201 that forms the second groove array, before forming the second groove array technique, can first form the separator that covers Semiconductor substrate first surface and N-shaped thermoelectric structure 201.
Described separator is for the protection of the N-shaped thermoelectric structure 201 having formed, and avoids N-shaped thermoelectric structure 201 with follow-up p-type thermoelectric structure 202 conductings or sustains damage at follow-up deposition plasma etching technics.
Described insolated layer materials is silica or silicon nitride, and the formation technique of described separator is chemical vapor deposition method, and described separator can be removed in the lump in the flatening process of the step of follow-up formation p-type thermoelectric structure 202.
Step S105 forms p-type thermoelectric structure in the groove of the second groove array.
With reference to Figure 10, described p-type thermoelectric structure 202 is p-type superlattice structure, described p-type superlattice structure comprises two kinds of p-type super crystal lattice materials, wherein p-type superlattice structure comprises at least Si/SiGe membrane structure of one deck p-type, and the plane parallel of the sidewall of described p-type Si film and SiGe film and the second groove array 103.
In other embodiment, described p-type superlattice structure can also be p-type B
4c/B
9c membrane structure, same, p-type B
4c film and p-type B
9the plane parallel of the sidewall of C film and the second groove array 103.
The formation technique of p-type thermoelectric structure 202 can be with reference to the formation technique of N-shaped thermoelectric structure 201, that just in the technique of deposition Si and SiGe, deposit is p-type Si film 120a and p-type SiGe film 120b, and the thickness a3 of p-type Si film 120a is less than 100 nanometers, the thickness a4 of p-type SiGe film 120b is less than 100 nanometers.
The superlattice structure of two-layer or two-layer above p-type forms technique can form technique with reference to the Si/SiGe membrane structure of one deck p-type, adopts multiple etching depositing operation, until form the superlattice structure of two-layer or two-layer above p-type.
Certainly, p-type thermoelectric structure 202 structures can be also p-type SiGe, p-type Si, the p-type B of single coating
4c or p-type B
9c, it is simple that the p-type thermoelectric structure 201 of single structure forms technique, only need in the groove of the second groove array 103, adopt N-shaped SiGe or N-shaped Si to fill and lead up the groove of described the second groove array 103, but adopt the thermoelectric structure refrigeration of superlattice structure better.
Step S106 forms isolation structure between N-shaped thermoelectric structure and p-type thermoelectric structure.
With reference to Figure 11, corresponding, described isolation structure 203 comprises multiple isolation structures unit, makes N-shaped thermoelectric structure and p-type thermoelectric structure be positioned at both sides, isolation structure unit.
In the present embodiment, isolation structure unit 203a is between groove 101a and groove 103a, isolation structure unit 203b is between groove 103a and groove 101b, isolation structure unit 203c is between groove 101b and groove 103b, for isolating N-shaped thermoelectric structure 201 and p-type thermoelectric structure 202.
The formation technique of described isolation structure 203 comprises: form photoresist layer (not shown) on described top layer silicon 100c surface; Adopt exposure technology to transfer on photoresist layer in the figure on the mask plate corresponding with described isolation structure 203, and the photoresist layer after described exposure is developed, form photoetching offset plate figure (not shown); Taking described photoetching offset plate figure as mask, using plasma etching technics etching top layer silicon 100c first surface I forms groove (not shown) until expose buried oxide layer 100b; After etching technics completes, can adopt ashing method to remove photoetching offset plate figure or adopt chemical reagent to remove photoetching offset plate figure, adopting chemical vapor deposition method to fill spacer medium in described groove, described spacer medium is preferably Al
2o
3, SiO
2, Si
3n
4; After fill process completes, planarization is removed unnecessary spacer medium until expose top layer silicon 100c.
What here to point out is, the present embodiment is first to form N-shaped thermoelectric structure 201, secondly p-type thermoelectric structure 202, finally form isolation structure 203, but in other embodiments, N-shaped thermoelectric structure 201, secondly p-type thermoelectric structure 202, the priority formation order that finally forms isolation structure 203 does not also affect the normal work of this thermoelectric device.
Step S107, adopt the first conductive electrode that p-type thermoelectric structure in n groove of the N-shaped thermoelectric structure in n groove of the first groove array and the second groove array is connected, and described the first conductive electrode is positioned at the first surface I of top layer silicon 100c.
With reference to Figure 12, described the first conductive electrode 140 is Al, Cu, Au, Ni, Ta or Ag, or is the alloy of Al, Cu, Au, Ni, Ta or Ag, or is polysilicon, or is doped polycrystalline silicon; Described the first conductive electrode 140 is electrically connected p-type thermoelectric structure and p-type thermoelectric structure with the second conductive electrode of follow-up formation, forms cascaded structure.
The formation technique of described the first conductive electrode 140 comprises: adopt chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form layer of conductive film on described top layer silicon 100c surface, form photoresist layer (not shown) on described conductive film surface; Adopt exposure technology to transfer on photoresist layer in the figure on the mask plate corresponding with the first conductive electrode 140, and the photoresist layer after described exposure is developed, form photoetching offset plate figure (not shown); Taking described photoetching offset plate figure as mask, remove conductive film, form the first conductive electrode 140.
In the present embodiment, described the first conductive electrode 140 comprises conductive electrode 140a and conductive electrode 140b, N-shaped thermoelectric structure 201 in described conductive electrode 140a connection groove 101a and the p-type thermoelectric structure 202 in groove 103a, the N-shaped thermoelectric structure 201 in conductive electrode 140b connection groove 101b and the p-type thermoelectric structure 201 in groove 103b.
In the time that the quantity of the first groove array 101 is greater than 2, the first discrete conductive electrode 140 is connected p-type thermoelectric structure 202 in n groove of the N-shaped thermoelectric structure 201 in n groove of the first groove array 101 and the second groove array 103.
Step S108, forms the protective layer that covers described the first conductive electrode and Semiconductor substrate first surface, forms supporting layer at described protective layer.
With reference to Figure 13, described the first protective layer 150 is for the protection of the first conductive electrode and prevent that the first conductive electrode is exposed in air and be oxidized.
The material of described the first protective layer 150 is silica or silicon nitride, and the formation technique of described the first protective layer 150 is chemical vapor deposition method.
Still, with reference to Figure 13, described supporting layer 160 makes Semiconductor substrate 100 breakages for preventing follow-up reduction process.
Described supporting layer 160 is adopted as Si or carborundum, and the formation technique of described supporting layer 160 is chemical vapor deposition method or adopts adhesion process that Si thicker one deck or silicon carbide substrates are adhered on protective layer 150.
In order to save technique; described supporting layer 160 and the first protective layer 150 can be also same coating; adopt primary depositing technique to form; but because supporting layer 160 thickness are thicker; adopt depositing operation to form efficiency lower; more preferably scheme still adopts depositing operation to form the first protective layer 150, then adopts adhesion process to form supporting layer 160.
Step S109, along the second surface attenuate Semiconductor substrate of Semiconductor substrate until expose N-shaped thermoelectric structure and p-type thermoelectric structure.
With reference to Figure 14, described reduction process is chemico-mechanical polishing, along the second surface II attenuate Semiconductor substrate 100 of Semiconductor substrate 100 until expose N-shaped thermoelectric structure 201 and N-shaped thermoelectric structure 202.
In the present embodiment, due to adopt be silicon-on-insulator as Semiconductor substrate, described reduction process is specially removes silicon substrate 100a, buried oxide layer 100b until expose the second surface II of top layer silicon 100c.
Step S110, adopts the second conductive electrode that p-type thermoelectric structure in n groove of the N-shaped thermoelectric structure in n+1 groove of the first groove array and the second groove array is connected.
With reference to Figure 15, in the present embodiment, because the first groove array 101 only includes 2 grooves, described the second conductive electrode 170 only has a conductive electrode, the p-type thermoelectric structure 202 in connection groove 103a and the N-shaped thermoelectric structure 201 in groove 101b.
In the time that the quantity of the first groove array 101 is greater than 2, the second conductive electrode 170 is connected p-type thermoelectric structure 202 in n groove of the N-shaped thermoelectric structure 201 in n+1 groove of the first groove array 101 and the second groove array 103.
First discrete electrodes of the formation technique of described the second conductive electrode in can refer step 109 forms technique, here repeats no more.
From narrating above, the first conductive electrode 140 and the second conductive electrode 170 are by all N-shaped thermoelectric structures, and p-type thermoelectric structure is connected.
Step S111, forms the second protective layer that covers Semiconductor substrate second surface and the second discrete conductive electrode, removes supporting layer.
With reference to Figure 16, described the second protective layer 180 is for the protection of discrete conductive electrode and prevent that discrete conductive electrode is exposed in air and be oxidized.
The material of described the second protective layer 180 is silica or silicon nitride, and the formation technique of described the second protective layer 180 is chemical vapor deposition method.
Still, with reference to Figure 16, the technique of described removal supporting layer 160 is that grinding is removed or chemical reagent removal coherent substance is removed, and forms technique select accordingly removal technique according to supporting layer 160 in step S110.
In another embodiment; the formation step of thermoelectric device is also included in the second protective layer 180 and the first protective layer 150 surfaces form epitaxial loayer; in epitaxial loayer, form and need cooling semiconductor structure, the separator that now the second protective layer 180 and the first protective layer 150 are hot spot device.
In another embodiment, the formation step of thermoelectric device is also included in the Semiconductor substrate that the second protective layer 180 and the first protective layer 150 surface are connected (bonding) and are formed with chip, carries out cooling to described chip.
In another embodiment; the formation step of described thermoelectric device also comprises that formation runs through the metal plug of the second protective layer 180 and the first protective layer 150; one end of described metal plug is electrically connected with the first conductive electrode 140 and the second conductive electrode 170; the other end of described metal plug is electrically connected with voltage device; by metal plug, described thermoelectric device is applied to voltage, drive described thermoelectric device work.
Do exemplary illustrated with a specific embodiment below, in the time that the thermoelectric device of above-described embodiment is applied to chip refrigeration, shown in Fig. 2 and Figure 16, suppose that described integrated circuit (IC) chip 20b, 20c are respectively logic circuit chip and high pressure chip, temperature sensor in thermoelectric device control circuit is wherein PN junction temperature sensor, the PN junction temperature sensor that for example becomes diode to make with base stage short circuit on the collector electrode of triode.Described PN junction temperature sensor has utilized the junction voltage of PN junction can be with the temperature characteristic declining that raises, thereby in the time of variations in temperature, described PN junction temperature sensor can provide different voltage signals.The voltage signal of described thermoelectric device switching circuit based on different realized the switch control to thermoelectric device.For example, in the time that chip temperature is higher, described thermoelectric device absorbs heat to chip by the control of described thermoelectric device control circuit, cooling to realize chip.
The invention provides a kind of thermoelectric device and forming method thereof, wherein thermoelectric device forms by conventional semiconductor technology, and can realize driving by metal plug, does not need extra connecting line to be connected with integrated circuit (IC) chip, simple in structure; And this thermoelectric device can be placed in chip thermoelectric device cooling effect optimum position, improve the operating efficiency of thermoelectric device, thermoelectric device of the present invention is connected multiple N-shaped thermoelectric structures with p-type thermoelectric structure, further improve refrigeration, and can apply in a flexible way N-shaped thermoelectric structure and p-type thermoelectric structure number, realize cooling or cooling among a small circle on a large scale, further, the N-shaped thermoelectric structure of thermoelectric device of the present invention and p-type thermoelectric structure have been selected N-shaped superlattice structure and p-type superlattice structure, improve cooling effectiveness.Formation method of the present invention can adopt more excellent technique to form above-mentioned thermoelectric structure.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (21)
1. a thermoelectric device, is characterized in that, comprising:
For the Semiconductor substrate of integrated circuit (IC) chip, described integrated circuit (IC) chip comprises logic circuit chip and high-tension circuit chip, and described logic circuit chip and high-tension circuit chip are formed in Semiconductor substrate; Described logic circuit chip with in high-tension circuit chip, comprise respectively the thermoelectric device control circuit being connected by silicon trench with described thermoelectric device, the collector electrode that temperature sensor in described thermoelectric device control circuit is triode becomes the PN junction temperature sensor of diode with base stage short circuit, the junction voltage that described PN junction temperature sensor has a PN junction is with the temperature characteristic declining that raises, thereby in the time of variations in temperature, described PN junction temperature sensor is suitable for the voltage signal that provides different;
In Semiconductor substrate, the position of counterlogic circuit chip, high-tension circuit chip arranges respectively described thermoelectric device; Described thermoelectric device comprises: run through multiple isolation structures of Semiconductor substrate and lay respectively at N-shaped thermoelectric structure, the p-type thermoelectric structure of isolation structure both sides, and described p-type thermoelectric structure and N-shaped thermoelectricity are spaced;
Be positioned at multiple first conductive electrodes of Semiconductor substrate upper surface, be positioned at multiple second conductive electrodes of Semiconductor substrate lower surface; Wherein the first conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, the second conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, and the first conductive electrode and the second conductive electrode are by all N-shaped thermoelectric structures, and p-type thermoelectric structure is connected.
By silicon trench, described thermoelectric device is communicated with logic circuit chip and high-tension circuit chip, in the time that thermoelectric device obtains the DC circuit that logic circuit chip and high-tension circuit chip provide, the switching circuit of described thermoelectric device is suitable for based on described PN junction temperature sensor the voltage signal that provides different, carries out cooling to logic circuit chip and high-tension circuit chip.
2. thermoelectric device as claimed in claim 1, is characterized in that, the material of described N-shaped thermoelectric structure is N-shaped SiGe, and the material of described p-type thermoelectric structure is p-type SiGe.
3. thermoelectric device as claimed in claim 1, is characterized in that, the material of described N-shaped thermoelectric structure comprises the superlattice of two kinds of N-shaped thermoelectric materials, and the material of described p-type thermoelectric structure comprises the superlattice of two kinds of p-type thermoelectric materials.
4. thermoelectric device as claimed in claim 3, is characterized in that, the material of described two kinds of N-shaped thermoelectric structures comprises N-shaped Si and N-shaped SiGe.
5. thermoelectric device as claimed in claim 3, is characterized in that, the material of described two kinds of p-type thermoelectric structures comprises p-type Si and p-type SiGe.
6. thermoelectric device as claimed in claim 3, is characterized in that, described two kinds of P type thermoelectric materials comprise B
4c and B
9c.
7. thermoelectric device as claimed in claim 1, is characterized in that, described isolation structure material is Al
2o
3, SiO
2, Si
3n
4in any one.
8. thermoelectric device as claimed in claim 1, is characterized in that, described thermoelectric device also comprises the separator that covers described the first conductive electrode or the second conductive electrode.
9. thermoelectric device as claimed in claim 1, is characterized in that, described insulation surface extension has the semiconductor base or the described insulation surface extension that form chip to be cooled to have semiconductor base.
10. thermoelectric device as claimed in claim 1, is characterized in that, described semiconductor base is silicon substrate, SOI substrate, gallium nitride substrate or gallium arsenide substrate.
The formation method of 11. 1 kinds of thermoelectric devices as claimed in claim 1, is characterized in that, comprising:
Semiconductor substrate is provided;
Formation runs through multiple isolation structures of described Semiconductor substrate;
Form and run through Semiconductor substrate N-shaped thermoelectric structure in isolation structure both sides, p-type thermoelectric structure, and described p-type thermoelectric structure and N-shaped thermoelectricity are spaced;
Form multiple the first conductive electrodes at Semiconductor substrate upper surface, the first conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure; Form multiple the second conductive electrodes at Semiconductor substrate lower surface, the second conductive electrode is electrically connected adjacent N-shaped thermoelectric structure and p-type thermoelectric structure, and the first conductive electrode and the second conductive electrode be all N-shaped thermoelectric structures, the series connection of p-type thermoelectric structure.
The formation method of 12. thermoelectric devices as claimed in claim 11, is characterized in that, the formation of isolation structure
Step comprises: form the groove array that runs through described Semiconductor substrate, adopt spacer medium to fill and lead up the groove of groove array.
The formation method of 13. thermoelectric devices as claimed in claim 12, is characterized in that, described spacer medium material is Al
2o
3, SiO
2, Si
3n
4in any one.
The formation method of 14. thermoelectric devices as claimed in claim 11, is characterized in that, the formation step of described N-shaped thermoelectric structure comprises: form the groove array that runs through described Semiconductor substrate, adopt N-shaped thermoelectric material to fill and lead up the groove of groove array.
The formation method of 15. thermoelectric devices as claimed in claim 14, is characterized in that, described N-shaped thermoelectric material is N-shaped SiGe or N-shaped Si.
The formation method of 16. thermoelectric devices as claimed in claim 14, is characterized in that, described N-shaped thermoelectric material comprises the superlattice of two kinds of N-shaped thermoelectric materials.
The formation method of 17. thermoelectric devices as claimed in claim 16, is characterized in that, in the time that N-shaped thermoelectric material comprises the superlattice of two kinds of N-shaped thermoelectric materials, the superlattice rete of two kinds of N-shaped thermoelectric materials is parallel to trenched side-wall.
The formation method of 18. thermoelectric devices as claimed in claim 11, is characterized in that, the formation step of described p-type thermoelectric structure comprises: form the groove array that runs through described Semiconductor substrate, adopt p-type thermoelectric material to fill and lead up the groove of groove array.
The formation method of 19. thermoelectric devices as claimed in claim 18, is characterized in that, described p-type thermoelectric material is p-type SiGe, p-type Si, p-type B
4c or p-type B
9c.
The formation method of 20. thermoelectric devices as claimed in claim 18, is characterized in that, described p-type thermoelectric material comprises the superlattice of two kinds of p-type thermoelectric materials.
The formation method of 21. thermoelectric devices as claimed in claim 20, is characterized in that, in the time that p-type thermoelectric material comprises the superlattice of two kinds of p-type thermoelectric materials, the superlattice rete of two kinds of p-type thermoelectric materials is parallel to trenched side-wall.
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| JP2014007376A (en) * | 2012-05-30 | 2014-01-16 | Denso Corp | Thermoelectric conversion device |
| CN102856278B (en) * | 2012-09-17 | 2015-08-05 | 华进半导体封装先导技术研发中心有限公司 | Adapter plate structure and manufacture method thereof |
| CN103604521B (en) * | 2013-11-04 | 2016-01-06 | 深圳市彩煌实业发展有限公司 | Temperature-sensitivprobe probe and preparation method thereof |
| JP6767928B2 (en) * | 2017-05-26 | 2020-10-14 | 株式会社Kelk | Thermoelectric transmitter |
| CN110763344B (en) * | 2019-10-30 | 2021-04-09 | 广东先导稀材股份有限公司 | GaN-based photo-thermal detection thin film element |
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| US5897330A (en) * | 1994-05-16 | 1999-04-27 | Citizen Watch Co., Ltd. | Method of manufacturing thermoelectric power generation unit |
| CN1702881A (en) * | 2004-03-25 | 2005-11-30 | 株式会社东芝 | Thermoelectric device |
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