CN102214693B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN102214693B CN102214693B CN 201010260919 CN201010260919A CN102214693B CN 102214693 B CN102214693 B CN 102214693B CN 201010260919 CN201010260919 CN 201010260919 CN 201010260919 A CN201010260919 A CN 201010260919A CN 102214693 B CN102214693 B CN 102214693B
- Authority
- CN
- China
- Prior art keywords
- mentioned
- grid
- semiconductor device
- clearance wall
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device, which comprises a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer. The dielectric constant of the first gate spacer is smaller than the dielectric constant of the second gate spacer. The dielectric constant of gate spacers, that is the capacitive coupling between the LDD regions and the gate, is reduced.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly a kind of in order to reduce the semiconductor device of the capacitance coupling effect between grid and lightly-doped source/drain electrode (LDD) district.
Background technology
Integrated circuit (IC) industry has been gone through fast and has been grown up.The technical development of integrated circuit (IC) material and design has made each integrated circuit more previous generation of circuit from generation to generation little and more complicated.Yet these development can increase the complexity of integrated circuit technology and manufacture method, and in order to realize these technical developments, need the better simply integrated circuit technology of development and manufacture method.
In the process of integrated circuit development; when physical dimension (smallest elements (or live width) that meaning can utilize a technique to make) when dwindling, can increase functional density (functional density) (that is quantity of the interconnect component of each chip area) usually.The technique of this size micro has the advantage that increases process efficiency and reduce cost usually.The technique of this size micro can make for example higher power of low consumpting power components consume of CMOS transistor (hereinafter to be referred as CMOS).Typically, cmos element has a transistor, it utilizes following manner to form, on a silicon substrate, form a grid, and be used in afterwards substrate regions and inject suitable dopant material to form the mode of source area and drain region, form together one source pole district and a drain region in the substrate that is arranged in the grid below.Utilize thin grid oxide layer that grid and source area and drain region are completely cut off.This general structure is combined into a transistor.
Be to promote the effect of helping each other between grid and source area and the drain region, most source area and drain region can not be positioned at grid under.Yet the sub-fraction of source area can be overlapping with grid part, similarly, the sub-fraction of drain region can extend to grid under.The overlapping sub-fraction of above-mentioned source area and drain region and grid part is considered as respectively lightly-doped source/drain electrode (LDD) district.
When lightly-doped source/drain electrode (LDD) district strengthens grid and during the coupling effect of the raceway groove that formed by source area and drain region, grid and lightly-doped source/drain electrode (LDD) also can be responded to generation " edge " capacitance coupling effect between distinguishing.This edge capacitance coupling effect can reduce the transistorized performance that is applied to alternating current (AC).Because in the time of transistorized all size decreases, lightly-doped source/drain electrode (LDD) district and grid part overlapping so far yet change of size, so using ultra-large type integrated circuit (ULSI) when technique is dwindled transistorized size, increased the importance of edge capacitance coupling effect.Therefore, in very little transistor, the undesired edge capacitance coupling effect between grid and lightly-doped source/drain electrode (LDD) district can be exaggerated.
Therefore, in this technical field, need a kind of in order to reduce the semiconductor device of the capacitance coupling effect between grid and lightly-doped source/drain electrode (LDD) district, to overcome the shortcoming of known technology.
Summary of the invention
In view of this, one embodiment of the invention provides a kind of semiconductor device, and above-mentioned semiconductor device comprises a substrate, wherein has the isolated district of a plurality of shallow trenchs and a plurality of source/drain region; One gate stack structure is positioned on the aforesaid substrate, and between above-mentioned source/drain region; One first clearance wall, it has one first dielectric constant, is positioned on the sidewall of above-mentioned gate stack structure, and wherein above-mentioned the first clearance wall has a lateral wall; One second clearance wall, it has one second dielectric constant, is positioned on the above-mentioned lateral wall of above-mentioned the first clearance wall, and wherein above-mentioned the first dielectric constant is less than above-mentioned the second dielectric constant.
Another embodiment of the present invention provides a kind of MOS device, and above-mentioned MOS device comprises the semiconductor substrate, wherein has the isolated district of a plurality of shallow trenchs; One gate stack structure is positioned on the above-mentioned semiconductor substrate, and between the isolated district of above-mentioned shallow trench; A plurality of lightly-doped source/drain regions are arranged in above-mentioned semiconductor substrate; Wherein the edge of above-mentioned gate stack structure aligns in fact in above-mentioned lightly-doped source/drain region; One boron doping clearance wall is positioned on the sidewall of above-mentioned gate stack structure; One protection clearance wall is positioned on the lateral wall of above-mentioned boron doping clearance wall, and wherein above-mentioned protection clearance wall is around above-mentioned boron doping clearance wall.
Another embodiment of the present invention provides a kind of MOS device, and above-mentioned MOS device comprises the semiconductor substrate, wherein has the isolated district of a plurality of shallow trenchs; One gate stack structure is positioned on the above-mentioned semiconductor substrate, and between the isolated district of above-mentioned shallow trench; A plurality of lightly-doped source/drain regions are arranged in above-mentioned semiconductor substrate, and wherein the edge of above-mentioned gate stack structure aligns in fact in above-mentioned lightly-doped source/drain region; A plurality of pad oxide are positioned on the sidewall of above-mentioned gate stack structure; A plurality of boron doping clearance walls are positioned on the lateral wall of above-mentioned pad oxide; A plurality of non-doping clearance walls are positioned on the lateral wall of above-mentioned boron doping clearance wall, and wherein above-mentioned protection clearance wall is respectively around above-mentioned boron doping clearance wall; A plurality of source/drain regions are arranged in above-mentioned semiconductor substrate, and the sidewall of the above-mentioned non-doping clearance wall that aligns in fact respectively.
The present invention can reduce the capacitance coupling effect between grid and lightly-doped source/drain electrode (LDD) district.
Description of drawings
Fig. 1 to Fig. 7 is the process section of the semiconductor device of one embodiment of the invention.
Fig. 8 is the process chart of the semiconductor device of invention one embodiment.
Wherein, description of reference numerals is as follows:
200～method;
202,204,206,208,210,212,214～step;
2～substrate;
The isolated district of 4～shallow trench;
12～gate stack structure;
14～gate dielectric;
16～grid;
20～lightly-doped source/drain region;
22～grid gap wall layer;
22
1～laying;
22
2The～the first gap parietal layer;
24～grid gap wall;
24
1～sark;
24
2The～the first clearance wall;
26～second grid gap parietal layer;
28～second grid clearance wall;
30～source/drain region.
Embodiment
Below describe and be accompanied by the example of description of drawings in detail with each embodiment, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover, the part of each element will be to describe respectively explanation in the accompanying drawing, it should be noted that, not shown or describe element, be the form known to a person of ordinary skill in the art in the affiliated technical field, in addition, the ad hoc fashion that specific embodiment only uses for disclosing the present invention, it is not to limit the present invention.
Please refer to Fig. 1 to Fig. 8, method 200 originates in step 202, and step 202 provides a gate stack structure 12 on a substrate 2.Substrate 2 can comprise bulk silicon.In other embodiments, substrate 2 can comprise block SiGe or other semi-conducting materials.Substrate 2 also can have for example composite construction of silicon-on-insulator (silicon on insulator, SOI).Form the isolated district of a plurality of shallow trenchs (STI region) 4 in substrate 2, the isolated district 4 of above-mentioned shallow trench is usually in order to the active area in the isolated substrate 2.The isolated district 4 of above-mentioned shallow trench can be by silica, silicon nitride, silicon oxynitride, fluorine doped silicon glass (FSG) and/or low-k (low k) dielectric material commonly used.Can be used in the substrate 2 and etch depression, the usual way of then dielectric material being inserted in the above-mentioned depression forms the isolated district 4 of above-mentioned shallow trench.
Patternable gate dielectric 14 and grid 16 are to form gate stack structure 12.The above-mentioned technique that forms gate stack structure 12 can also be included in grid 16 tops and form a hard mask layer (figure does not show).Can utilize depositing operation or other suitable technique to form above-mentioned hard mask layer.Above-mentioned hard mask layer can comprise silicon nitride, silicon oxynitride, carborundum and/or other dielectric materials that is fit to.Can utilize photoetching process to form patterning photoresist layer (figure does not show), with the patterning grid.Above-mentioned photoetching process can comprise rotary coating, soft roasting, exposure, postexposure bake, development of photoresist, infiltration, oven dry and other modes that is fit to.In other embodiments, immersion lithography technique, ion beam write the technique that technique or other are fit to and carry out Patternized technique.Can carry out the first etch process with patterning hard mask layer, and above-mentioned patterning hard mask layer can be used the mask as etching grid dielectric medium 14 and grid 16 (the second etch process).The second etch process can comprise dry ecthing or wet etching process.In addition, the second etch process can have high etching selectivity so that etch process can be parked on the substrate 2.Can utilize and divest or technique that other are suitable removes patterning photoresist layer and hard mask layer.
Refer again to Fig. 1, optionally carry out a decrystallized front injection technology (pre-amorphization implant as shown by arrows, PAI), to reduce admixture channeling effect (dopant channeling effect) and to strengthen the dopant activation effect.In one embodiment, but Implanted Silicon, germanium and/or carbon.In other embodiments, can use for example inert gas of neon, argon, krypton, xenon, radon.The admixture that above-mentioned decrystallized front injection technology can be avoided follow-up doping arrives the degree of depth greater than ideal value by the space between the lattice structure.After decrystallized front injection technology, (polysilicon) grid 16 of at least a portion and (monocrystalline) substrate 2 that comes out can become amorphous state (amorphous state).
Please refer to Fig. 2 and Fig. 8, carry out the step 204 of method 200, in substrate 2, to form lightly-doped source/drain electrode (LDD) district 20.Can be used in and inject a p-type admixture in the p-type metal oxide semiconductor device (PMOS), and the mode of injection one N-shaped admixture forms lightly-doped source/drain electrode (LDD) district 20 in a N-shaped metal oxide semiconductor device (NMOS).Gate stack structure 12 is as a mask, so that gate stack structure 12 each other sidewall that align in fact.Also can be used in and inject a N-shaped admixture in the p-type metal oxide semiconductor device (PMOS), and in a N-shaped metal oxide semiconductor device (NMOS), inject the mode of a p-type admixture, in substrate 2, form ring-type/pocket (halo/pocket) district (figure does not show).
Please refer to Fig. 3 and Fig. 8, carry out the step 206 of method 200, to form a grid gap wall floor 22 in above-mentioned gate stack structure 12 and above-mentioned lightly-doped source/20 tops, drain electrode (LDD) district.In one embodiment, grid gap wall layer 22 can comprise a laying 22
1Be positioned at laying 22
1One first gap parietal layer 22 of top
2For instance, laying 22
1Can comprise silica, silicon oxynitride, silicon nitride, silicon nitride boron (silicon boron nitride) or boron nitride.Laying 22
1Thickness can between
Extremely
Between.For instance, the first gap parietal layer 22
2Can comprise a dielectric layer that wherein has admixture, and for the dielectric layer that does not have admixture, have a lower dielectric constant (k).In one embodiment, the first gap parietal layer 22
2Dielectric constant can be between 4.5 to 5.5.Laying 22
1With the first gap parietal layer 22
2Can have different stress types (compression stress/tensile stress).In one embodiment, the first gap parietal layer 22
2One silicon nitride layer that can comprise the admixture with boron, carbon, fluorine or combinations thereof.Predecessor in order to the depositing operation that forms above-mentioned silicon nitride layer can comprise for example dichlorosilane (SiH
2Cl
2), two silicon ethane (Si
2H
6), silane (SiH
4), chlordene two silicomethane (Si
2Cl
6) or the silicon-containing gas of BTBAS (bis (tertiary-butylamino) silane), and comprise for example ammonia (NH3), nitrogen (N
2), nitric oxide (N
2O) nitrogenous gas.The predecessor with admixture in order to the depositing operation that forms above-mentioned silicon nitride layer can also comprise for example boron chloride (BCl
3), borine (BH
3) or diborane (B
2H
6) boron-containing gas, or comprise for example ethene (C
2H
4) or ethane (C
2H
6) carbonaceous gas.Can set the flow of above-mentioned silicon-containing gas, nitrogenous gas and boron-containing gas or carbonaceous gas respectively between between the 10sccm to 200sccm, between between the 500sccm to 4000sccm and between between the 20sccm to 200sccm, so that the atomic percent of boron or carbon is between 2% to 40%.In another embodiment, the first gap parietal layer 22
2One silicon oxynitride layer that can comprise the admixture with boron, carbon, fluorine or combinations thereof.In another embodiment, the first gap parietal layer 22
2One silicon carbide layer that can comprise the admixture with boron, carbon, fluorine or combinations thereof.For example can utilizing, the conventional process of plasma enhanced chemical vapor deposition method (plasma-enhanced CVD), Low Pressure Chemical Vapor Deposition (low pressure LPCVD), inferior aumospheric pressure cvd method (sub-atmospheric SACVD), atomic layer deposition method (ALD) or similar technique forms the first gap parietal layer 22
2In one embodiment, can utilize original position (in-situ) depositing operation, in the first gap parietal layer 22
2Middle doping admixture.In another embodiment, can utilize deposition and ion implantation technology, in the first gap parietal layer 22
2Middle doping admixture.The technological temperature of above-mentioned depositing operation can be between 200 ℃ to 700 ℃, better can be between 300 ℃ to 500 ℃.The first gap parietal layer 22
2Thickness can between
Extremely
Between, better can between
Extremely
Between.
Please refer to Fig. 4 and Fig. 8, carry out the step 208 of method 200, the above-mentioned grid gap wall layer 22 of patterning is adjacent to the grid gap wall 24 of the sidewall of gate stack structure 12 with formation.Above-mentioned Patternized technique can comprise the technique of wet etching, dry ecthing or combinations thereof.In one embodiment, can utilize the above-mentioned grid gap wall layer 22 of dry etching process patterning.In another embodiment, can more utilize the above-mentioned grid gap wall layer 22 of anisotropy (anisotropic) dry etching process patterning.Can use carbon tetrafluoride (CF
4) or fluoromethane (CH
3F), oxygen (O
2) and the gas of helium (He) carry out laying 22
1Dry etching process.Therefore, laying 22
1With the first gap parietal layer 22
2Remainder branch form respectively sark 24
1With the first clearance wall 24
2
Please refer to Fig. 5 and Fig. 8, carry out the step 210 of method 200, on structure shown in Figure 4, form a second grid gap parietal layer 26.For instance, second grid gap parietal layer 26 is positioned at gate stack structure 12, grid gap wall 24 and substrate 2 tops.Second grid gap parietal layer 26 can be as a protection thing to prevent the first clearance wall 24 under it
2Part is not attacked by follow-up wet etching and/or cleaning procedure.In one embodiment, second grid gap parietal layer 26 can be and not have in fact admixture in a dielectric layer (non-doping dielectric layer) wherein.In another embodiment, second grid gap parietal layer 26 can be the dielectric layer with admixture, and the admixture quantity of above-mentioned second grid gap parietal layer 26 is less than the first clearance wall 24
2Admixture quantity.In another embodiment, second grid gap parietal layer 26 can be the dielectric layer that admixture quantity is less than 3% atomic percent.For instance, second grid gap parietal layer 26 can comprise silicon nitride, silicon oxynitride, carborundum or combinations thereof.The dielectric constant (k) of second grid gap parietal layer 26 is higher than the first clearance wall 24
2Dielectric constant (k), for example can be between 5.0 to 7.8.For example can utilizing, the conventional process of plasma enhanced chemical vapor deposition method (plasma-enhanced CVD), Low Pressure Chemical Vapor Deposition (low pressure LPCVD), inferior aumospheric pressure cvd method (sub-atmospheric SACVD), atomic layer deposition method (ALD) or similar technique forms second grid gap parietal layer 26.Can utilize original position (in-situ) depositing operation or utilize deposition, Implantation and annealing process, admixture mixes in second grid gap parietal layer 26.The technological temperature of above-mentioned depositing operation can be between 200 ℃ to 700 ℃, better can be between 400 ℃ to 600 ℃.The thickness of second grid gap parietal layer 26 can between
Extremely
Between, better can between
Extremely
Between.
Please refer to Fig. 6 and Fig. 8, carry out the step 212 of method 200, the above-mentioned second grid of patterning gap parietal layer 26 is adjacent to the first clearance wall 24 with formation
2The second grid clearance wall 28 of exterior side wall.Above-mentioned Patternized technique can comprise the technique of wet etching, dry ecthing or combinations thereof.In one embodiment, can utilize the above-mentioned second grid of dry etching process patterning gap parietal layer 26.In another embodiment, can more utilize the above-mentioned second grid of anisotropy (anisotropic) dry etching process patterning gap parietal layer 26.Can use carbon tetrafluoride (CF
4) or fluoromethane (CH
3F), oxygen (O
2) and the gas of helium (He) carry out the dry etching process of second grid gap parietal layer 26.In one embodiment, second grid clearance wall 28 is in fact around the first clearance wall 24
2Exterior side wall to prevent the first clearance wall 24
2Be exposed to the chemicals for follow-up wet process.Therefore, second grid clearance wall 28 can be protected the first clearance wall 24
2Do not attacked by above-mentioned chemicals.
Please refer to Fig. 7 and Fig. 8, carry out the step 214 of method 200, can utilize gate stack structure 12, grid gap wall 24 and second grid clearance wall 28 as a mask, formation source/drain region 30 in aforesaid substrate 2.Can utilize Implantation or diffusion technology to form source/drain region 30.
Although the present invention with embodiment openly as above; so it is not to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the protection range that the claim of enclosing defines.
Claims (9)
1. semiconductor device comprises:
One substrate wherein has the isolated district of a plurality of shallow trenchs and a plurality of source/drain region;
One gate stack structure is positioned on this substrate, and between described a plurality of source/drain regions;
One first clearance wall, it has one first dielectric constant, is positioned on the sidewall of this gate stack structure, and wherein this first clearance wall has a lateral wall; And
One second clearance wall, it has one second dielectric constant, be positioned on this lateral wall of this first clearance wall, wherein this first dielectric constant is less than this second dielectric constant, one first impurity that wherein has one first quantity in this first clearance wall, and have one second impurity of one second quantity in this second clearance wall, wherein this first quantity is different from this second quantity.
2. semiconductor device as claimed in claim 1, wherein this first dielectric constant is between 4.5 to 5.5.
3. semiconductor device as claimed in claim 1, wherein this second quantity is less than this first quantity.
4. semiconductor device as claimed in claim 1, wherein this first impurity and this second impurity a kind of material for selecting among the material group who is formed by boron, carbon, fluorine and combinations thereof.
5. semiconductor device as claimed in claim 1, wherein the atomic percent of this first impurity is between 2% to 40%.
6. semiconductor device as claimed in claim 1, wherein the atomic percent of this second impurity is less than 3%.
7. semiconductor device as claimed in claim 1, wherein this first clearance wall is the boron doped nitride, and this second clearance wall is non-doped nitride.
8. semiconductor device as claimed in claim 1, wherein the thickness of this first clearance wall between
Extremely
Between.
9. semiconductor device as claimed in claim 1, wherein the thickness of this second clearance wall between
Extremely
Between.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/757,517 | 2010-04-09 | ||
| US12/757,517 US8299508B2 (en) | 2009-08-07 | 2010-04-09 | CMOS structure with multiple spacers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102214693A CN102214693A (en) | 2011-10-12 |
| CN102214693B true CN102214693B (en) | 2013-05-29 |
Family
ID=44759314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010260919 Active CN102214693B (en) | 2010-04-09 | 2010-08-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102214693B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632943A (en) * | 2012-08-24 | 2014-03-12 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103915341B (en) * | 2013-01-08 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| US8889022B2 (en) * | 2013-03-01 | 2014-11-18 | Globalfoundries Inc. | Methods of forming asymmetric spacers on various structures on integrated circuit products |
| CN104701260B (en) * | 2013-12-04 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN106298527B (en) * | 2015-06-01 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | PMOS transistor and forming method thereof |
| US11380680B2 (en) | 2019-07-12 | 2022-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device for a low-loss antenna switch |
| DE102020113596A1 (en) | 2019-07-12 | 2021-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMI-CONDUCTOR DEVICE FOR A LOW-LOSS ANTENNA SWITCH |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1967871A (en) * | 2005-11-17 | 2007-05-23 | 力旺电子股份有限公司 | Semiconductor device and its manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687861B2 (en) * | 2005-10-12 | 2010-03-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicided regions for NMOS and PMOS devices |
| JP2008103644A (en) * | 2006-10-20 | 2008-05-01 | Toshiba Corp | Semiconductor device and production method thereof |
-
2010
- 2010-08-20 CN CN 201010260919 patent/CN102214693B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1967871A (en) * | 2005-11-17 | 2007-05-23 | 力旺电子股份有限公司 | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102214693A (en) | 2011-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8299508B2 (en) | CMOS structure with multiple spacers | |
| CN102214693B (en) | Semiconductor device | |
| CN100552904C (en) | Semiconductor structure and forming method thereof | |
| US7402496B2 (en) | Complementary metal-oxide-semiconductor device and fabricating method thereof | |
| US9136383B2 (en) | Contact structure of semiconductor device | |
| CN102163618B (en) | Field effect transistor and production method of spacer structure | |
| US8835267B2 (en) | Semiconductor device and fabrication method thereof | |
| US7795107B2 (en) | Method for forming isolation structures | |
| US20080116525A1 (en) | Complementary metal-oxide-semiconductor device | |
| CN101728273B (en) | Semiconductor device and method of fabricating the same | |
| CN102709183B (en) | The method being used for producing the semiconductor devices | |
| US9799750B2 (en) | Semiconductor device and fabrication method thereof | |
| WO2012055198A1 (en) | Semiconductor structure and manufacturing method thereof | |
| CN102087980A (en) | High performance semiconductor device and method of forming the same | |
| CN101661904A (en) | Semiconductor device and method for fabricating same | |
| US9214552B2 (en) | Method for fabricating a strain feature in a gate spacer of a semiconductor device | |
| CN102087979A (en) | High performance semiconductor device and method of forming the same | |
| TW200522348A (en) | Advanced strained-channel technique to improve CMOS performance | |
| CN102292811A (en) | Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions | |
| KR20140055907A (en) | Semiconductor device and fabrication method thereof | |
| WO2012041035A1 (en) | Flash memory device and forming method thereof | |
| CN102157379B (en) | Semiconductor device and manufacturing method thereof | |
| CN102237277B (en) | Semiconductor device and method of forming the same | |
| US8728894B2 (en) | Method for fabricating an NMOS transistor | |
| CN102110609B (en) | High performance semiconductor device and method of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |