CN102214601B - Formation method for dual damascene structure - Google Patents
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- CN102214601B CN102214601B CN201010144234.5A CN201010144234A CN102214601B CN 102214601 B CN102214601 B CN 102214601B CN 201010144234 A CN201010144234 A CN 201010144234A CN 102214601 B CN102214601 B CN 102214601B
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Abstract
The invention provides a formation method for a dual damascene structure. The formation method comprises the following steps: providing a pressed shielding and a semiconductor structure which comprises an interconnection layer, a dielectric layer above the interconnection layer and a sacrificial layer above the dielectric layer; heating the sacrificial layer on the semiconductor structure to soften the sacrificial layer; stamping the sacrificial layer on the semiconductor structure by using the pressed shielding so as to embed a bulge on the semiconductor structure into the sacrificial layer; cooling the sacrificial layer on the semiconductor layer to harden the sacrificial layer; taking out the pressed shielding so as to form a dual damascene structure on the sacrificial layer of the semiconductor layer; etching the semiconductor structure with the dual damascene structure to form a dual damascene structure in the dielectric layer and exposing the bottom of a through hole in the dual damascene structure to the interconnection layer. Thus the damages on the substrate can be reduced and the reliability of the device can be improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of Double-embedded structure forming method.
Background technology
Current semiconductor device processing technology development at full speed, semiconductor device has had deep-submicron structure, comprises the semiconductor element of enormous quantity in integrated circuit.In large scale integrated circuit like this, the high-performance between element, highdensity connection not only interconnect in single interconnection layer, and will between multilayer, interconnect.Therefore, multilayer interconnect structure is provided conventionally, the multilayer interconnect structure that particularly utilizes dual damascene (dual_damascene) technique to form, this technique forms groove (trench) and through hole (via) in dielectric layer, then with electric conducting material for example copper (Cu) fill described groove and through hole.This interconnection structure is used widely in integrated circuit manufacture.
Traditional Double-embedded structure forming method needs at least Twi-lithography and etching, below in conjunction with Fig. 1 to Fig. 4, the Twi-lithography in a kind of traditional Double-embedded structure forming method and the process of etching is described.First carry out photoetching for the first time and etching, step is as follows: as shown in Figure 1, substrate 10 is provided, described substrate 10 comprises Semiconductor substrate 11, be positioned at interconnection layer 12 on substrate, be positioned at the dielectric layer 13 on interconnection layer, and described dielectric layer 13 comprises etching stop layer 13a, interlayer dielectric layer 13b, the barrier layer 13c that stacks gradually arrangement.Then, as shown in Figure 2, in substrate 10, form mask layer 20, then expose and develop, in mask layer 20, form the first opening 30; Continuation is with reference to shown in figure 2, utilizes under the sheltering of this mask layer 20 and carries out etching, forms through hole 40 in substrate 10.Then, as shown in Figure 3, carry out ashing for the first time, remove mask layer 20.Then, carry out the 2nd photoetching and etching, step is as follows: as shown in Figure 4, in substrate 10, form mask layer 50, then expose and develop, in mask layer 50, form the second opening 60, described through hole 40 is arranged in the second opening 60, and the size of the second opening 60 is greater than through hole 40.Then, continue with reference to shown in figure 4, utilize under the sheltering of this mask layer 50 and carry out etching, in substrate, form groove 70.Then, carry out as shown in Figure 5 ashing for the second time, remove mask layer 50.So just in substrate, formed dual-damascene structure.Therefore but said method need to be through twice cineration technics, cineration technics can cause damage to substrate 10, utilizes substrate 10 in the dual-damascene structure that said method forms to sustain damage.
Dual damascene (Damascus) process providing in the Chinese document of title " a kind of process for Damascus " number of patent application " 200810035095.5 " is improved said method, reduce the step of development and etching, but still may have the damage to substrate of cineration technics after etching.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of Double-embedded structure forming method, reduces the damage that substrate is caused.
In order to address the above problem, the invention provides a kind of Double-embedded structure forming method, comprise step:
Semiconductor structure and impression shielding are provided, and semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on interconnection layer, is positioned at the sacrifice layer on dielectric layer, and described impression shielding comprises the projection having with dual-damascene structure complementary shape;
Sacrifice layer on described semiconductor structure is heated, make described sacrifice layer softening;
Utilize described impression shielding to carry out punching press to the sacrifice layer on described semiconductor structure, the projection on described semiconductor structure is embedded in described sacrifice layer;
Sacrifice layer on semiconductor structure is carried out cooling, make the sclerosis of described sacrifice layer;
Described impression shielding is taken out, thereby form dual-damascene structure on the sacrifice layer of described semiconductor structure;
To thering is the semiconductor structure of dual-damascene structure, carry out etching, make in dielectric layer, to form dual-damascene structure, and the via bottoms in described dual-damascene structure exposes interconnection layer.
Preferably, the height of described projection equals the thickness of sacrifice layer.
Preferably, in described also comprising carry out the step of etching to thering is the semiconductor structure of dual-damascene structure after, utilize wet etching to remove described sacrifice layer.
Preferably, described wet-cleaned is utilized the mixed solution of phosphoric acid and hydrofluoric acid.
Preferably, the concentration ratio of described phosphoric acid and hydrofluoric acid is: 4: 5～5: 4.
Preferably, described wet-cleaned is utilized the mixed solution of hydrochloric acid and phosphoric acid.
Preferably, the concentration of described hydrochloric acid and the concentration ratio of phosphoric acid are: 10: 1～10: 3.
Preferably, the material of described sacrifice layer is metal.
Preferably, the material of described sacrifice layer is metallic nickel.
Preferably, the thickness of described sacrifice layer is
Preferably, the fusing point of described sacrifice layer is lower than the fusing point of described impression shielding.
Preferably, the material of described impression shielding is metal.
Preferably, the material of described impression shielding is a kind of or its combination in vanadium, lead, tantalum, niobium, zirconium and titanium.
Preferably, described impression shielding comprises substrate and is positioned at the projection on substrate, the cylinder on the described projection side of comprising body and the side's of being positioned at body, and described side's body and cylindrical central shaft are perpendicular to described substrate surface.
Preferably, describedly to thering is the semiconductor structure of dual-damascene structure, carry out etching parameters in etch step and be: chlorine 10sccm～50sccm, argon gas 10sccm～100sccm, chamber pressure is 2mTorr～10mTorr, bottom bias voltage is 100V～500V, and power is 500W～1000W.
Compared with prior art, the present invention mainly has the following advantages:
The present invention impresses shielding impression by utilization and in dielectric layer, forms dual-damascene structure in conjunction with the method for etching, thereby avoided utilizing in the prior art two step photoetching and be etched in the method that forms dual-damascene structure in dielectric layer, therefore avoid damage when mask layer is removed in ashing after etch step in prior art, substrate being caused, improved like this reliability of the device of follow-up formation.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately by actual size equal proportion convergent-divergent, do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 to Fig. 5 is a kind of existing Double-embedded structure forming method;
Fig. 6 is the flow chart of Double-embedded structure forming method of the present invention;
Fig. 7 to Figure 11 is formation dual-damascene structure method schematic diagram of the present invention.
Embodiment
From background technology, in the dielectric layer of semiconductor base, make dual-damascene structure in the prior art, conventionally need to be through twice cineration technics, therefore cineration technics can cause damage to substrate, utilizes substrate in the dual-damascene structure that said method forms to sustain damage.
The present inventor is through a large amount of experiments, obtained a kind of Double-embedded structure forming method and comprised step: semiconductor structure and impression shielding are provided, semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on interconnection layer, be positioned at the sacrifice layer on dielectric layer, described impression shielding comprises the projection having with dual-damascene structure complementary shape; Sacrifice layer on described semiconductor structure is heated, make described sacrifice layer softening; Utilize described impression shielding to carry out punching press to the sacrifice layer on described semiconductor structure, the projection on described semiconductor structure is embedded in described sacrifice layer; Sacrifice layer on semiconductor structure is carried out cooling, make the sclerosis of described sacrifice layer; Described impression shielding is taken out, thereby form dual-damascene structure on the sacrifice layer of described semiconductor structure; To thering is the semiconductor structure of dual-damascene structure, carry out etching, make in dielectric layer, to form dual-damascene structure, and the via bottoms in described dual-damascene structure exposes interconnection layer.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, specific implementation of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the profile that represents device architecture can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
Fig. 6 is the flow chart of formation dual-damascene structure of the present invention.As shown in Figure 6, the present invention forms dual-damascene structure method and comprises step:
S10: semiconductor structure and impression shielding are provided, and semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on interconnection layer, is positioned at the sacrifice layer on dielectric layer, described impression shielding comprises the projection having with dual-damascene structure complementary shape;
S20: the sacrifice layer on described semiconductor structure is heated, make described sacrifice layer softening;
S30: utilize described impression shielding to carry out punching press to the sacrifice layer on described semiconductor structure, the projection on described semiconductor structure is embedded in described sacrifice layer;
S40: the sacrifice layer on semiconductor structure is carried out cooling, make the sclerosis of described sacrifice layer;
S50: described impression shielding is taken out, thereby form dual-damascene structure on the sacrifice layer of described semiconductor structure;
S60: carry out etching to thering is the semiconductor structure of dual-damascene structure, make to form dual-damascene structure in dielectric layer, and the via bottoms in described dual-damascene structure exposes interconnection layer.
Fig. 7 to Figure 11 is Double-embedded structure forming method schematic diagram of the present invention, below in conjunction with Fig. 7 to Figure 11, Double-embedded structure forming method one specific embodiment of the present invention is described.
First, with reference to figure 7, carry out step S10, semiconductor structure 100 is provided, described semiconductor structure 100 comprises Semiconductor substrate 105, is positioned at interconnection layer 110, dielectric layer 120 and sacrifice layer 130 on substrate 105.Interconnection layer 110 can form for the electric conducting material of metal or polysilicon, for being electrically connected to.On interconnection layer 110, there is dielectric layer 120; for the interconnection layer 110 of semiconductor structure 100 and the isolation between follow-up other conductive layers that form on semiconductor structure 100; general dielectric layer 120 can be the laminated construction of multilayer; the nitride layer 120a that has for example comprised etching stop layer effect; be positioned at the interlayer dielectric layer 120b on nitride layer 120a, and be arranged in the barrier layer 120c shielding in etching on interlayer dielectric layer.Described interlayer dielectric layer 120b is selected from SiO conventionally
2or the SiO of doping
2uSG (Undoped silicon glass for example, the silex glass that there is no doping), BPSG (Borophosphosilicate glass, the silex glass of boron phosphorus doped), BSG (borosilicate glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.On described dielectric layer 120, there is sacrifice layer 130.As in a specific implementation, the material of described sacrifice layer 130 is metal, and the thickness of sacrifice layer is
for example be specially metallic nickel (nickel), fusing point is at 1456 degrees Celsius, and the thickness of nickel dam is
this thickness can guarantee in sacrifice layer 130, to form dual-damascene structure in follow-up punching press, and this thickness can also and follow-up etch step combine, make the dual-damascene structure in sacrifice layer well to be transferred in dielectric layer.
Impression shielding 200 also will be provided in this step S10, and described impression shielding comprises the projection of shape and dual-damascene structure complementation, general dual-damascene structure have a groove and with groove logical through hole repeatedly.In a specific implementation, the structure of described impression shielding 200 comprises substrate 210, be positioned at the projection 220 on substrate, cylinder 220b on described protruding 220 side of comprising body 220a (comprising cuboid and square) and the side of being positioned at body 220a, the central shaft of described side's body 220a and cylinder 220b is perpendicular to described substrate 210 surfaces.
The formation method of impression shielding 200 can be utilized metal material, for example any one in vanadium, lead (vanadium), tantalum (tantalum), niobium (niobium), zirconium (zirconium) and titanium (titanium) and combination thereof, under molten condition, in grinding tool, once-cast forms, also can utilize ground floor substrate 210 is first provided, then on ground floor substrate 210, utilize physical vapor deposition to form the second layer, through over etching, the second layer is formed and the square body 220a of groove complementation; Then on the second layer after etching, utilize physical vapor deposition to form the 3rd layer, then utilize etching by the cylinder 220b of the 3rd layer of formation and through hole complementation.So just formed the protruding impression shielding 200 on ground floor with the second layer and the 3rd layer of formation.Certainly those skilled in the art also can, utilize other method to form.Thickness those skilled in the art of described side's body 220a can determine according to the degree of depth of groove in the dual-damascene structure that will form.Thickness those skilled in the art of described cylinder 220b can determine according to through hole in the dual-damascene structure that will form.Except above-mentioned material, also can utilize and be not easy Pressing Deformation, and the other materials of fusing point more than nickel fusing point.The material of described substrate 210 and projection 220 can be the same or different.General, the fusing point of described sacrifice layer 130, like this can be so that can not be out of shape in the shielding of impression described in follow-up punching course 200 lower than the fusing point of described impression shielding 200.
Then, continue with reference to figure 7, carry out step S20, semiconductor structure 100 is heated, make the sacrifice layer 130 on it softening.In a specific implementation, can by semiconductor structure 100 as for making its sacrifice layer 130 reach fusing point in annealing furnace, for example, for the sacrifice layer 130 of nickel material, sacrifice layer 130 need to be heated to 1453 degrees Celsius.Make nickel material be molten state.
Then, with reference to figure 8, carry out step S30, utilize described impression shielding 200, along the upper surface direction perpendicular to described semiconductor structure 100, described semiconductor structure 100 is carried out to punching press, described in during punching press, the cylinder 220b of impression shielding 100 projections 220 is positioned at below, to semiconductor structure 100 punching presses that are positioned at described impression and shield 200 belows, described cylinder 220b subpunch is compressed into into sacrifice layer 130, then square body 220a enters sacrifice layer 130, concrete stamping press those skilled in the art can obtain according to the material of sacrifice layer 130, as long as can guarantee that impression shielding 200 enters sacrifice layer 130, because be molten state after the sacrifice layer 130 that described nickel material forms is heated in step S20, therefore than being easier to, be stamped.
For example can in advance described impression shielding 200 be fixed on a device that can move along pressing direction, then control this device to semiconductor structure 100 direction punching presses, because sacrifice layer 130 is molten state or softer state, thereby sacrifice layer 130 is stamped the projection 220 of shielding 200 and presses to other positions under the effect of stamping press, thereby the projection 220 of impression shielding 200 can embed in described sacrifice layer 130.In this step S30, because the fusing point that impresses shielding 200 is higher than sacrifice layer 130, therefore impression shielding 200 can not be out of shape, and has kept well and the bulge-structure of dual-damascene structure complementation.
In a specific implementation, in described impression shielding 200, the edge of ground floor substrate 210 stretches out projection 220 scopes that are positioned at, this marginal portion just can be stuck on the surface of described semiconductor structure 100, make lucky described protruding 220 to embed in sacrifice layer, make manufacture process more accurate, the dual-damascene structure of formation is better.
Then, continue, with reference to figure 8, to carry out step S40, the sacrifice layer 130 on described semiconductor structure 100 is cooling, in a specific implementation, can be by semiconductor structure 100 as among cooling device, or cooling through nature, make described sacrifice layer 130 hardening.
Then, with reference to figure 9, carry out step S40, the projection 220 of impression shielding 200 is taken out from sacrifice layer 130.In a specific implementation, the shielding 200 of described impression is different with the material of sacrifice layer 130, can not merge completely between therefore, shields 200 like this as long as described impression is withdrawn from away from semiconductor structure 100 directions in edge.Thereby just in described sacrifice layer 130, left the shape of described protruding 220 complementations, i.e. a groove 140a and a dual-damascene structure that through hole 140b forms.
In a specific implementation, described protruding 220 height equals the thickness of sacrifice layer 130.Thereby the groove 140a that projection 220 forms and the degree of depth sum of through hole 140b equal the thickness of sacrifice layer 130, and therefore, after step S40, the dual-damascene structure of formation can expose the dielectric layer 120 of through hole 140b bottom.
Then, with reference to Figure 10, carry out step S50, semiconductor structure 100 is carried out to etching, along with the dual-damascene structure (and groove and through hole) in described sacrifice layer 130 of carrying out of etching extends can be from sacrifice layer 130 to dielectric layer 120, thereby make to form dual-damascene structure in dielectric layer 120.
In a specific implementation, described etching parameters is: chlorine 10sccm～50sccm, and argon gas 10sccm～100sccm, chamber pressure is 2mTorr～10mTorr, and bottom bias voltage is 100V～500V, and power is 500W～1000W.Under above-mentioned etching parameters, if sacrifice layer 130 is metallic nickel materials, dielectric layer is SiO
2or the SiO of doping
2the etch rate of dielectric layer 120 can be faster than the etch rate of sacrifice layer 130; through hole 140a position is owing to there is no the protection of sacrifice layer 130 like this; other positions of the speed ratio of etching are fast; when groove 140b position etches into dielectric layer 120; speed can be accelerated, thereby the through hole 150b degree of depth and the groove 150a degree of depth of the dual-damascene structure in the dielectric layer 120 in the end forming are all large than the degree of depth in sacrifice layer 130.
With reference to Figure 11, in another preferred embodiment, after step S50, also comprise and utilize wet etching to remove described sacrifice layer 130.For example the concrete concentration of utilizing is 4: 5～5: 4, the mixed solution of 1: 1 phosphoric acid and hydrofluoric acid for example, or concentration ratio is: 10: 1～10: 3, for example the mixed solution of the hydrochloric acid of 5: 1 and phosphoric acid carried out wet etching.
The present invention impresses shielding impression by utilization and in dielectric layer, forms dual-damascene structure in conjunction with the method for etching, thereby avoided utilizing in the prior art two step photoetching and be etched in the method that forms dual-damascene structure in dielectric layer, therefore avoid damage when mask layer is removed in ashing after etch step in prior art, substrate being caused, improved like this reliability of the device of follow-up formation.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (13)
1. a Double-embedded structure forming method, is characterized in that, comprises step:
Semiconductor structure and impression shielding are provided, and semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on interconnection layer, is positioned at the sacrifice layer on dielectric layer, and described impression shielding comprises the projection having with dual-damascene structure complementary shape;
Sacrifice layer on described semiconductor structure is heated, make described sacrifice layer softening;
Utilize described impression shielding to carry out punching press to the sacrifice layer on described semiconductor structure, the projection on described semiconductor structure is embedded in described sacrifice layer;
Sacrifice layer on semiconductor structure is carried out cooling, make the sclerosis of described sacrifice layer;
Described impression shielding is taken out, thereby form dual-damascene structure on the sacrifice layer of described semiconductor structure;
To thering is sacrifice layer and the dielectric layer of the semiconductor structure of dual-damascene structure, carry out etching simultaneously, along with the dual-damascene structure in described sacrifice layer of carrying out of etching extends simultaneously from sacrifice layer to dielectric layer, make in dielectric layer, to form dual-damascene structure, and the via bottoms in described dual-damascene structure exposes interconnection layer.
2. Double-embedded structure forming method according to claim 1, is characterized in that, the height of described projection equals the thickness of sacrifice layer.
3. Double-embedded structure forming method according to claim 1, is characterized in that, described, to also comprise after having the sacrifice layer of semiconductor structure of dual-damascene structure and step that dielectric layer carries out etching simultaneously, utilizes wet etching to remove described sacrifice layer.
4. Double-embedded structure forming method according to claim 3, is characterized in that, described wet-cleaned is utilized the mixed solution of phosphoric acid and hydrofluoric acid.
5. Double-embedded structure forming method according to claim 3, is characterized in that, described wet-cleaned is utilized the mixed solution of hydrochloric acid and phosphoric acid.
6. Double-embedded structure forming method according to claim 1, is characterized in that, the fusing point of described sacrifice layer is lower than the fusing point of described impression shielding.
7. Double-embedded structure forming method according to claim 1, is characterized in that, the material of described sacrifice layer is metal.
8. Double-embedded structure forming method according to claim 7, is characterized in that, the thickness of described sacrifice layer is
9. Double-embedded structure forming method according to claim 8, is characterized in that, the material of described sacrifice layer is metallic nickel.
10. Double-embedded structure forming method according to claim 9, it is characterized in that, describedly to thering is the sacrifice layer of semiconductor structure of dual-damascene structure and dielectric layer, carry out etching parameters in etch step simultaneously and be: chlorine 10sccm～50sccm, argon gas 10sccm～100sccm, chamber pressure is 2mTorr～10mTorr, bottom bias voltage is 100V～500V, and power is 500W～1000W.
11. Double-embedded structure forming methods according to claim 9, is characterized in that, the material of described impression shielding is metal.
12. Double-embedded structure forming methods according to claim 11, is characterized in that, the material of described impression shielding is a kind of or its combination in vanadium, lead, tantalum, niobium, zirconium and titanium.
13. Double-embedded structure forming methods according to claim 1, it is characterized in that, described impression shielding comprises substrate and is positioned at the projection on substrate, the cylinder on the described projection side of comprising body and the side's of being positioned at body, and described side's body and cylindrical central shaft are perpendicular to described substrate surface.
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| CN1722366A (en) * | 2004-06-01 | 2006-01-18 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN1860605A (en) * | 2003-09-29 | 2006-11-08 | 国际商业机器公司 | Fabrication method |
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| CN1722366A (en) * | 2004-06-01 | 2006-01-18 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
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