CN102214601A - Formation method for dual damascene structure - Google Patents
Formation method for dual damascene structure Download PDFInfo
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- CN102214601A CN102214601A CN2010101442345A CN201010144234A CN102214601A CN 102214601 A CN102214601 A CN 102214601A CN 2010101442345 A CN2010101442345 A CN 2010101442345A CN 201010144234 A CN201010144234 A CN 201010144234A CN 102214601 A CN102214601 A CN 102214601A
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Abstract
The invention provides a formation method for a dual damascene structure. The formation method comprises the following steps: providing a pressed shielding and a semiconductor structure which comprises an interconnection layer, a dielectric layer above the interconnection layer and a sacrificial layer above the dielectric layer; heating the sacrificial layer on the semiconductor structure to soften the sacrificial layer; stamping the sacrificial layer on the semiconductor structure by using the pressed shielding so as to embed a bulge on the semiconductor structure into the sacrificial layer; cooling the sacrificial layer on the semiconductor layer to harden the sacrificial layer; taking out the pressed shielding so as to form a dual damascene structure on the sacrificial layer of the semiconductor layer; etching the semiconductor structure with the dual damascene structure to form a dual damascene structure in the dielectric layer and exposing the bottom of a through hole in the dual damascene structure to the interconnection layer. Thus the damages on the substrate can be reduced and the reliability of the device can be improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of dual-damascene structure formation method.
Background technology
Current semiconductor device processing technology development at full speed, semiconductor device has had the deep-submicron structure, comprises the semiconductor element of enormous quantity in the integrated circuit.In large scale integrated circuit like this, the high-performance between the element, highdensity connection not only interconnect in single interconnection layer, and will interconnect between multilayer.Therefore, multilayer interconnect structure is provided usually, the multilayer interconnect structure that particularly utilizes dual damascene (dual_damascene) technology to form, this technology forms groove (trench) and through hole (via) in dielectric layer, then with electric conducting material for example copper (Cu) described groove of filling and through hole.This interconnection structure is used widely in the integrated circuit manufacturing.
Traditional dual-damascene structure formation method needs Twi-lithography and etching at least, below in conjunction with Fig. 1 to Fig. 4 the Twi-lithography in a kind of traditional dual-damascene structure formation method and the process of etching is described.At first carry out the photoetching first time and etching, step is as follows: as shown in Figure 1, substrate 10 is provided, described substrate 10 comprises Semiconductor substrate 11, be positioned at interconnection layer 12 on the substrate, be positioned at the dielectric layer 13 on the interconnection layer, and described dielectric layer 13 comprises etching stop layer 13a, interlayer dielectric layer 13b, the barrier layer 13c that stacks gradually arrangement.Then, as shown in Figure 2, in substrate 10, form mask layer 20, expose then and develops formation first opening 30 in mask layer 20; Continue with reference to shown in Figure 2, utilize the sheltering of this mask layer 20 to carry out etching down, formation through hole 40 in substrate 10.Then, as shown in Figure 3, carry out the ashing first time, remove mask layer 20.Then, carry out the 2nd photoetching and etching, step is as follows: as shown in Figure 4, in substrate 10, form mask layer 50, expose then and develops formation second opening 60 in mask layer 50, described through hole 40 is arranged in second opening 60, and the size of second opening 60 is greater than through hole 40.Then, continue, utilize the sheltering of this mask layer 50 to carry out etching down, formation groove 70 in substrate with reference to shown in Figure 4.Then, carry out the ashing second time as shown in Figure 5, remove mask layer 50.So just in substrate, formed dual-damascene structure.Therefore but said method need be through twice cineration technics, and cineration technics can cause damage to substrate 10, utilizes that substrate 10 can sustain damage in the dual-damascene structure that said method forms.
Dual damascene (Damascus) process that provides in the Chinese document of title " a kind of process for Damascus " number of patent application " 200810035095.5 " is improved said method, reduced the step of development and etching, but still may exist cineration technics after the etching the damage of substrate.
Summary of the invention
The technical problem that the present invention solves provides a kind of dual-damascene structure formation method, reduces the damage that substrate is caused.
In order to address the above problem, the invention provides a kind of dual-damascene structure formation method, comprise step:
Semiconductor structure and impression shielding are provided, and semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on the interconnection layer, is positioned at the sacrifice layer on the dielectric layer, and described impression shielding comprises the projection that has with the dual-damascene structure complementary shape;
Sacrifice layer on the described semiconductor structure is heated, make described sacrifice layer softening;
Utilize described impression shielding that the sacrifice layer on the described semiconductor structure is carried out punching press, make that the projection on the described semiconductor structure embeds in the described sacrifice layer;
Sacrifice layer on the semiconductor structure is cooled off, make described sacrifice layer harden;
Described impression shielding is taken out, thereby on the sacrifice layer of described semiconductor structure, form dual-damascene structure;
Semiconductor structure with dual-damascene structure is carried out etching, make in dielectric layer, to form dual-damascene structure, and the via bottoms in the described dual-damascene structure exposes interconnection layer.
Preferably, the height of described projection equals the thickness of sacrifice layer.
Preferably, utilize wet etching to remove described sacrifice layer in described also comprising after semiconductor structure with dual-damascene structure being carried out the step of etching.
Preferably, described wet-cleaned is utilized the mixed solution of phosphoric acid and hydrofluoric acid.
Preferably, the concentration ratio of described phosphoric acid and hydrofluoric acid is: 4: 5～5: 4.
Preferably, described wet-cleaned is utilized the mixed solution of hydrochloric acid and phosphoric acid.
Preferably, the concentration of described hydrochloric acid and concentration of phosphoric acid ratio is: 10: 1～10: 3.
Preferably, the material of described sacrifice layer is a metal.
Preferably, the material of described sacrifice layer is a metallic nickel.
Preferably, the thickness of described sacrifice layer is
Preferably, the fusing point of described sacrifice layer is lower than the fusing point of described impression shielding.
Preferably, the material of described impression shielding is a metal.
Preferably, the material of described impression shielding is a kind of or its combination in vanadium, lead, tantalum, niobium, zirconium and the titanium.
Preferably, described impression shielding comprises substrate and the projection that is positioned on the substrate, the cylinder on the described projection side of comprising body and the side's of the being positioned at body, and described side's body and cylindrical central shaft are perpendicular to described substrate surface.
Preferably, describedly semiconductor structure with dual-damascene structure is carried out etching parameters is in the etch step: chlorine 10sccm～50sccm, argon gas 10sccm～100sccm, chamber pressure are 2mTorr～10mTorr, the bottom bias voltage is 100V～500V, and power is 500W～1000W.
Compared with prior art, the present invention mainly has the following advantages:
The present invention forms dual-damascene structure by utilizing impression shielding impression in conjunction with the method for etching in dielectric layer, thereby avoided utilizing in the prior art two step photoetching and be etched in the method that forms dual-damascene structure in the dielectric layer, therefore avoid the damage that when mask layer is removed in ashing after etch step in the prior art substrate caused, improved the reliability of the device of follow-up formation like this.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 to Fig. 5 is a kind of existing dual-damascene structure formation method;
Fig. 6 is the flow chart of dual-damascene structure formation method of the present invention;
Fig. 7 to Figure 11 is a formation dual-damascene structure method schematic diagram of the present invention.
Embodiment
By background technology as can be known, in the dielectric layer at the semiconductor-based end, make dual-damascene structure in the prior art, usually need be through twice cineration technics, therefore cineration technics can cause damage to substrate, utilizes that substrate sustains damage in the dual-damascene structure that said method forms.
The present inventor is through a large amount of experiments, obtained a kind of dual-damascene structure formation method and comprised step: semiconductor structure and impression shielding are provided, semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on the interconnection layer, be positioned at the sacrifice layer on the dielectric layer, described impression shielding comprises the projection that has with the dual-damascene structure complementary shape; Sacrifice layer on the described semiconductor structure is heated, make described sacrifice layer softening; Utilize described impression shielding that the sacrifice layer on the described semiconductor structure is carried out punching press, make that the projection on the described semiconductor structure embeds in the described sacrifice layer; Sacrifice layer on the semiconductor structure is cooled off, make described sacrifice layer harden; Described impression shielding is taken out, thereby on the sacrifice layer of described semiconductor structure, form dual-damascene structure; Semiconductor structure with dual-damascene structure is carried out etching, make in dielectric layer, to form dual-damascene structure, and the via bottoms in the described dual-damascene structure exposes interconnection layer.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, specific implementation of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 6 is the flow chart of formation dual-damascene structure of the present invention.As shown in Figure 6, the present invention forms the dual-damascene structure method and comprises step:
S10: semiconductor structure and impression shielding are provided, and semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on the interconnection layer, is positioned at the sacrifice layer on the dielectric layer, and described impression shielding comprises the projection that has with the dual-damascene structure complementary shape;
S20: the sacrifice layer on the described semiconductor structure is heated, make described sacrifice layer softening;
S30: utilize described impression shielding that the sacrifice layer on the described semiconductor structure is carried out punching press, make that the projection on the described semiconductor structure embeds in the described sacrifice layer;
S40: the sacrifice layer on the semiconductor structure is cooled off, make described sacrifice layer harden;
S50: described impression shielding is taken out, thereby on the sacrifice layer of described semiconductor structure, form dual-damascene structure;
S60: the semiconductor structure with dual-damascene structure is carried out etching, make in dielectric layer, to form dual-damascene structure, and the via bottoms in the described dual-damascene structure exposes interconnection layer.
Fig. 7 to Figure 11 is a dual-damascene structure formation method schematic diagram of the present invention, below in conjunction with Fig. 7 to Figure 11 dual-damascene structure formation method one specific embodiment of the present invention is described.
At first, carry out step S10 with reference to figure 7, semiconductor structure 100 is provided, described semiconductor structure 100 comprises Semiconductor substrate 105, is positioned at interconnection layer 110, dielectric layer 120 and sacrifice layer 130 on the substrate 105.Interconnection layer 110 can form for the electric conducting material of metal or polysilicon, is used to be electrically connected.On interconnection layer 110, has dielectric layer 120; be used for the interconnection layer 110 and the follow-up isolation between other conductive layers that form on the semiconductor structure 100 of semiconductor structure 100; general dielectric layer 120 can be the laminated construction of multilayer; the nitride layer 120a that has for example comprised the etching stop layer effect; be positioned at the interlayer dielectric layer 120b on the nitride layer 120a, and be arranged on the interlayer dielectric layer at barrier layer 120c that etching shields.Described interlayer dielectric layer 120b is selected from SiO usually
2The perhaps SiO of Can Zaing
2USG (Undoped silicon glass for example, the silex glass that does not have doping), BPSG (Borophosphosilicate glass, the silex glass of boron phosphorus doped), BSG (borosilicate glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.Has sacrifice layer 130 on the described dielectric layer 120.As in a specific implementation, the material of described sacrifice layer 130 is a metal, and the thickness of sacrifice layer is
For example be specially metallic nickel (nickel), fusing point is at 1456 degrees centigrade, and the thickness of nickel dam is
This thickness can guarantee to form dual-damascene structure in follow-up punching press in sacrifice layer 130, and this thickness can also combine feasible dual-damascene structure in the sacrifice layer well can being transferred in the dielectric layer with follow-up etch step.
The formation method of impression shielding 200 can be utilized metal material, for example any one in vanadium, lead (vanadium), tantalum (tantalum), niobium (niobium), zirconium (zirconium) and the titanium (titanium) and combination thereof, under molten condition, once-cast forms in grinding tool, also can utilize provides ground floor substrate 210 earlier, on ground floor substrate 210, utilize physical vapor deposition to form the second layer then, through the square body 220a of over etching with second layer formation and groove complementation; On the second layer after the etching, utilize physical vapor deposition to form the 3rd layer then, utilize the cylinder 220b of etching then the 3rd layer of formation and through hole complementation.So just formed the impression shielding 200 of the projection that on ground floor, has the second layer and the 3rd layer of formation.Certainly those skilled in the art also can, utilize other method to form.Thickness those skilled in the art of described side's body 220a can be according to the degree of depth decision of groove in the dual-damascene structure that will form.Thickness those skilled in the art of described cylinder 220b can be according to through hole decision in the dual-damascene structure that will form.Except that above-mentioned material, also can utilize to be not easy the punching press distortion, and the other materials of fusing point more than the nickel fusing point.The material of described substrate 210 and projection 220 can be the same or different.General, the fusing point of described sacrifice layer 130 is lower than the fusing point of described impression shielding 200, like this can be so that can not be out of shape in the shielding of impression described in the follow-up punching course 200.
Then, continue to carry out step S20, semiconductor structure 100 is heated, make the sacrifice layer 130 on it softening with reference to figure 7.In a specific implementation, can for example, sacrifice layer 130 need be heated to 1453 degrees centigrade with semiconductor structure 100 as for making its sacrifice layer 130 reach fusing point in the annealing furnace for the sacrifice layer 130 of nickel material.Make nickel material be molten state.
Then, carry out step S30 with reference to figure 8, utilize described impression shielding 200, along upper surface direction perpendicular to described semiconductor structure 100, described semiconductor structure 100 is carried out punching press, below the cylinder 220b of projection 220 is positioned in the described impression shielding 100 during punching press, to being positioned at semiconductor structure 100 punching presses that described impression shields 200 belows, described cylinder 220b subpunch is compressed into into sacrifice layer 130, square then body 220a enters sacrifice layer 130, concrete stamping press those skilled in the art can obtain according to the material of sacrifice layer 130, enter sacrifice layer 130 as long as can guarantee impression shielding 200, because be molten state after the sacrifice layer 130 that described nickel material constitutes is heated in step S20, therefore be stamped than being easier to.
For example can be in advance described impression shielding 200 be fixed on the device that can move along pressing direction, control this device then to semiconductor structure 100 direction punching presses, because sacrifice layer 130 is molten state or softer state, thereby sacrifice layer 130 is stamped the projection 220 of shielding 200 and presses to other positions under the effect of stamping press, thereby the projection 220 of impression shielding 200 can embed in the described sacrifice layer 130.In this step S30, because the fusing point of impression shielding 200 is higher than sacrifice layer 130, therefore impression shielding 200 can not be out of shape, and has kept the bulge-structure of good and dual-damascene structure complementation.
In a specific implementation, the edge of ground floor substrate 210 stretches out projection 220 scopes that are positioned in the described impression shielding 200, this marginal portion just can be stuck on the surface of described semiconductor structure 100, make lucky described protruding 220 to embed in the sacrifice layer, make manufacture process more accurate, the dual-damascene structure of formation is better.
Then, continue to carry out step S40,, in a specific implementation, can perhaps pass through natural cooling, make described sacrifice layer 130 hardening with semiconductor structure 100 as among the cooling device with 130 coolings of the sacrifice layer on the described semiconductor structure 100 with reference to figure 8.
Then,, carry out step S40, the projection 220 of impression shielding 200 is taken out from sacrifice layer 130 with reference to figure 9.In a specific implementation, the shielding 200 of described impression is different with the material of sacrifice layer 130, can not merge fully between therefore, like this as long as shield 200 along withdraw from described impression away from semiconductor structure 100 directions.Thereby just in described sacrifice layer 130, stayed the shape of described protruding 220 complementations, i.e. a groove 140a and the dual-damascene structure that through hole 140b constitutes.
In a specific implementation, described protruding 220 height equals the thickness of sacrifice layer 130.Thereby groove 140a that projection 220 forms and the degree of depth sum of through hole 140b equal the thickness of sacrifice layer 130, and therefore after step S40, the dual-damascene structure of formation can expose the dielectric layer 120 of through hole 140b bottom.
Then, with reference to Figure 10, carry out step S50, semiconductor structure 100 is carried out etching, along with the dual-damascene structure (and groove and through hole) that carries out in the described sacrifice layer 130 of etching can extend to dielectric layer 120 from sacrifice layer 130, thereby make and in dielectric layer 120, form dual-damascene structure.
In a specific implementation, described etching parameters is: chlorine 10sccm～50sccm, and argon gas 10sccm～100sccm, chamber pressure are 2mTorr～10mTorr, and the bottom bias voltage is 100V～500V, and power is 500W～1000W.Under above-mentioned etching parameters, if sacrifice layer 130 is a metallic nickel materials, dielectric layer is SiO
2The perhaps SiO of Can Zaing
2Then the etch rate of dielectric layer 120 can be faster than the etch rate of sacrifice layer 130; through hole 140a position is not owing to there is the protection of sacrifice layer 130 like this; other positions of the speed ratio of etching are fast; when groove 140b position etches into dielectric layer 120; speed can be accelerated, thereby the through hole 150b degree of depth and the groove 150a degree of depth of the dual-damascene structure in the dielectric layer 120 that in the end forms are all big than the degree of depth in the sacrifice layer 130.
With reference to Figure 11, in another preferred embodiment, after step S50, also comprise and utilize wet etching to remove described sacrifice layer 130.The for example concrete concentration of utilizing is 4: 5～5: 4, the mixed solution of 1: 1 phosphoric acid and hydrofluoric acid for example, and perhaps concentration ratio is: 10: 1～10: 3, for example the mixed solution of 5: 1 hydrochloric acid and phosphoric acid carried out wet etching.
The present invention forms dual-damascene structure by utilizing impression shielding impression in conjunction with the method for etching in dielectric layer, thereby avoided utilizing in the prior art two step photoetching and be etched in the method that forms dual-damascene structure in the dielectric layer, therefore avoid the damage that when mask layer is removed in ashing after etch step in the prior art substrate caused, improved the reliability of the device of follow-up formation like this.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (15)
1. a dual-damascene structure formation method is characterized in that, comprises step:
Semiconductor structure and impression shielding are provided, and semiconductor structure comprises interconnection layer, is positioned at the dielectric layer on the interconnection layer, is positioned at the sacrifice layer on the dielectric layer, and described impression shielding comprises the projection that has with the dual-damascene structure complementary shape;
Sacrifice layer on the described semiconductor structure is heated, make described sacrifice layer softening;
Utilize described impression shielding that the sacrifice layer on the described semiconductor structure is carried out punching press, make that the projection on the described semiconductor structure embeds in the described sacrifice layer;
Sacrifice layer on the semiconductor structure is cooled off, make described sacrifice layer harden;
Described impression shielding is taken out, thereby on the sacrifice layer of described semiconductor structure, form dual-damascene structure;
Semiconductor structure with dual-damascene structure is carried out etching, make in dielectric layer, to form dual-damascene structure, and the via bottoms in the described dual-damascene structure exposes interconnection layer.
2. dual-damascene structure formation method according to claim 1 is characterized in that, the height of described projection equals the thickness of sacrifice layer.
3. dual-damascene structure formation method according to claim 1 is characterized in that, utilizes wet etching to remove described sacrifice layer in described also comprising after semiconductor structure with dual-damascene structure being carried out the step of etching.
4. dual-damascene structure formation method according to claim 3 is characterized in that described wet-cleaned is utilized the mixed solution of phosphoric acid and hydrofluoric acid.
5. dual-damascene structure formation method according to claim 4 is characterized in that, the concentration ratio of described phosphoric acid and hydrofluoric acid is: 4: 5～5: 4.
6. dual-damascene structure formation method according to claim 3 is characterized in that described wet-cleaned is utilized the mixed solution of hydrochloric acid and phosphoric acid.
7. dual-damascene structure formation method according to claim 6 is characterized in that, the concentration of described hydrochloric acid and concentration of phosphoric acid ratio are: 10: 1～10: 3.
8. dual-damascene structure formation method according to claim 1 is characterized in that, the fusing point of described sacrifice layer is lower than the fusing point of described impression shielding.
9. dual-damascene structure formation method according to claim 1 is characterized in that, the material of described sacrifice layer is a metal.
10. dual-damascene structure formation method according to claim 9 is characterized in that the thickness of described sacrifice layer is
11. dual-damascene structure formation method according to claim 10 is characterized in that, the material of described sacrifice layer is a metallic nickel.
12. dual-damascene structure formation method according to claim 11, it is characterized in that, describedly semiconductor structure with dual-damascene structure is carried out etching parameters is in the etch step: chlorine 10sccm～50sccm, argon gas 10sccm～100sccm, chamber pressure is 2mTorr～10mTorr, the bottom bias voltage is 100V～500V, and power is 500W～1000W.
13. dual-damascene structure formation method according to claim 11 is characterized in that, the material of described impression shielding is a metal.
14. dual-damascene structure formation method according to claim 13 is characterized in that, the material of described impression shielding is a kind of or its combination in vanadium, lead, tantalum, niobium, zirconium and the titanium.
15. dual-damascene structure formation method according to claim 1, it is characterized in that, described impression shielding comprises substrate and the projection that is positioned on the substrate, the cylinder on the described projection side of comprising body and the side's of the being positioned at body, and described side's body and cylindrical central shaft are perpendicular to described substrate surface.
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| CN114235870A (en) * | 2021-12-17 | 2022-03-25 | 中国核动力研究设计院 | Preparation method of irradiated zirconium alloy scanning electron microscope sample based on conductive shielding mosaic |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1722366A (en) * | 2004-06-01 | 2006-01-18 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN1860605A (en) * | 2003-09-29 | 2006-11-08 | 国际商业机器公司 | Fabrication method |
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| CN1860605A (en) * | 2003-09-29 | 2006-11-08 | 国际商业机器公司 | Fabrication method |
| CN1722366A (en) * | 2004-06-01 | 2006-01-18 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114235870A (en) * | 2021-12-17 | 2022-03-25 | 中国核动力研究设计院 | Preparation method of irradiated zirconium alloy scanning electron microscope sample based on conductive shielding mosaic |
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