CN102201606B - Time-sharing frequency-reducing filter and time-sharing frequency-reducing filtering method - Google Patents
Time-sharing frequency-reducing filter and time-sharing frequency-reducing filtering method Download PDFInfo
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Abstract
The invention provides a time-sharing frequency-reducing filter and a time-sharing frequency-reducing filtering method. The time-sharing frequency-reducing filter comprises two frequency-reducing filtering units, wherein a first frequency-reducing filtering unit is operated under a system clock pulse and is used for receiving a first order input data string; each datum in the first order input data string comprises first part data and second part data; at an odd clock pulse period, the first part data are output after filtration and frequency reduction; at an even clock pulse period, the second part data are output after filtration and frequency reduction; the second frequency-reducing filtering unit is operated under the system clock pulse; 2N clock pulse periods are taken as one operation interval unit; N is more than or equal to 2; and the second frequency-reducing filtering unit is used for receiving the output of the first frequency-reducing filtering unit and receiving a plurality of feedback data of the second frequency-reducing filtering unit in a time-sharing mode to distribute the feedback data into the 2N clock pulse periods for performing filtering and frequency-reducing output in a time-sharing mode.
Description
Technical field
The invention relates to a kind of timesharing frequency reducing filter and timesharing frequency reducing filtering method, wherein the filtering of frequency reducing filter unit and the processing of frequency reducing can be carried out in timesharing.
Background technology
In signal transmits, having some signals is to utilize highdensity sampling point and convert digital form to transmit.Yet the processing of transmitted data must first will just can be taken out in the one end at reception & disposal after the processing of signal filtering and frequency reducing.Generally speaking, the degree of frequency reducing need to reach quadravalence, is to do the frequency reducing of 16 times.
Fig. 1 is the configuration diagram of traditional filtering and frequency reducing.Consult Fig. 1, from frequency domain (frequency domain), input signal is the frequency input with fs, and it does the frequency reducing of quadravalence by four frequency reducing filter units (decimation filter unit) 100, and the frequency of its output signal is fs/16.Frequency reducing filter unit 100 is comprised of half band filter (half band filter, HBF) and discarding unit (decimator).Discarding unit is with arrow representative down.Change sentence or say, each frequency reducing filter unit 100 can be done the frequency reducing sampling of fs/2 and frequency reducing that four frequency reducing filter units 100 amount to fs/16 samples.For output, the frequency reducing filter unit 100 of every single order can offer the input of the frequency reducing filter unit 100 of lower single order, also can output in addition time division multiplexing device (time-division multiplexer, MUX) 102 simultaneously, by control signal 104, the information of output is selected in timesharing.
With regard to actual data, for example, in satellite communication, an one data are comprised of real part information (real part) and imaginary data (imaginary part), are called I data and Q data.If according to the conventional architectures of Fig. 1, four times of frequency reducings that will reach I data and Q data can be reached with regard to 16 frequency reducing filter unit 100 wealth of needs.This design at least has expensive considering.Design how more effectively to carry out filtering and frequency reducing is the direction one of research and development.
Summary of the invention
The invention provides a kind of timesharing frequency reducing filter and timesharing frequency reducing filtering method, can effectively utilize the time idle in traditional approach, with pipeline (pipeline) mechanism, reach the use amount that reduces filtering and frequency reducing unit.
The present invention proposes a kind of timesharing frequency reducing filter, comprises two frequency reducing filter units.The first frequency reducing filter unit operates under a system clock pulse, receives one first rank input serial data.Each data in the first rank input serial data comprise first's data and second portion information.After doing filtering and frequency reducing, odd number clock pulse cycle ，Jiang first data export.In the even number clock pulse cycle, after being done to filtering and frequency reducing, second portion data export.The second frequency reducing filter unit, under system clock pulse, take in 2N clock pulse cycle unit as between an operating space in operation, and N is greater than or equal to 2.The second frequency reducing filter unit receives the output of this first frequency reducing filter unit and a plurality of feedback data that timesharing receives this second frequency reducing filter unit, and to be assigned to described 2N clock pulse in the cycle, filtering and frequency reducing output are done in timesharing.
The present invention proposes a kind of timesharing frequency reducing filtering method, comprise and utilize first two times of frequency reducing filter units, under a system clock pulse, operate, receive one first rank input serial data, wherein each data in this first rank input serial data comprise first's data and second portion data, wherein after each odd number clock pulse cycle Jiang Gai first data of this system clock pulse are done filtering and two times of frequency reducings, export, export after these second portion data being done to filtering and two times of frequency reducings in each even number clock pulse cycle.Utilize one second two times of frequency reducing filter unit, under system clock pulse, take in 2N clock pulse cycle unit as between an operating space in operation, N is greater than or equal to 2, wherein these second two times of frequency reducing filter unit receives the output of this first two times of frequency reducing filter units and a plurality of feedback data that timesharing receives these second two times of frequency reducing filter unit, to be assigned to described 2N clock pulse in the cycle, filtering and frequency reducing output are done in timesharing.
For the above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the configuration diagram of traditional filtering and frequency reducing;
Fig. 2 is the circuit box schematic diagram of a kind of timesharing frequency reducing of one embodiment of the invention filter;
Fig. 3 is that the present invention will reach the operation mechanism schematic diagram of simplifying two times of frequency reducing filter units 120;
Fig. 4 is the operation mechanism schematic diagram of two times of frequency reducing filter units 120 of one embodiment of the invention
Fig. 5 is input and the output function schematic diagram of mechanism of two times of frequency reducing filter units 120 of one embodiment of the invention
Fig. 6 is the time sequential routine schematic diagram of two times of frequency reducing filter units 122 of one embodiment of the invention;
Fig. 7 is the digital sampling data that are input to two times of frequency reducing filter units;
Fig. 8 is designed half band filter (HBF) circuit diagram of the sampling of Fig. 7;
Fig. 9 is the function circuit schematic diagram of mechanism of two times of frequency reducing filter units;
Figure 10 is the input and output schematic diagram of mechanism that two times of frequency reducing filter units carry out the filtering down conversion process of three times;
Figure 11 does the schematic diagram of mechanism of time-sharing operation in Fig. 8;
Figure 12 is the selection schematic diagram of mechanism of one embodiment of the invention selector.
Description of reference numerals
100: frequency reducing filter unit; 102: time division multiplexing device;
104: control signal; 120: two times of frequency reducing filter units;
122: two times of frequency reducing filter units; 130: delayer;
132: adder; 134: multiplier;
136: add up device; 138: output data;
140,144: selector; 142: control unit.
Embodiment
The present invention proposes the design that frequency reducing filter unit is more effectively utilized, and can reduce the quantity of frequency reducing filter unit, and it for example can reach traditional approach by two frequency reducing filter units and use eight frequency reducing filter units to reach the effect of 16 times of frequency reducings.
Below for some embodiment, the present invention is described, but the present invention is not limited only to lifted a plurality of embodiment, and for a plurality of embodiment between also suitably combination.
With regard to carrying out 16 times of frequency reducings operation of quadravalence, one embodiment of the invention proposes can reach by two frequency reducing filter units, the operation of real part data and 16 times of frequency reducings of imaginary data.Fig. 2 is the circuit box schematic diagram of a kind of timesharing frequency reducing of one embodiment of the invention filter.Timesharing frequency reducing filter comprises two two times of frequency reducing filter units 120,122.The circuit structure of frequency reducing filter unit can be in being described in more detail below.Two times of frequency reducing filter units 120 operate under a system clock pulse, receive input serial data.Each data in input serial data comprise first's data and second portion data.First's data are for example real part data, with I, represent.Second portion data are for example imaginary data, with Q, represent.Real part data and imaginary data form a complex data (complex data).As described below, after doing filtering and two times of frequency reducings, each odd number clock pulse cycle Jiang Gai first data of system clock pulse export, export after these second portion data being done to filtering and two times of frequency reducings in each even number clock pulse cycle.Real part data and the imaginary data of 120 pairs of input serial datas of two times of frequency reducing filter units like this are all done frequency reducing filtering, are then input to two times of frequency reducing filter units 122.The output frequency of two times of frequency reducing filter units 120 can be by two times of frequency reducings.That is to say, 120 pairs of real part data of two times of frequency reducing filter units and imaginary data have all been done the first rank frequency reducing filtering (D1).
In the present invention, two times of frequency reducing filter units 122 are also to operate with 2 under system clock pulse
nthe individual clock pulse cycle is unit between an operating space, and N is greater than or equal to 2, and the present embodiment is to take N=4 as example.Two times of frequency reducing filter units 122 receive data output and a plurality of feedback data of two times of frequency reducing filter units of timesharing reception 122 own of two times of frequency reducing filter units 120, to be assigned to described 2
nindividual clock pulse is in the cycle, and filtering and frequency reducing output are done in timesharing.That is to say, with the operation of quadravalence, 122 pairs of real part data of two times of frequency reducing filter units and imaginary data feedback loop have been done the second frequency reducing filtering (D2-D4) to quadravalence.So, for example only with two two times of frequency reducing filter units 120,122, can reach the action of 16 times of frequency reducings.
Fig. 3 is that the present invention will reach the operation mechanism schematic diagram of simplifying two times of frequency reducing filter units 120.Consult Fig. 3, the present invention inspects traditional approach and uses two two times of frequency reducing filter units for real part and imaginary data, to do rate frequency reducing respectively, and its characteristic is as follows.Input serial data comprises real part input serial data I
incomprise X1, X2, X3, X4, X5 ....; And imaginary part input serial data Q
incomprise Q1, Q2, Q3, Q4, Q5 ..., by a discarding unit, do frequency reducing again after doing filtering by a HBF respectively.At this, be first to process real part data instance, yet also can first process imaginary data according to identical mode, it is determined according to actual needs.
First from real part input serial data I
inobtain time relationship and observe, it obtains Y1 after the filtering of half band filter, Y2, and Y3, Y4, Y5 ....Then, the even data Y2 in filtered data, Y4 ... can all be abandoned, to reach the effect of two times of frequency reducings.In other words processing even data Y2, the time of Y4... etc. is in fact unnecessary, and its corresponding data can be lost.And be also to do with the data of real part the down conversion process of same way for the data of imaginary part.
Based on imaginary data and real part data, all can do through discarding unit the processing of two times of frequency reducings, if the present invention considers the serial data of imaginary part to delay the even data Y2 of corresponding real part data, the time of Y4, be replaced to the filtering of the data of carrying out imaginary part, and the mode of output is changed into the sequentially output of real part and imaginary part.More, it does not need the frequency reducing of discarding unit, because when doing real part and imaginary part for rate ripple, it just reaches the effect of two times of frequency reducings.
Fig. 4 is the operation mechanism schematic diagram of two times of frequency reducing filter units 120 of one embodiment of the invention.Mechanism based on Fig. 3, two times of frequency reducing filter units 120 of Fig. 4 do not need to abandon data, but adjust the order of input data, and the order of output data.The embodiment of the present invention proposes, in two times of frequency reducing filter units 120 on the first rank, when carrying out real part data, imaginary part to be inputted to serial data Q
inin the corresponding clock pulse cycle of the data that cooperation real part data will abandon, after suitably postponing, be input in two times of identical frequency reducing filter units 120.So, imaginary part input serial data Q
inthe odd data Y1 retaining, Y3 ... be corresponding to real part input serial data I
inthe even data Y2 abandoning, Y4....So two times of real part output serial data I that frequency reducing filter unit 120 is exported
outodd data Y1, Y3, Y5... is two times of frequency reducing data with respect to system clock pulse.Again, two times of imaginary part output serial data Q that frequency reducing filter unit 120 is exported
outodd data Y1, Y3 ... with respect to system clock pulse, be also two times of frequency reducing data, but with respect to I
outto delay a clock pulse cycle.So, two times of frequency reducing filter units 120 on the first rank can be processed real part data and imaginary data simultaneously, and do not need two two times of frequency reducing filter units 120 respectively real part data and imaginary data to be dealt with.
Fig. 5 is input and the output function schematic diagram of mechanism of two times of frequency reducing filter units 120 of one embodiment of the invention.Consult Fig. 5, the input mode of real part and imaginary part be by the data Q1 of imaginary part, Q3 ... correspond to X2, the X4... of real part data, it is the data that can be dropped while belonging to frequency reducing.At data output end, do not need traditional discarding unit to do frequency reducing, but sequentially the data of odd number are considered as to the output of real part data I, and the data of even number are considered as imaginary data Q output.
The operation mechanism of two times of frequency reducing filter units 122 in Fig. 2 is then described.In two times of frequency reducing filter units 122 of second-order, because follow-up frequency reducing action can be vacated the how available time, and allow to fall the frequency reducing action of three times, be integrated at two times of frequency reducing filter units 122 and process.According to identical principle, compared with the data input that sequentially circulates, and output data are selected according to rule, with the frequency reducing output of the every single order of correspondence.
Fig. 6 is the time sequential routine schematic diagram of two times of frequency reducing filter units 122 of one embodiment of the invention.Consult Fig. 6, because two times of frequency reducing filter units 120 on the first rank have been done two times of frequency reducings, therefore be input to the clock pulse of two times of frequency reducing filter units 122, with D2in Clk, indicate, its sequential is two times of frequency reducings with respect to system clock pulse (System Clk), and output clock pulse indicates with D2out Clk, can be once again by two times of frequency reducings, the data that wherein belong to the clock pulse cycle that indicates x can be dropped.In other words, with regard to the frequency reducing of second-order, its output cycle is 2
2the individual clock pulse cycle.So mechanism, with respect to the frequency reducing on D2 rank, has a clock pulse cycle having more can not be actually used as the aforementioned, therefore, according to the similar mechanism of Fig. 3-5, can utilize the clock pulse cycle having more to do down conversion process.
Two times of frequency reducing filter units 122 itself still operate in system clock pulse (System Clk), and it,, for the follow-up frequency reducing action of three times, can contain 2
4=16 clock pulse cycle 0-15 is a time quantum, as shown in the 4th sequential.Again, system clock pulse, can be with 2 for the clock pulse cycle of the D2out Clk of second-order
2=4 is a sub-cell, as shown in the 3rd sequential.In Fig. 6, I real part output data, Q represents imaginary part output data.Frequency reducing along with the digitized representation 2-4 rank of I and Q.Again, the sign of DecF No is in order to correspondence, to be indicated in the order of two times of frequency reducing filter units, 122 circulations.
In the present embodiment, from the 3rd sequential, in the clock pulse cycle of clock pulse sequence number 0, be for processing the data with output I2.In the clock pulse cycle of clock pulse sequence number 1, be for processing the data with output Q2.In the clock pulse cycle of clock pulse sequence number 3, be for processing and the data of exporting I3 and Q3.In the clock pulse cycle of clock pulse sequence number 2, be for processing and the data of exporting I4 and Q4.
As above-described embodiment, it only needs three frequency reducings of just can the time-division processing follow-up D2-D4 of two times of frequency reducing filter units 122.Certainly to the output data of wanting, can feed back to two times of frequency reducing filter units 122 according to sequential, and output is timesharing output.
Mechanism based on identical, the mode that the planning of Fig. 6 neither be unique.Its quantity according to the vacated clock pulse cycle can be integrated down conversion process repeatedly.Change sentence or say, it can be with 2
nthe individual clock pulse cycle is that a time quantum is done repeatedly frequency reducing, N≤2.The N of the present embodiment is 4.Table 1-3 is the embodiment of the sequential program(me) of three frequency reducings under the cycle at 16 clock pulses.
Table 1
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
| I2 | ? | ? | ? | I2 | ? | ? | ? | I2 | ? | ? | ? | I2 | ? | ? | ? |
| ? | Q2 | ? | ? | ? | Q2 | ? | ? | ? | Q2 | ? | ? | ? | Q2 | ? | ? |
| ? | ? | I3 | ? | ? | ? | ? | ? | ? | ? | I3 | ? | ? | ? | ? | ? |
| ? | ? | ? | ? | ? | ? | Q3 | ? | ? | ? | ? | ? | ? | ? | Q3 | ? |
| ? | ? | ? | ? | ? | ? | ? | I4 | ? | ? | ? | ? | ? | ? | ? | ? |
| ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | Q4 | ? | ? | ? | ? |
Table 2
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
| I2 | ? | ? | ? | I2 | ? | ? | ? | I2 | ? | ? | ? | I2 | ? | ? | ? |
| ? | Q2 | ? | ? | ? | Q2 | ? | ? | ? | Q2 | ? | ? | ? | Q2 | ? | ? |
| ? | ? | ? | I3 | ? | ? | ? | ? | ? | ? | ? | I3 | ? | ? | ? | ? |
| ? | ? | ? | ? | ? | ? | ? | Q3 | ? | ? | ? | ? | ? | ? | ? | Q3 |
| ? | ? | ? | ? | ? | ? | I4 | ? | ? | ? | ? | ? | ? | ? | ? | ? |
| ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | Q4 | ? | ? | ? | ? | ? |
Table 3
Below describe side circuit and process the anaiog signal of input.Fig. 7 is the digital sampling data that are input to two times of frequency reducing filter units.Consult Fig. 7, anaiog signal every sampling and digitlization, wherein coordinates the design of half band filter according to regular time, for example, be once that 11 digital sampling points with P0-P10 carry out filtering processing.Fig. 8 is designed half band filter (HBF) circuit diagram of the sampling of Fig. 7.Consult Fig. 8, the digital sampling point of corresponding diagram 7 and be provided with 10 delayers 130, each delayer 130 can postpone clock pulse cycles.When input numerical data according to after time input, by the effect of delayer and the effect of three adders 132, obtain respectively P0+P10, p2+p8, three output numerical value of P4+P6, wherein the data of P5 are independent output.Then there are four multipliers 134 respectively to P0+P10, p2+p8, P4+P6, P5 is multiplied by predetermined ordinal number h (0)-h (4).What then, by a totalling device 136, four numerical value are added up obtains output data 138, the Y value in representative graph 5.
Fig. 9 is the function circuit schematic diagram of mechanism of two times of frequency reducing filter units.Consult Fig. 9, coordinate the operation mechanism of Fig. 5, half band filter of two times of frequency reducing filter units receives after the data of real part I, and the data of imaginary part Q, after delayer D does and postpones, are input to again half band filter of two times of frequency reducing filter units.Wherein dotted line representative utilizes the input selection position of time division multiplexing to adder.Then the data that selection will retain are done in the output of double band filter, reach the effect that abandons frequency reducing, but needn't need discarding unit to process, and this is because replacing of odd number I and even number Q arranges just can reach the effect abandoning.So complete the filtering down conversion process on the first rank.
Three times follow-up filtering down conversion process also can the mode with timesharing be completed by another two times of frequency reducing filter units.Figure 10 is the input and output schematic diagram of mechanism that two times of frequency reducing filter units carry out the filtering down conversion process of three times.Consult Figure 10, the corresponding I2 that illustrates, Q2, I3, Q3, I4, Q4 six string delayers, on hardware, be all identical string delayer, and be only input data different from time point.I2 and Q2 do the input data of filtering frequency reducing for the second time according to the output of I1 and Q1.I3 and Q3 do the input data of filtering frequency reducing for the third time according to the output of I2 and Q2.I4 and Q4 do the input data of the 4th filtering frequency reducing according to the output of I3 and Q3.
Figure 11 does the schematic diagram of mechanism of time-sharing operation in Fig. 8.Consult Figure 11, three pairs of data of corresponding Figure 10, it also comprises six kinds of data I 2, Q2, I3, Q3, I4, the selection of Q4, the sequential of cooperation Fig. 4, corresponding to P0+P10, P2+P8, three adders 132 of difference of P4+P6, the input of adder 132 need to be done timesharing switching.Selector 140 represents corresponding I2 with selector 144, Q2, and I3, Q3, I4, does timesharing the input time of Q4 and switches, and the switching signal being provided by control unit 142 is controlled.
Figure 12 is the selection schematic diagram of mechanism of one embodiment of the invention selector.Consult Figure 12, the operation mechanism of selector 140 of take illustrates as example.From the sequential relationship shown in Fig. 4 or table 2, the data of I2 can be processed in the clock pulse cycle 0,4,8,12.The data of Q2 can be processed in the clock pulse cycle 1,5,9,13.The data of I3 can be processed in the clock pulse cycle 3,11.The data of Q3 can be processed in the clock pulse cycle 7,15.The data of I4 can be processed in the clock pulse cycle 6.The data of Q4 can be processed in the clock pulse cycle 10.Clock pulse is selected the data of correspondence of signal CLK_CNT timesharing choosing, makes data output to adder, carries out add operation.
So, two times of frequency reducing filter units of second are by the feedback input processing of timesharing and the output of timesharing, and the clock pulse cycle that while utilizing frequency reducing, corresponding data can be dropped is done the filtering frequency reducing of lower single order, to reach two times of frequency reducings on three rank.So at least with the present embodiment, can be by generally using 8 two times of frequency reducing filter units to reach the effect of 16 times of frequency reducings, economization is for using two two times of frequency reducing filter units, and also can reach the effect of 16 times of frequency reducings.
Although the present invention describes as above with embodiment; so it,, not in order to limit the present invention, has and conventionally knows the knowledgeable in any affiliated technical field, is not departing from spirit and scope of the invention; all can do a little change and retouching, therefore protection range of the present invention is when being as the criterion with claims.
Claims (8)
1. a timesharing frequency reducing filter, comprising:
One first two times of frequency reducing filter units, under a system clock pulse, operate, receive one first rank input serial data, wherein each data in this first rank input serial data comprise first's data and second portion data, wherein after each odd number clock pulse cycle Jiang Gai first data of this system clock pulse are done filtering and two times of frequency reducings, export, export after these second portion data being done to filtering and two times of frequency reducings in each even number clock pulse cycle; And,
One second two times of frequency reducing filter unit, under this system clock pulse, operation is with 2
nthe individual clock pulse cycle is unit between an operating space, N is greater than or equal to 2, wherein these second two times of frequency reducing filter unit receives the output of this first two times of frequency reducing filter units and a plurality of feedback data that timesharing receives these second two times of frequency reducing filter unit, to be assigned to described 2
nindividual clock pulse is in the cycle, and filtering and frequency reducing output are done in timesharing.
2. timesharing frequency reducing filter according to claim 1, the N=4 of these second two times of frequency reducing filter unit and obtain take 16 clock pulse cycles unit as between this operating space wherein, wherein 16 clock pulse cycles are divided and give sequence number 0-15 as a following tabular, wherein I represents these first's data of each these data, Q represents these second portion data of each these data, I2, Q2 represents the output of second-order filtering and frequency reducing, I3, Q3 represents the output of the 3rd rank filtering and frequency reducing, I4, Q4 represents the output of quadravalence filtering and frequency reducing, this tabular is
Or
Or
3. timesharing frequency reducing filter according to claim 1, wherein these first's data and this second portion data are respectively real part data and imaginary data of each these data.
4. timesharing frequency reducing filter according to claim 1, wherein these second two times of frequency reducing filter unit also comprises a time division multiplexing device, according to a predetermined time sequencing, selects the output of these second two times of frequency reducing filter unit.
5. timesharing frequency reducing filter according to claim 1, wherein each of this first two times of frequency reducing filter units and these second two times of frequency reducing filter unit comprises half band filter.
6. timesharing frequency reducing filter according to claim 1, wherein this first two times of frequency reducing filter units complete after first-order filtering and frequency reducing, this first two times of frequency reducing filter units utilization, in this first two times of clock pulse cycles that frequency reducing filter unit is vacated, operates rank filtering and the frequency reducing of the three phases of follow-up circulation.
7. a timesharing frequency reducing filtering method, comprising:
Utilize first two times of frequency reducing filter units, under a system clock pulse, operate, receive one first rank input serial data, wherein each data in this first rank input serial data comprise first's data and second portion data, wherein after each odd number clock pulse cycle Jiang Gai first data of this system clock pulse are done filtering and two times of frequency reducings, export, export after these second portion data being done to filtering and two times of frequency reducings in each even number clock pulse cycle; And,
Utilize one second two times of frequency reducing filter unit, under this system clock pulse, operation is with 2
nthe individual clock pulse cycle is unit between an operating space, N is greater than or equal to 2, wherein these second two times of frequency reducing filter unit receives the output of this first two times of frequency reducing filter units and a plurality of feedback data that timesharing receives these second two times of frequency reducing filter unit, to be assigned to described 2
nindividual clock pulse is in the cycle, and filtering and frequency reducing output are done in timesharing.
8. timesharing frequency reducing filtering method according to claim 7, wherein set the N=4 of these second two times of frequency reducing filter unit and obtain take 16 clock pulse cycles unit as between this operating space, wherein 16 clock pulse cycles are divided and give sequence number 0-15 as a following tabular, wherein I represents these first's data of each these data, Q represents these second portion data of each these data, I2, Q2 represents the output of second-order filtering and frequency reducing, I3, Q3 represents the output of the 3rd rank filtering and frequency reducing, I4, Q4 represents the output of quadravalence filtering and frequency reducing
Wherein these second two times of frequency reducing filter unit carries out this second-order filtering and frequency reducing according to the sequential of this tabular, the 3rd rank filtering and frequency reducing and this quadravalence filtering and frequency reducing, and this tabular is
or
。
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| CN1442986A (en) * | 2002-03-04 | 2003-09-17 | 三星电子株式会社 | I/Q demodulator and its I/Q signal sampling method |
| CN101674067A (en) * | 2006-09-18 | 2010-03-17 | 晨星半导体股份有限公司 | Frequency-lowering device and sound signal processing system using same |
| CN101682297A (en) * | 2007-06-04 | 2010-03-24 | Nxp股份有限公司 | Digital signal processing circuit and method comprising band selection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1442986A (en) * | 2002-03-04 | 2003-09-17 | 三星电子株式会社 | I/Q demodulator and its I/Q signal sampling method |
| CN101674067A (en) * | 2006-09-18 | 2010-03-17 | 晨星半导体股份有限公司 | Frequency-lowering device and sound signal processing system using same |
| CN101682297A (en) * | 2007-06-04 | 2010-03-24 | Nxp股份有限公司 | Digital signal processing circuit and method comprising band selection |
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