CN102195709A - Method for obtaining clock states and operation modes of network element in simulation of fiber breaking failure - Google Patents
Method for obtaining clock states and operation modes of network element in simulation of fiber breaking failure Download PDFInfo
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Abstract
The invention discloses a method for obtaining clock states and operation modes of a network element in the simulation of a fiber breaking failure. The network element connected with a failing optical fiber serves as a starting network element, quality level (QL) values of main and standby clocks of all downstream connected network elements taking a clock of the starting network element as the main clock are iteratively updated in turn to obtain the clock states of all the network elements in a system, and then the clock states and operation modes of all the network elements are definitely displayed according to the criterion rules of clock switching. A user can conveniently analyze reasons for the failure.
Description
Technical field
The present invention relates to the optical transport network analogue system, be specifically related in the optical transport network analogue system, obtain the method for network element clock status and mode of operation during the simulation fiber cut failure.
Background technology
Fast development along with network technology, the effect of network analog system is more and more important, utilizes the network analog system, and the user can dispose network element easily and set up network topology on graphical interfaces, observe the situation of network real time execution, and simulation diverse network fault.
In an optical transport network system, the clock frequency of all switching nodes (network element) all should be controlled in the predetermined range of tolerable variance in the network, so that make correct, the effectively transmission exchange of whole digital communication signals realizations of each switching node in the net.Solving the synchronous method of digital network mainly is that the principal and subordinate is synchronous.The principal and subordinate is meant synchronously the clock main station is set that the configuration high precision clock respectively all is controlled by this main station from office in the net, promptly follows the tracks of master clock, is timing base with the master clock, and controls the terminal network element (terminal station) in network down step by step in the optical transport network system.In order to increase the reliability of principal and subordinate's synchro system, can in net, some secondary clocks be set, adopt grade principal and subordinate control mode.Two clocks all adopt absolute clock, play the effect of network timing base at master clock just often, and secondary clock is a benchmark with the clock of master clock also.When master clock broke down, changing by secondary clock provided timing base to network, switched back after master clock recovers again, and continuing provides the network benchmark regularly by master clock.When adopting the principal and subordinate synchronous, the timing signal of upper level network element is by certain route synchronization link or be attached on the line signal, be transferred to the next stage network element, this grade network element extracts this clock signal, by this clock of phase-locked oscillator tracking lock of itself, and to produce with this clock be the used local clock signal of this network element of benchmark, transmits to lower level network element by synchronization link or by transmission line simultaneously, for its tracking lock.If our station can not receive the reference clock that transmits from the upper level network element, this network element local clock of providing this network element to use by built-in phase-locked oscillator itself so, and to next stage network element transmission clock signal.
From office clock three kinds of mode of operations are arranged usually in the synchronous digital network of principal and subordinate:
(1) normal mode of operation, i.e. tracking lock upper level clock pattern:
This moment, the clock reference from the office clock tracking lock transmitted from upper level, may be the master clock in the net, also may be the clock that upper level network element onboard clock source issues.
(2) maintenance pattern:
After all timing bases are lost, enter the maintenance pattern from office clock, the last frequency information of being stored utilize this moment timing reference signal to lose from the office clock source before, work as its timing base, that is to say from office clock memory function is arranged, provide the timing signal that conforms to former timing benchmark by memory function, to guarantee in long-time, having only very little frequency departure frequently with reference clock from clock frequency.But because the natural mode shape of oscillator can be drifted about at leisure, so the degree of precision clock that the kind working method provides can not last long, the clock accuracy of this kind mode of operation is only second to the clock accuracy of normal mode of operation.
(3) Switch mode:
When master clock breaks down, be switched to fully on the clock.
In the SDH net, the route of network timing all might change at any time, thereby its timing performance also may change at any time, thereby this just requires network element must have higher intelligence can determine whether timing source also is suitable for, whether need to search other more suitably timing sources etc., guaranteeing that rudimentary clock can only receive the timing of more high-grade or same grade clock, and to avoid forming the loop of timing signal, cause synchronous instability.In order to realize above-mentioned intelligent use, in the overhead byte of SDH, introduced S1 byte, i.e. synchronization status marker (SSM) byte.With the 5-8 bit of this byte by message coding showing the synchronous regime of this STM-N, and the protection that helps to carry out Synchronization Network is switched.
In the transmission network as shown in Figure 1, the BITS clock signal inserts by the external clock access port of network element 1 and network element 4, these two external BITS clocks are active and standby each other, satisfy G812 local clock a reference source quality requirement, and the synchronisation source of each network element and the configuration of clock source level are as shown in table 1.
Table 1:
In the time of operate as normal, the clock synchronization of whole transmission network is in the external BITS clock reference source of network element 1.When the optical fiber of 3 of network element 2 and network elements takes place to interrupt, the APS of synchronised clock will take place.Follow above-mentioned turning protocol, because what network element 4 was followed the tracks of is the clock of network element 3, therefore the network element 4 clock quality information that sends to network element 3 is " the clock source is unavailable ", be that S1 byte is 0XFF, so when network element 3 detects the west when lose in the synchronised clock source, network element 3 can not use the synchronisation source of the clock source of east orientation as our station, and can only use its onboard clock source as the clock reference source, and this information is passed to network element 4 by S1 byte, be that the S1 byte that network element 3 is passed to network element 4 is 0X0B, expression " synchronous equipment timing source (SETS) clock signal ".After network element 4 receives this information, find that it (was " G812 local office clock " originally that the synchronisation source quality of being followed the tracks of has reduced, be that S1 byte is 0X08), do not satisfy the requirement of the synchronisation source quality threshold that sets, so network element 4 need be chosen the clock reference source that conforms to quality requirements again, according to table 1, network element 4 can with the clock source have 4, the west to clock source, east orientation clock source, onboard clock source and external bits timing source.Obviously, have only east orientation clock source and external bits timing source to satisfy the requirement of quality threshold this moment.Because the rank in configuration east orientation clock source is than the rank height of external bits timing source, so network element 4 is finally chosen the synchronisation source of east orientation clock source as our station in the network element 4.After being switched to east orientation, the clock source of network element 3 east orientations becomes available the synchronisation source that network element 4 is followed the tracks of by the west.Obviously, in this moment clock source that can use of network element 3, the quality in east orientation clock source satisfies the requirement of quality threshold, and rank also is the highest, so network element 3 will be chosen the synchronisation source of east orientation clock source as our station.Finally, the clock tracing situation of whole transmission network will be as shown in Figure 2.
In said process, though the APS of synchronised clock finish, yet each network element can not show the clock status of this network element clearly and be in which kind of mode of operation, therefore, is unfavorable for the reason that the customer analysis fault produces.
Summary of the invention
Technical problem to be solved by this invention is which kind of mode of operation problem clock status and this network element that each network element in the transmission network can not obtain out this network element clearly are in when simulating fiber cut failure in the network analog system.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention provides a kind of method that obtains network element clock status and mode of operation when simulating fiber cut failure, may further comprise the steps:
Thereby A10, fault optical fiber ID is set in the optical transport network analogue system simulates corresponding fiber failure;
A20, read the active and standby clock chain circuit ID that database in the optical transport network analogue system obtains each network element;
A30, the active and standby clock chain circuit ID with described fault optical fiber ID and each network element compares successively, obtains the network element that clock chain circuit ID equals described fault optical fiber ID, obtains initial network element;
A40, iteration is upgraded the QL value of active and standby clock that network element clock with described initial network element is all second line of a couplet network elements of master clock successively, up to satisfying the iteration termination condition;
A50, successively with master clock in the steps A 40 be not the second line of a couplet network element of external clock as initial network element, repeating step A40;
A60, determine the clock work pattern of each network element according to the QL value of the active and standby clock of each network element, that is:
If the QL value of the master clock of network element equals its QL value that is equipped with clock, then this network element is in the maintenance mode of operation;
If the QL value of the master clock of network element is greater than its QL value that is equipped with clock, then this network element is in normal mode of operation;
If the QL value of the master clock of network element is equipped with the QL value of clock less than it, then this network element is in and switches mode of operation.
In said method, in the steps A 30, determine that the method for initial network element is as follows;
When (1) the master clock port of network element equals non-working port and is equipped with clock QL value greater than master clock QL value; Or,
(2), network element is equipped with that clock port equals non-working port and this network element works in clock module fully.
In said method, described iteration termination condition is one of following three kinds of conditions:
The master clock of condition 1, network element is an external clock;
Condition 2, network element are under normal mode, and standby port is the fault port;
Condition 3, network element are under switch status, and main port is the fault port.
In said method, in the steps A 40, begin iteration successively from the non-working port of network element and upgrade the active and standby clock QL value of second line of a couplet network element and may further comprise the steps:
A401, according to the network element clock information of network element record, judge whether the master clock of this network element is external clock, if external clock, then the clock QL value that is equipped with all network elements in the iteration set is updated to 2, this iteration is upgraded end; Otherwise change steps A 402;
A402, the master clock input port of judging this network element whether equals non-working port and whether it is equipped with clock QL value greater than master clock QL value, if satisfy above-mentioned condition then change steps A 403; Otherwise change steps A 406;
A403, judge being equipped with clock QL value and whether equaling 15 of this network element, if not then the master clock QL value of this network element being updated to 11, this iteration end; Otherwise change steps A 404;
Whether A404, this iteration are the 0th iteration, if not, then the master clock QL value with this network element is updated to 11, changes steps A 405; Otherwise, carry out iteration function, the master clock QL value of this network element is updated to 15, commentaries on classics steps A 405;
A405, obtain next network element, change steps A 404 and carry out next iteration;
A406, judge this network element be equipped with whether the input end of clock mouth equals non-working port and whether its master clock QL value equals 2, if satisfy condition then the clock QL value that is equipped with of this network element be updated to 15, this iteration end; Otherwise, change steps A 407;
Whether A407, the master clock input carbonyl mouth of judging this network element equal non-working port and its is equipped with clock QL value and whether equals 2, if satisfy condition, then the master clock QL value with this network element is updated to 15, this iteration end; Otherwise, change steps A 408;
A408, judge being equipped with the input end of clock mouth and whether equaling non-working port and its and be equipped with clock QL value and whether equal 2 of this network element, if satisfy condition then change steps A 409; Otherwise this iteration finishes;
A409, judge whether the master clock QL value of this network element equals 11, if then change step 405; Otherwise this iteration finishes.
The present invention, by a network element linking to each other with fault optical fiber as initial network element, the iteration renewal is the active and standby clock QL value of all second line of a couplet network elements of master clock with the clock of initial network element successively, the clock status of all network elements in the acquisition system, then according to the decision rule of clock switch, demonstrate the clock status of all network elements clearly and be in which kind of mode of operation, the reason that has made things convenient for the customer analysis fault to produce.
Description of drawings
Fig. 1 is the synchronous schematic diagram of principal and subordinate under the normal mode of operation;
Fig. 2 is the synchronous schematic diagram of principal and subordinate under the protection Switch mode;
Fig. 3 is the flow chart that iteration provided by the invention is upgraded the active and standby QL value of network element;
Fig. 4 is a network element mode of operation decision flowchart provided by the invention.
Embodiment
The invention provides a kind of in the network analog system, simulation is the clock status of all network elements and the method for mode of operation in the acquisition system during fiber cut failure, by a network element linking to each other with fault optical fiber as initial network element, according to iteration function, the iteration renewal is the master of all second line of a couplet network elements of master clock with the clock of initial network element successively, be equipped with clock QL value, again will be with this second line of a couplet network element as initial network element, in the same way respectively successively iteration upgrade the master of its all second line of a couplet network elements, be equipped with clock QL value, up to satisfying the finishing iteration condition, clock status by all network elements in the above method acquisition system, according to the decision rule of clock switch, determine the clock work pattern of all network elements then.
Specifically, method provided by the invention may further comprise the steps:
A10, in the optical transport network analogue system,, fault optical fiber ID simulates corresponding fiber failure by being set;
A20, read the active and standby clock chain circuit ID that optical transport network analogue system database obtains each network element;
A30, the active and standby clock chain circuit ID with described fault optical fiber ID and each network element compares successively, obtains the network element that clock chain circuit ID equals described fault optical fiber ID, obtains initial network element;
A40, iteration is upgraded the QL value of active and standby clock that network element clock with described initial network element is all second line of a couplet network elements of master clock successively, up to satisfying the iteration termination condition;
A50, successively with master clock in the steps A 40 be not the second line of a couplet network element of external clock as initial network element, repeating step A40;
A60, determine the clock work pattern of each network element according to the QL value of the active and standby clock of each network element, that is:
If the QL value of the master clock of network element equals its QL value that is equipped with clock, then this network element is in the maintenance mode of operation;
If the QL value of the master clock of network element is greater than its QL value that is equipped with clock, then this network element is in normal mode of operation;
If the QL value of the master clock of network element is equipped with the QL value of clock less than it, then this network element is in and switches mode of operation.
Wherein, in the steps A 30, the method of determining initial network element is as follows, and the master clock input port of network element equals the fault fiber port and is equipped with the QL value of the QL value of clock greater than master clock, and perhaps the input end of clock mouth fully of network element equals fault fiber port and this network element and works in and be equipped with clock module.
Among the present invention, iteration function is as follows:
Iteration variable in the iteration function is: master clock QL value iPriQLValue and be equipped with clock QL value iAlterQLValue.
The iteration termination condition is one of following three kinds of conditions:
The master clock of condition 1, network element is an external clock;
Condition 2, network element are under normal mode, and standby port is the fault port;
Condition 3, network element are under switch status, and main port is the fault port.
The iteration renewal process, at first, what the master clock link ID that the ID of failure judgement optical fiber equals this network element still equaled this network element is equipped with clock chain circuit ID, if the ID of fault optical fiber equals the link ID of the master clock of this network element, fault has taken place in the master clock that then shows this network element, this moment, the QL value of this network element became 11 from 2, so begin to search with this clock is the network element of master clock source, realize by function G etTopoLinkOppositeNe (), after finding, then call JudgeNeSwichOrNot () function iteration down successively, iteration finishes when the master clock of this network element is external clock.If find to such an extent that the clock of network element is not to be master clock source with this network element, the clock QL value iAlterQLValue that is equipped with that then will deposit each network element data in the network element clock data array becomes 2 from 15, simultaneously, the master clock iPriQLValue value with this network element becomes 15.This place should be noted that a problem, if be that the network element of master clock has been a switch status with this network element, then the clock QL value iAlterQLValue value that is equipped with of this network element should be 15.
If the ID of fault optical fiber equals the link ID that is equipped with clock of this network element, then fault has taken place in the clock that is equipped with of this network element, and the clock QL value that is equipped with in the timing topology body of this network element is remained 15 by iAlterQLValue.If the clock QL value that is equipped with in the timing topology body of this network element is 2 by iAlterQLValue, represent that this network element switches, and this moment this network element clock fully problem has taken place, clock need be poured into above the master clock.The iAlterQLValue value that is network element becomes 15 from 2, and its iPriQLValue value is 11, and then this time, network element became normal condition again.This place should be noted that: finding with this network element is the network element that is equipped with the clock source, once this process iteration is gone down.
After iteration finishes, if the iPriQLValue value of certain network element greater than the iAlterQLValue value, then this network element is a switch status.If the iPriQLValue value of certain network element is 15, the iAlterQLValue value is 15, and then this network element is a hold mode, other be normal condition.
Specifically, steps A 40 may further comprise the steps, and as shown in Figure 3, begins iteration successively from the non-working port of network element and upgrades the active and standby clock QL value of second line of a couplet network element and may further comprise the steps:
A401, according to the network element clock information of network element record, judge whether the master clock of this network element is external clock, if external clock, then the clock QL value that is equipped with all network elements in the iteration set is updated to 2, this iteration is upgraded end; Otherwise change steps A 402;
A402, the master clock input port of judging this network element whether equals non-working port and whether it is equipped with clock QL value greater than master clock QL value, if satisfy above-mentioned condition then change steps A 403; Otherwise change steps A 406;
A403, judge being equipped with clock QL value and whether equaling 15 of this network element, if not then the master clock QL value of this network element being updated to 11, this iteration end; Otherwise change steps A 404;
Whether A404, this iteration are the 0th iteration, if not, then the master clock QL value with this network element is updated to 11, changes steps A 405; Otherwise, carry out iteration function, the master clock QL value of this network element is updated to 15, commentaries on classics steps A 405;
A405, obtain next network element, change steps A 404 and carry out next iteration;
A406, judge this network element be equipped with whether the input end of clock mouth equals non-working port and whether its master clock QL value equals 2, if satisfy condition then the clock QL value that is equipped with of this network element be updated to 15, this iteration end; Otherwise, change steps A 407;
Whether A407, the master clock input carbonyl mouth of judging this network element equal non-working port and its is equipped with clock QL value and whether equals 2, if satisfy condition, then the master clock QL value with this network element is updated to 15, this iteration end; Otherwise, change steps A 408;
A408, judge being equipped with the input end of clock mouth and whether equaling non-working port and its and be equipped with clock QL value and whether equal 2 of this network element, if satisfy condition then change steps A 409; Otherwise this iteration finishes;
A409, judge whether the master clock QL value of this network element equals 11, if then change step 405; Otherwise this iteration finishes.
Below in conjunction with instantiation illustrated in figures 1 and 2 the present invention is made detailed explanation:
As depicted in figs. 1 and 2, in when, between network element 2 and the network element 3 fiber cut failure taking place when, because the master clock port of network element 3 equals non-working port, therefore, be that the QL value of active and standby clock of the network element of master clock is carried out iteration and upgraded to clock with network element 3 with network element 3 as initial network element, be the QL value that iteration is upgraded the active and standby clock of network element 4, the active and standby clock QL value of network element 4 is updated to 2 and 11 by 2 and 15 respectively; Judge whether to satisfy the condition of finishing iteration after the renewal, owing to do not satisfy, the clock that needs the continuation iteration to upgrade with network element 4 is the network element of master clock, so master of network element 5, be equipped with clock QL value and be updated to 2 and 11 by 2 and 15 respectively, at this moment, still do not satisfy the condition of finishing iteration, upgrade network element 6, the master of network element 6 so continue iteration, be equipped with clock QL value and be updated to 2 and 11 by 2 and 15 respectively, at this moment, still do not satisfy the condition of finishing iteration, upgrade network element 1, the master of network element 1 so continue iteration, be equipped with clock QL value and be updated to 2 and 11 by 2 and 15 respectively, because the master clock of network element 1 is external clock BITS, therefore, satisfy the condition of finishing iteration, iteration finishes.
After iteration finishes, can judge the state of network element according to the clock status value set of each network element, in conjunction with Fig. 4, at first search the clock of all network elements, the active and standby clock QL value of all network elements is as shown in table 2.
Table 2:
| ?NE1 | NE2 | NE3 | NE4 | NE5 | NE6 | |
| Master clock QL value | ?2 | 11 | 11 | 11 | 11 | 11 |
| Be equipped with clock QL value | ?11 | 15 | 15 | 15 | 15 | 15 |
Can find by analyzing: the master clock QL value of network element may be 2,11 or 15; May be 2 or 15 and be equipped with clock QL value,, determine the clock work pattern of all network elements then successively according to the clock switch decision rule of following regulation:
(1), main with QL value be 2, with the QL value be 15 or lead with the QL value be 11, standby QL value is 15, this network element is in normal mode;
(2), main with QL value be 15, standby QL value be 2 or lead with the QL value be 11, standby QL value is 2, this network element is in Switch mode;
(3), main with the QL value be 15, standby QL value is 15, this network element is in the maintenance pattern.
That is:
If the QL value of the master clock of network element equals its QL value that is equipped with clock, then this network element is in the maintenance mode of operation;
If the QL value of the master clock of network element is greater than its QL value that is equipped with clock, then this network element is in normal mode of operation;
If the QL value of the master clock of network element is equipped with the QL value of clock less than it, then this network element is in and switches mode of operation.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (4)
1. obtain the method for network element clock status and mode of operation when simulating fiber cut failure, it is characterized in that may further comprise the steps:
A10, in the optical transport network analogue system,, fault optical fiber ID simulates corresponding fiber failure by being set;
A20, read the active and standby clock chain circuit ID that optical transport network analogue system database obtains each network element;
A30, the active and standby clock chain circuit ID with described fault optical fiber ID and each network element compares successively, obtains the network element that clock chain circuit ID equals described fault optical fiber ID, obtains initial network element;
A40, iteration is upgraded the QL value of active and standby clock that network element clock with described initial network element is all second line of a couplet network elements of master clock successively, up to satisfying the iteration termination condition;
A50, successively with master clock in the steps A 40 be not the second line of a couplet network element of external clock as initial network element, repeating step A40;
A60, determine the clock work pattern of each network element according to the QL value of the active and standby clock of each network element, that is:
If the QL value of the master clock of network element equals its QL value that is equipped with clock, then this network element is in the maintenance mode of operation;
If the QL value of the master clock of network element is greater than its QL value that is equipped with clock, then this network element is in normal mode of operation;
If the QL value of the master clock of network element is equipped with the QL value of clock less than it, then this network element is in and switches mode of operation.
2. obtain the method for network element clock status and mode of operation during simulation fiber cut failure as claimed in claim 1, it is characterized in that, in steps A 30, determine that the method for initial network element is as follows;
When (1) the master clock port of network element equals non-working port and is equipped with clock QL value greater than master clock QL value; Or,
(2), network element is equipped with that clock port equals non-working port and this network element works in clock module fully.
3. obtain the method for network element clock status and mode of operation during simulation fiber cut failure as claimed in claim 1, it is characterized in that described iteration termination condition is one of following three kinds of conditions:
The master clock of condition 1, network element is an external clock;
Condition 2, network element are under normal mode, and standby port is the fault port;
Condition 3, network element are under switch status, and main port is the fault port.
4. obtain the method for network element clock status and mode of operation during simulation fiber cut failure as claimed in claim 1, it is characterized in that, in the steps A 40, begin iteration successively from the non-working port of network element and upgrade the active and standby clock QL value of second line of a couplet network element and may further comprise the steps:
A401, according to the network element clock information of network element record, judge whether the master clock of this network element is external clock, if external clock, then the clock QL value that is equipped with all network elements in the iteration set is updated to 2, this iteration is upgraded end; Otherwise change steps A 402;
A402, the master clock input port of judging this network element whether equals non-working port and whether it is equipped with clock QL value greater than master clock QL value, if satisfy above-mentioned condition then change steps A 403; Otherwise change steps A 406;
A403, judge being equipped with clock QL value and whether equaling 15 of this network element, if not then the master clock QL value of this network element being updated to 11, this iteration end; Otherwise change steps A 404;
Whether A404, this iteration are the 0th iteration, if not, then the master clock QL value with this network element is updated to 11, changes steps A 405; Otherwise, carry out iteration function, the master clock QL value of this network element is updated to 15, commentaries on classics steps A 405;
A405, obtain next network element, change steps A 404 and carry out next iteration;
A406, judge this network element be equipped with whether the input end of clock mouth equals non-working port and whether its master clock QL value equals 2, if satisfy condition then the clock QL value that is equipped with of this network element be updated to 15, this iteration end; Otherwise, change steps A 407;
Whether A407, the master clock input carbonyl mouth of judging this network element equal non-working port and its is equipped with clock QL value and whether equals 2, if satisfy condition, then the master clock QL value with this network element is updated to 15, this iteration end; Otherwise, change steps A 408;
A408, judge being equipped with the input end of clock mouth and whether equaling non-working port and its and be equipped with clock QL value and whether equal 2 of this network element, if satisfy condition then change steps A 409; Otherwise this iteration finishes;
A409, judge whether the master clock QL value of this network element equals 11, if then change step 405; Otherwise this iteration finishes.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108712285A (en) * | 2018-05-18 | 2018-10-26 | 国家电网公司信息通信分公司 | A kind of analog simulation method and device of optical transport network |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1352500A (en) * | 2000-11-06 | 2002-06-05 | 深圳市中兴通讯股份有限公司 | Automatic clock line protecting method in implementing digital transmission group net |
| CN101335609A (en) * | 2007-06-26 | 2008-12-31 | 华为技术有限公司 | Network time clock tracking method, network apparatus and network system |
| CN101499930A (en) * | 2009-03-04 | 2009-08-05 | 北京邮电大学 | Preset protection ring distributed configuration protocol based on local diffusion type |
-
2011
- 2011-06-22 CN CN201110168261.0A patent/CN102195709B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1352500A (en) * | 2000-11-06 | 2002-06-05 | 深圳市中兴通讯股份有限公司 | Automatic clock line protecting method in implementing digital transmission group net |
| CN101335609A (en) * | 2007-06-26 | 2008-12-31 | 华为技术有限公司 | Network time clock tracking method, network apparatus and network system |
| CN101499930A (en) * | 2009-03-04 | 2009-08-05 | 北京邮电大学 | Preset protection ring distributed configuration protocol based on local diffusion type |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108712285A (en) * | 2018-05-18 | 2018-10-26 | 国家电网公司信息通信分公司 | A kind of analog simulation method and device of optical transport network |
| CN108712285B (en) * | 2018-05-18 | 2021-06-18 | 国家电网公司信息通信分公司 | Analog simulation method and device of optical transmission network |
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| CN102195709B (en) | 2014-06-04 |
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