CN102195678B - Power line carrier signal demodulation circuit and microcontroller - Google Patents
Power line carrier signal demodulation circuit and microcontroller Download PDFInfo
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Abstract
The invention provides a power line carrier signal demodulation circuit and a microcontroller. The power line carrier signal demodulation circuit comprises a processing module, a demodulation circuit and a grating module, wherein the demodulation circuit is connected with the processing module; the grating module is connected with the processing module and provides a selection signal for the processing module; the modulation circuit at least comprises a first modulation unit and a second modulation unit; therefore, the problem that the power line carrier signal modulation circuit in the prior art has a single demodulation mode can be solved, and the power line carrier signal demodulation circuit disclosed by the prior art can support multiple demodulation modes, so that users can select demodulation modes flexibly, the use cost for users can be reduced effectively, and the use convenience for users can be improved.
Description
Technical field
The embodiment of the present invention relates to power-line carrier communication field, relates in particular to a kind of power line carrier signal demodulating circuit and microcontroller.
Background technology
Power line carrier (Power Line Carrier; Hereinafter to be referred as: PLC) communication refers to take power line as information transmitting medium, utilizes ZAP, and signal of communication is modulated in electrical network and is transmitted, and realizes a kind of communication mode of transmission of information between each node of electrical network.At present, the microcontroller chip of existing power-line carrier communication system has multiple, and normally used have two kinds, and the first is supported frequency shift keying (Frequency Shift Keying; Hereinafter to be referred as the FSK) microcontroller chip of modulating/demodulating mode, it two is to support phase shift keying (Phase Shift Keying; Hereinafter to be referred as: the PSK) microcontroller chip of modulating/demodulating mode.In addition, industry can also be used other modulating/demodulating mode, at this, will not enumerate.
In prior art, be used for the microcontroller chip of power-line carrier communication system or be only applicable to FSK mode, be only applicable to PSK mode, therefore, user can only modulating/demodulating mode as required buy corresponding microcontroller chip, once will change the modulating/demodulating mode of communication, will change corresponding hardware circuit design on the one hand, also to again choose on the other hand the microcontroller chip of other modulating/demodulating modes, thereby bring great inconvenience to user's use.
Summary of the invention
The embodiment of the present invention provides a kind of power line carrier signal demodulating circuit and microcontroller, in order to have solved the relatively single problem of demodulation mode of power line carrier signal demodulating circuit in prior art, can support multiple demodulation mode, thereby user can select demodulation mode so that carrier signal is carried out to demodulation flexibly.
The embodiment of the present invention provides a kind of power line carrier signal demodulating circuit, comprising: processing module and the demodulator circuit being connected with described processing module; It is characterized in that, also comprise: gating module, described gating module is connected with described processing module, to described processing module, provides selection signal; Described demodulator circuit at least consists of the first demodulating unit and the second demodulating unit.
The embodiment of the present invention provides a kind of microcontroller, comprises central processing module, processing module and the demodulator circuit being connected with described processing module; Wherein, also comprise: gating module, described gating module is connected with described processing module, to described processing module, provides selection signal; Described demodulator circuit at least consists of the first demodulating unit and the second demodulating unit.
Power line carrier signal demodulating circuit and the microcontroller of the embodiment of the present invention, by gating module, to processing module, provide selection signal, for processing module, the carrier signal of input is carried out to orthogonal processing and filtering processing, and the selection signal providing according to gating module, orthogonal processing and filtering orthogonal signalling after treatment are outputed to demodulating unit corresponding to selection signal, so that this demodulating unit carries out demodulation to these orthogonal signalling, and export restituted signal, thereby it is relatively single to have changed in prior art the demodulation mode of power line carrier signal demodulating circuit, can support multiple demodulation mode, and then make user can select flexibly demodulation mode, effectively reduce user's use cost, also improved the convenience that user uses.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of the power line carrier signal demodulating circuit that Fig. 1 provides for the embodiment of the present invention one;
The structural representation of the power line carrier signal demodulating circuit that Fig. 2 provides for the embodiment of the present invention two;
The circuit theory diagrams of the power line carrier signal demodulating circuit that Fig. 3 provides for the embodiment of the present invention three;
The structural representation of the microcontroller that Fig. 4 provides for the embodiment of the present invention four.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment mono-
The structural representation of the power line carrier signal demodulating circuit that Fig. 1 provides for the embodiment of the present invention one, as shown in Figure 1, this electric wire carrier signal demodulator circuit comprises: gating module 11, processing module 12 and demodulator circuit 13; Wherein, gating module 11 is connected with processing module 12, to processing module 12, provides selection signal.Demodulator circuit 13 at least consists of the first demodulating unit 131 and the second demodulating unit 132.The first demodulating unit 131 is connected with processing module 12 respectively with the second demodulating unit 132.
In the present embodiment, this gating module 11 is specially mask register, and in actual applications, this mask register is arranged on central processing module (Central Processing Unit; Hereinafter to be referred as: CPU), and can utilize this mask register preserve power line carrier demodulation mode algorithm and and selection signal corresponding to this algorithm, for example this selection signal can be the state informations such as " 0 " or " 1 " of Digital Logic, this selection signal is used to indicate: power line carrier signal demodulating circuit will carry out demodulation to the carrier signal of input according to algorithm corresponding to which type of demodulation mode, and exports restituted signal.There has is this for determining the mask register of demodulation mode, when separating timing to the carrier signal of input, the specific implementation of mask register is: CPU is by access mask register, revise the state information of the mask register of power line carrier signal demodulating circuit, to determine power line carrier signal demodulating circuit is according to which kind of demodulation mode, carrier signal to input is carried out demodulation, be specially, CPU calls the demodulating algorithm corresponding to state information of pre-stored from mask register, control power line carrier signal demodulating circuit the carrier signal of input is carried out to demodulation.It should be noted which kind of demodulation mode mask register selects specifically can arrange according to the environment of power-line carrier communication system operation.
In the present embodiment, by gating module, to processing module, provide selection signal, for processing module, the carrier signal of input is carried out to orthogonal processing and filtering processing, and the selection signal providing according to gating module, orthogonal processing and filtering orthogonal signalling after treatment are outputed to demodulating unit corresponding to selection signal, so that this demodulating unit carries out demodulation to these orthogonal signalling, and export restituted signal, thereby it is relatively single to have changed in prior art the demodulation mode of power line carrier signal demodulating circuit, can support multiple demodulation mode, and then make user can select flexibly demodulation mode, effectively reduce user's use cost, also improved the convenience that user uses.
Embodiment bis-
The structural representation of the power line carrier signal demodulating circuit that Fig. 2 provides for the embodiment of the present invention two, the present embodiment is take above-described embodiment one as basis, as shown in Figure 2, the processing module 12 of this power line carrier signal demodulating circuit comprises: digital oscillation control unit 121, the first mixing and filtering unit 122 and the second mixing and filtering unit 123; Wherein digital oscillation control unit 121 is connected with gating module 11, for generation of and export the first local orthogonal signalling and the second local orthogonal signalling; The first mixing and filtering unit 122 is connected with digital oscillation control unit 121, for utilizing the first local orthogonal signalling to carry out orthogonal processing and filtering processing to carrier signal, and exports the first orthogonal signalling to described the first demodulating unit 131; The second mixing and filtering unit 123, is connected with digital oscillation control unit 121, for utilizing the second local orthogonal signalling to carry out orthogonal processing and filtering processing to carrier signal, and exports the first orthogonal signalling to the second demodulating unit 132.
In the present embodiment, digital oscillation control unit 121 is specially digital oscillating controller (NumericalControlled Oscillator; Hereinafter to be referred as: NCO) 121, like this, the first local orthogonal signalling that NCO 121 exports specifically can be the cosine signal that NCO produces, and the second local orthogonal signalling specifically can be the sinusoidal signal that NCO produces; The first mixing and filtering unit 122 comprises multiplier and low pass filter (Low PassFilter; Hereinafter to be referred as: LPF); The second mixing and filtering unit 123 also comprises multiplier and LPF.More specifically, in the present embodiment, LPF can be finite impulse response (Finite Impulse Response; Hereinafter to be referred as: FIR) filter or infinite impulse response (Infinite Impulse Response; Hereinafter to be referred as: IIR) filter.
In the present embodiment, the workflow of processing module 12 is: the carrier signal of input can specifically be divided into I, Q two-way, and two paths of signals is carrier signal; Wherein, the cosine signal that the carrier signal on I road is exported by multiplier and the NCO 121 of the first mixing and filtering unit 122 multiplies each other, to obtain the first orthogonal signalling, these first orthogonal signalling are specifically as follows homophase carrier signal, and these first orthogonal signalling are carried out to filtering by the LPF of the first mixing and filtering unit 122, to remove the high-frequency signal in the first orthogonal signalling, thereby obtain filtered the first orthogonal signalling.The sinusoidal signal that Q road carrier signal is exported by multiplier and the NCO 121 of the second mixing and filtering unit 123 multiplies each other, to obtain the second orthogonal signalling, these second orthogonal signalling are specifically as follows quadrature carrier signal, and these second orthogonal signalling are carried out to filtering by the LPF of the second mixing and filtering unit 123, to remove the high-frequency signal in the second orthogonal signalling, thereby obtain filtered the second orthogonal signalling.
For example, for I road carrier signal, this carrier signal comprises two frequencies, is respectively 125KHz and 135KHz.The frequency of the cosine signal that meanwhile, NCO 121 exports is 130KHz; The present embodiment is take the frequency of carrier signal as 125KHz is as example, when the cosine signal of exporting by multiplier and the NCO 121 of the first mixing and filtering unit 122 when the frequency carrier signal that is 125KHz multiplies each other, the frequency of obtaining the first orthogonal signalling is respectively 255KHz and 5KHz, then by the LPF of the first mixing and filtering unit 122, carry out filtering, signal take rejection frequency as 255KHz, thus effectively removed the interference of high-frequency signal to the first orthogonal signalling.
In the present embodiment, by digital oscillation control unit, the first mixing and filtering unit and the second mixing and filtering unit are set, thereby the carrier signal to input is carried out orthogonal processing, obtain respectively the first orthogonal signalling and the second orthogonal signalling, and the first orthogonal signalling and the second orthogonal signalling have been carried out to filtering processing, thereby effectively removed the interference of high frequency.
In the present embodiment, take the alternative demodulation mode of power line carrier signal demodulating circuit, be respectively FSK demodulation mode and PSK demodulation mode as example, introduce in detail technical scheme of the present invention, but it should be noted that, the alternative demodulation mode of this power line carrier signal demodulating circuit is not limited to two kinds of demodulation modes that the present invention lifts, can also comprise other demodulation mode, for example ASK demodulation mode.
The selection signal providing to processing module 12 when gating module 11 is the carrier signal of input to be carried out to FSK separate timing, and the first demodulating unit 131 comprises: first postpones subelement 1311, the second delay subelement 1312, the first mixing subelement 1313, the second mixing subelement 1314 and subtraction subelement 1315; Wherein, first postpones subelement 1311 is connected with the first mixing and filtering unit 122, for the first orthogonal signalling that receive are carried out to delay disposal, to obtain the first delay orthogonal signalling; Second postpones subelement 1312 is connected with the second mixing and filtering unit 123, for the second orthogonal signalling that receive are carried out to delay disposal, to obtain the second delay orthogonal signalling; The first mixing subelement 1313 and first postpones subelement 1311 and is connected, for the first delay orthogonal signalling and the second orthogonal signalling are multiplied each other, to obtain the first crossbar signal; The second mixing subelement 1314, is connected with the second delay subelement 1312, for the second delay orthogonal signalling and the first orthogonal signalling are multiplied each other, to obtain the second crossbar signal; Subtraction subelement 1315, is connected with the second mixing subelement 1314 with the first mixing subelement 1313, after the first crossbar signal and the second crossbar signal are subtracted each other, obtains the first restituted signal, and by the first restituted signal output.
Further, the selection signal providing when processing module 12 is the carrier signal of input to be carried out to PSK separate timing, and the second demodulating unit 132 comprises: the 3rd mixing subelement 1321 and loop filtering subelement 1322; Wherein, the 3rd mixing subelement 1321 is connected with the second mixing and filtering unit 123 with the first mixing and filtering unit 122, for the first orthogonal signalling and the second orthogonal signalling are multiplied each other, to obtain the 3rd orthogonal signalling; Loop filtering subelement 1322, be connected with the 3rd mixing subelement 1321, digital oscillation control unit 121 and gating module 11, for the 3rd orthogonal signalling are carried out to filtering processing, and the 3rd orthogonal signalling are exported to digital oscillation control unit 121, to obtain the second restituted signal.Concrete, in digital oscillation control unit 121, specifically comprise that adder, K register and NCO control subelement.Because the numerical value of storing in K register is the settings of the numerical frequency of digital oscillation control unit 121, therefore by changing the numerical value of storing in K register, adjust the sinusoidal signal producing of digital oscillation control unit 121 and the frequency of cosine signal, and the sinusoidal signal after adjusting is exported as the second restituted signal.More specifically implementation is: the numerical value of storing in the 3rd orthogonal signalling of filtering processing and K register is input in the adder of digital oscillation control unit 121, adder is carried out phase-accumulated according to the numerical value of storing in K register to the phase information of the 3rd orthogonal signalling, and send to NCO to control subelement the phase information after cumulative, for NCO, control subelement according to the phase information after cumulative, the sinusoidal signal that furnishing NCO produces and the frequency of cosine signal, to reach sinusoidal signal and cosine signal, follow the tracks of the phase information after upper accumulation, and the sinusoidal signal after adjusting frequency is multiplied each other by the multiplier of the first mixing and filtering unit 122 and the homophase carrier signal of input, obtain the second restituted signal, and the second restituted signal obtaining is carried out to filtering by the LPF of the first mixing and filtering unit 122, with filtering high-frequency signal, thereby effectively removed the interference of high-frequency signal to the second restituted signal.
Further, this power line carrier signal demodulating circuit also comprises: the first demodulation switch module 14, be connected with processing module 12 with the first demodulating unit 131, and for controlling the first demodulating unit 131, be connected or disconnect with processing module 12.Specific implementation is: the selection signal providing to processing module 12 when gating module 11 is the carrier signal of input to be carried out to FSK separate timing, and the first demodulation switch module 14 closures, so that the first demodulating unit 131 is connected with processing module 12; The selection signal providing to processing module 12 when gating module 11 is the carrier signal of input to be carried out to PSK separate timing, the first demodulation switch module 14 disconnects, so that the first demodulating unit 131 disconnects mutually with processing module 12, thereby carrying out PSK solution timing, the first demodulating unit 131 does not need work, effectively raises the useful life of power line carrier signal demodulating circuit.
The power line carrier signal demodulating circuit that possesses above-mentioned functions provided by the present invention is on concrete circuit is realized, above-mentioned module, unit and subelement can integrate, form an overall hardware circuit or chip, also can adopt the form of separation to be arranged among concrete power line carrier signal demodulating circuit, no matter adopt which kind of concrete circuit or semiconductors, the technological know-how that one of ordinary skill in the art possess based on it can need to be selected according to concrete product design.Wherein a kind of optional embodiment is described below.
Embodiment tri-
The circuit theory diagrams of the demodulator circuit that Fig. 3 provides for the embodiment of the present invention three, as shown in Figure 3, this power line carrier signal demodulating circuit is by mask register 301, the first multiplier 302, the second multipliers 303, the 3rd multiplier 304, the 4th multiplier 305, the 5th multiplier 306, a LPF 307, the 2nd LPF 308, NCO 309, loop filter 310, the first delay cell (Z
-1) 311, the second delay cell (Z
-1) 312 and subtracter 313 form.
The workflow of this power line carrier signal demodulating circuit is specially: when mask register 301 configuration bit set, loop filter 310 conductings, it is the Costas loop in mask register 301 gating circuits, now, power line carrier signal demodulating circuit is selected PSK demodulation mode, carrier signal is divided into I, Q two-way, be carrier signal I and carrier signal Q, wherein, carrier signal I is through the first multiplier 302, the cosine signal that produces with NCO 309 (be the embodiment of the present invention described in the first local orthogonal signalling) multiplies each other, obtain the first orthogonal signalling, these first orthogonal signalling are homophase carrier signal, again these first orthogonal signalling are passed through to a LPF 307, filtering high-frequency signal, obtain the first orthogonal signalling I
n.Carrier signal Q is through the second multiplier 303, the sinusoidal signal that produces with NCO 309 (be the embodiment of the present invention described in the second local orthogonal signalling) multiplies each other, obtain the second orthogonal signalling, these second orthogonal signalling are quadrature carrier signal, again these second orthogonal signalling are passed through to the 2nd LPF 308, filtering high-frequency signal, obtains the second orthogonal signalling Q
n, the first orthogonal signalling I
nwith the second orthogonal signalling Q
nafter multiplying each other by the 5th multiplier 306, export the 3rd orthogonal signalling, the 3rd orthogonal signalling are carried out filtering processing through loop filter 310 again, and filtered the 3rd orthogonal signalling are exported to NCO 309, concrete, NCO 309 mainly comprises that adder, K register and NCO control subelement.Wherein, the numerical value of storing in the 3rd orthogonal signalling and K register first sends to adder, so that adder is carried out accumulation of phase according to the numerical value of storing in K register to the phase information of the 3rd orthogonal signalling, and send to NCO to control subelement the phase information after cumulative, NCO controls subelement according to the phase information after cumulative, adjust NCO and control the sinusoidal signal of subelement generation and the frequency of cosine signal, so that sinusoidal signal and cosine signal are followed the tracks of the phase information after upper adding up, sinusoidal signal after adjusting frequency is multiplied each other by the first multiplier 302 and the homophase carrier signal of input simultaneously, obtain the second restituted signal, and the second restituted signal is passed through to a LPF 307, thereby the high-frequency signal of filtering the second restituted signal, like this, filtered the second restituted signal of exporting from a LPF 307 is the signal of exporting by PSK demodulation mode.
When mask register 301 configuration bit reset, loop filter 310 disconnects, and disconnects Costas loop, and now, power line carrier signal demodulating circuit is selected FSK demodulation mode, and carrier signal is divided into I, Q two-way, i.e. carrier signal I and carrier signal Q.Carrier signal I is through the first multiplier 302, the cosine signal that produces with NCO 309 (be the embodiment of the present invention described in the first local orthogonal signalling) multiplies each other, obtain the first orthogonal signalling, these first orthogonal signalling are homophase carrier signal, again these first orthogonal signalling are passed through to a LPF 307, filtering high-frequency signal, obtains the first orthogonal signalling I
n.Quadrature carrier signal Q is through the second multiplier 303, the sinusoidal signal that produces with NCO 309 (be the embodiment of the present invention described in the second local orthogonal signalling) multiplies each other, obtain the second orthogonal signalling, these second orthogonal signalling are quadrature carrier signal, again these second orthogonal signalling are passed through to the 2nd LPF 308, filtering high-frequency signal, obtains the second orthogonal signalling Q
n.The first orthogonal signalling I
nwith the second orthogonal signalling Q
nthrough the first delay cell 311 and the second delay cell 312, carry out delay disposal respectively, obtain the first delay orthogonal signalling I
n-1with the second delay orthogonal signalling Q
n-1, first postpones orthogonal signalling I
n-1by the 3rd multiplier 304 and the second orthogonal signalling Q
nmultiply each other, obtain the first crossbar signal I
n1.Second postpones orthogonal signalling Q
n-1by the 4th multiplier 305 and the first orthogonal signalling I
nmultiply each other, obtain the second crossbar signal Q
n1, the first crossbar signal I
n1with the second crossbar signal Q
n1after subtracter 313 subtracts each other, obtain the first restituted signal output, this first restituted signal is the signal of exporting by FSK demodulation mode.
Embodiment tetra-
The structural representation of the microcontroller that Fig. 4 provides for the embodiment of the present invention four, as shown in Figure 4, this microcontroller comprises: CPU 41, processing module 42, the demodulator circuit (not drawing) and the gating module 44 that are connected with processing module 42.Wherein, demodulator circuit at least consists of the first demodulating unit 431 and the second demodulating unit 432; Gating module 44 is connected with processing module 42, to processing module 42, provides selection signal.
Further, this microcontroller also comprises: input-output unit 45, for receiving the carrier signal of ancillary equipment input, and inputs to processing module 42 by carrier signal; Or the first restituted signal or second restituted signal of receiving demodulation circuit output, and this first restituted signal or the second restituted signal are carried out exporting to ancillary equipment after software algorithm processing.Concrete, input-output unit 45 can be specially the pin of the chip of microcontroller, and for receiving the carrier signal of ancillary equipment input, and the first restituted signal that demodulation is obtained or the second restituted signal are exported to ancillary equipment by input-output unit 45.In order to improve demodulation performance, in the present embodiment, adopt software algorithm to process the first restituted signal or the second restituted signal, then the first restituted signal after treatment or the second restituted signal are exported to ancillary equipment by input-output unit 45.Concrete, software algorithm is specially software spread spectrum algorithm, for example, adopt 15 spreading codes to process restituted signal.
In the present embodiment, microcontroller provides selection signal by gating module to processing module, for processing module, the carrier signal of input is carried out to orthogonal processing and filtering processing, and the selection signal providing according to gating module, orthogonal processing and filtering orthogonal signalling after treatment are outputed to demodulating unit corresponding to selection signal, so that this demodulating unit carries out demodulation to these orthogonal signalling, and export restituted signal, thereby it is relatively single to have changed in prior art the demodulation mode of power line carrier signal demodulating circuit, can support multiple demodulation mode, and then make user can select flexibly demodulation mode, effectively reduce user's use cost, also improved the convenience that user uses.
Further, processing module 42 specifically comprises: digital oscillation control unit 421, the first mixing and filtering unit 422 and the second mixing and filtering unit 423; Wherein digital oscillation control unit 421 is connected with gating module 44, for generation of and export the first local orthogonal signalling and the second local orthogonal signalling; The first mixing and filtering unit 422 is connected with digital oscillation control unit 421, for utilizing the first local orthogonal signalling to carry out orthogonal processing and filtering processing to carrier signal, and exports the first orthogonal signalling to described the first demodulating unit 431; The second mixing and filtering unit 423, is connected with digital oscillation control unit 421, for utilizing the second local orthogonal signalling to carry out orthogonal processing and filtering processing to carrier signal, and exports the first orthogonal signalling to the second demodulating unit 432.
In the present embodiment, digital oscillation control unit 421 is specially digital oscillating controller (NumericalControlled Oscillator; Hereinafter to be referred as: NCO) 421, like this, the first local orthogonal signalling that NCO 421 exports specifically can be the cosine signal that NCO 421 produces, and the second local orthogonal signalling specifically can be the sinusoidal signal that NCO 421 produces; The first mixing and filtering unit 422 comprises multiplier and LPF; The second mixing and filtering unit 423 also comprises multiplier and LPF.More specifically, in the present embodiment, LPF can be FIR filter or iir filter.
In the present embodiment, the workflow of processing module 42 is: the carrier signal of input can specifically be divided into I, Q two-way, and two paths of signals is carrier signal; Wherein, the cosine signal that I road carrier signal is exported by multiplier and the NCO 421 of the first mixing and filtering unit 422 multiplies each other, to obtain the first orthogonal signalling, these first orthogonal signalling are specifically as follows homophase carrier signal, and these first orthogonal signalling are carried out to filtering by the LPF of the first mixing and filtering unit 422, to remove the high-frequency signal in the first orthogonal signalling, thereby obtain filtered the first orthogonal signalling.The sinusoidal signal that Q road carrier signal is exported by multiplier and the NCO 421 of the second mixing and filtering unit 423 multiplies each other, to obtain the second orthogonal signalling, these second orthogonal signalling are specifically as follows quadrature carrier signal, and these second orthogonal signalling are carried out to filtering by the LPF of the second mixing and filtering unit 423, to remove the high-frequency signal in the second orthogonal signalling, thereby obtain filtered the second orthogonal signalling.
Further, the first demodulating unit 431 is specially carrier signal is carried out to FSK demodulation, and it comprises: first postpones subelement 4311, the second delay subelement 4312, the first mixing subelement 4313, the second mixing subelement 4314 and subtraction subelement 4315; Wherein, first postpones subelement 4311 is connected with the first mixing and filtering unit 422, for the first orthogonal signalling that receive are carried out to delay disposal, to obtain the first delay orthogonal signalling; Second postpones subelement 4312 is connected with the second mixing and filtering unit 423, for the second orthogonal signalling that receive are carried out to delay disposal, to obtain the second delay orthogonal signalling; The first mixing subelement 4313 and first postpones subelement 4311 and is connected, for the first delay orthogonal signalling and the second orthogonal signalling are multiplied each other, to obtain the first crossbar signal; The second mixing subelement 4314, is connected with the second delay subelement 4312, for the second delay orthogonal signalling and the first orthogonal signalling are multiplied each other, to obtain the second crossbar signal; Subtraction subelement 4315, is connected with the second mixing subelement 4314 with the first mixing subelement 4313, after the first crossbar signal and the second crossbar signal are subtracted each other, obtains the first restituted signal, and by the first restituted signal output.
Further, the second demodulating unit 432 carries out PSK demodulation to carrier signal, and it comprises: the 3rd mixing subelement 4321 and loop filtering subelement 4322; Wherein, the 3rd mixing subelement 4321 is connected with the second mixing and filtering unit 423 with the first mixing and filtering unit 422, for the first orthogonal signalling and the second orthogonal signalling are multiplied each other, to obtain the 3rd orthogonal signalling; Loop filtering subelement 4322, be connected with the 3rd mixing subelement 4321, digital oscillation control unit 421 and gating module 44, for the 3rd orthogonal signalling are carried out to filtering processing, and the 3rd orthogonal signalling are exported to digital oscillation control unit 421, to obtain the second restituted signal.
In addition, this microcontroller also comprises in the present embodiment: the first demodulation switch module 46, be connected with processing module 42 with the first demodulating unit 431, and for controlling the first demodulating unit 431, be connected or disconnect with processing module 42.Specific implementation is: the selection signal providing to processing module 42 when gating module 44 is the carrier signal of input to be carried out to FSK separate timing, and the first demodulation switch module 46 closures, so that the first demodulating unit 431 is connected with processing module 42; The selection signal providing to processing module 42 when gating module 44 is the carrier signal of input to be carried out to PSK separate timing, the first demodulation switch module 46 disconnects, so that the first demodulating unit 431 disconnects mutually with processing module 42, thereby carrying out PSK solution timing, the first demodulating unit 431 does not need work, effectively raises the useful life of power line carrier signal demodulating circuit.
Further, in the present embodiment, gating module 44 is specially mask register, its input is connected with CPU 41, its output is connected with digital oscillation control unit 421 with loop filtering subelement 4322, the control command of processing for receiving central authorities, to provide selection signal to processing module 42.When the selection signal that mask register provides to processing module 42, for carrier signal being carried out to FSK, separate timing, control loop filtering subelement 4322 and digital oscillation control unit 421 disconnect; When the selection signal that mask register provides to processing module 42, for carrier signal being carried out to PSK, separate timing, control loop filtering subelement 4322 is connected with digital oscillation control unit 421.
It is worth mentioning that, this mask register can also be arranged in CPU 41.In the present embodiment, so that the carrier signal of input is carried out to PSK, be demodulated into example, introduce in detail technical scheme of the present invention.CPU41, by the enable register of CPU 41 interior settings, controls the unlatching of demodulator circuit or closes.When CPU 42 opens demodulator circuit by enable register, CPU 41, by access mask register, revises the selection information in mask register, makes mask register setting in " 1 ".Thereby provide selection signal to processing module 42, like this, CPU 41, according to calling the PSK algorithm of storing in mask register, controls processing module 42 and the second demodulating unit 432 carrier signal of input is carried out to PSK demodulation, and by the second restituted signal output obtaining.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can complete by the relevant hardware of program command, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (7)
1. a power line carrier signal demodulating circuit, comprising: processing module and the demodulator circuit being connected with described processing module; It is characterized in that, also comprise: mask register, described mask register is connected with described processing module, to described processing module, provides selection signal; Described demodulator circuit at least consists of the first demodulating unit and the second demodulating unit;
Wherein, described mask register store electricity line of force carrier wave demodulation mode algorithm and selection signal corresponding to described algorithm;
Described processing module comprises:
Numeral oscillation control unit, is connected with described mask register, for generation of and export the first local orthogonal signalling and the second local orthogonal signalling;
The first mixing and filtering unit, be connected with described digital oscillation control unit, be used for utilizing described the first local orthogonal signalling to carry out orthogonal processing and filtering processing to carrier signal, and export the first orthogonal signalling to described the first demodulating unit and described the second demodulating unit;
The second mixing and filtering unit, be connected with described digital oscillation control unit, be used for utilizing described the second local orthogonal signalling to carry out orthogonal processing and filtering processing to described carrier signal, and export the second orthogonal signalling to described the first demodulating unit and described the second demodulating unit;
Described the first demodulating unit comprises:
First postpones subelement, is connected, for described the first orthogonal signalling that receive are carried out to delay disposal, to obtain the first delay orthogonal signalling with described the first mixing and filtering unit;
Second postpones subelement, is connected, for described the second orthogonal signalling that receive are carried out to delay disposal, to obtain the second delay orthogonal signalling with described the second mixing and filtering unit;
The first mixing subelement, is connected with the first delay subelement of living in, for described the first delay orthogonal signalling and described the second orthogonal signalling are multiplied each other, to obtain the first crossbar signal;
The second mixing subelement, is connected with the second delay subelement of living in, for described the second delay orthogonal signalling and described the first orthogonal signalling are multiplied each other, to obtain the second crossbar signal;
Subtraction subelement, is connected with the second mixing subelement with described the first mixing subelement, for described the first crossbar signal and described the second crossbar signal are subtracted each other, and to obtain the first restituted signal, and by described the first restituted signal output;
Described the second demodulating unit comprises:
The 3rd mixing subelement, is connected with the second mixing and filtering unit with described the first mixing and filtering unit, for described the first orthogonal signalling and described the second orthogonal signalling are multiplied each other, to obtain the 3rd orthogonal signalling;
Loop filtering subelement, be connected with mask register with described the 3rd mixing subelement, digital oscillation control unit, for described the 3rd orthogonal signalling are carried out to filtering processing, and the 3rd orthogonal signalling after treatment filtering are exported to described digital oscillation control unit, to obtain the second restituted signal;
Described mask register, is connected with digital oscillation control unit with described loop filtering subelement, for controlling described loop filtering subelement, is connected or disconnects with digital oscillation control unit;
Described digital oscillation control unit comprises adder, K register and digital oscillation control unit control subelement, the settings of the numerical frequency that the numerical value of storing in described K register is described digital oscillation control unit, described the 3rd orthogonal signalling after treatment filtering are exported to described digital oscillation control unit, to obtain the second restituted signal, be specially: the numerical value of storing in described the 3rd orthogonal signalling and described K register is input in described adder, described adder is carried out phase-accumulated according to the numerical value of storing in described K register to the phase information of described the 3rd orthogonal signalling, and the phase information after cumulative is sent to described digital oscillation control unit control subelement, phase information after cumulative for described digital oscillation control unit control subelement basis, adjust sinusoidal signal that digital oscillation control unit produces and the frequency of cosine signal, to reach sinusoidal signal and cosine signal, follow the tracks of the phase information after upper adding up, and the sinusoidal signal after adjusting frequency is multiplied each other by the multiplier of described the first mixing and filtering unit and the homophase carrier signal of input, obtain described the second restituted signal.
2. power line carrier signal demodulating circuit according to claim 1, is characterized in that, described digital oscillation control unit is specially digital oscillating controller.
3. power line carrier signal demodulating circuit according to claim 1, it is characterized in that, also comprise: the first demodulation switch module, be connected with processing module with described the first demodulating unit, for controlling described the first demodulating unit, be connected with processing module or disconnect.
4. a microcontroller, comprises central processing module, processing module and the demodulator circuit being connected with described processing module; It is characterized in that, also comprise: mask register, described mask register is connected with described processing module, to described processing module, provides selection signal; Described demodulator circuit at least consists of the first demodulating unit and the second demodulating unit;
Wherein, described mask register store electricity line of force carrier wave demodulation mode algorithm and selection signal corresponding to described algorithm;
Described processing module comprises: digital oscillation control unit, be connected with described mask register, for generation of and export the first local orthogonal signalling and the second local orthogonal signalling;
The first mixing and filtering unit, for utilizing described the first local orthogonal signalling to carry out orthogonal processing and filtering processing to carrier signal, and exports the first orthogonal signalling to described the first demodulating unit and described the second demodulating unit;
The second mixing and filtering unit, for utilizing described the second local orthogonal signalling to carry out orthogonal processing and filtering processing to described carrier signal, and exports the second orthogonal signalling to described the first demodulating unit and described the second demodulating unit;
Described the first demodulating unit comprises:
First postpones subelement, is connected, for described the first orthogonal signalling that receive are carried out to delay disposal, to obtain the first delay orthogonal signalling with described the first mixing and filtering unit;
Second postpones subelement, is connected, for described the second orthogonal signalling that receive are carried out to delay disposal, to obtain the second delay orthogonal signalling with described the second mixing and filtering unit;
The first mixing subelement, is connected with the first delay subelement of living in, for described the first delay orthogonal signalling and described the second orthogonal signalling are multiplied each other, to obtain the first crossbar signal;
The second mixing subelement, is connected with the second delay subelement of living in, for described the second delay orthogonal signalling and described the first orthogonal signalling are multiplied each other, to obtain the second crossbar signal;
Subtraction subelement, is connected with the second mixing subelement with described the first mixing subelement, for described the first crossbar signal and described the second crossbar signal are subtracted each other, and to obtain the first restituted signal, and by described the first restituted signal output;
Described the second demodulating unit comprises:
The 3rd mixing subelement, is connected with the second mixing and filtering unit with described the first mixing and filtering unit, for described the first orthogonal signalling and described the second orthogonal signalling are multiplied each other, to obtain the 3rd orthogonal signalling;
Loop filtering subelement, be connected with mask register with described the 3rd mixing subelement, digital oscillation control unit, for described the 3rd orthogonal signalling are carried out to filtering processing, and the 3rd orthogonal signalling after treatment filtering are exported to described digital oscillation control unit, to obtain the second restituted signal;
Described mask register, is connected with digital oscillation control unit with described loop filtering subelement, for controlling described loop filtering subelement, is connected or disconnects with digital oscillation control unit;
Described digital oscillation control unit comprises adder, K register and digital oscillation control unit control subelement, the settings of the numerical frequency that the numerical value of storing in described K register is described digital oscillation control unit, described the 3rd orthogonal signalling after treatment filtering are exported to described digital oscillation control unit, to obtain the second restituted signal, be specially: the numerical value of storing in described the 3rd orthogonal signalling and described K register is input in described adder, described adder is carried out phase-accumulated according to the numerical value of storing in described K register to the phase information of described the 3rd orthogonal signalling, and the phase information after cumulative is sent to described digital oscillation control unit control subelement, phase information after cumulative for described digital oscillation control unit control subelement basis, adjust sinusoidal signal that digital oscillation control unit produces and the frequency of cosine signal, to reach sinusoidal signal and cosine signal, follow the tracks of the phase information after upper adding up, and the sinusoidal signal after adjusting frequency is multiplied each other by the multiplier of described the first mixing and filtering unit and the homophase carrier signal of input, obtain described the second restituted signal.
5. microcontroller according to claim 4, is characterized in that, described digital oscillation control unit is specially digital oscillating controller.
6. microcontroller according to claim 4, is characterized in that, also comprises: the first demodulation switch module, be connected with processing module with described the first demodulating unit, and for controlling described the first demodulating unit, be connected with processing module or disconnect.
7. microcontroller according to claim 4, is characterized in that, also comprises: input-output unit, for receiving the described carrier signal of ancillary equipment input, and inputs to described processing module by described carrier signal; Or receive described the first restituted signal or second restituted signal of described demodulator circuit output, and described the first restituted signal or the second restituted signal are carried out exporting to described ancillary equipment after software algorithm processing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010123199.9A CN102195678B (en) | 2010-03-10 | 2010-03-10 | Power line carrier signal demodulation circuit and microcontroller |
| PCT/CN2010/073512 WO2011109966A1 (en) | 2010-03-10 | 2010-06-03 | Power line carrier signal demodulation circuit and micro controller |
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| CN201010123199.9A CN102195678B (en) | 2010-03-10 | 2010-03-10 | Power line carrier signal demodulation circuit and microcontroller |
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| CN102195678B true CN102195678B (en) | 2014-04-23 |
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| CN102594404B (en) * | 2011-01-07 | 2015-03-25 | 上海海尔集成电路有限公司 | Demodulator circuit for carrier signal of power line and microcontroller |
| CN103326740B (en) * | 2013-07-16 | 2016-04-06 | 中电华瑞技术有限公司 | A kind of Two-channel power line carrier communication chip |
| JP6929203B2 (en) * | 2017-11-15 | 2021-09-01 | 旭化成エレクトロニクス株式会社 | Direct conversion receiver |
| CN112671682A (en) * | 2020-12-14 | 2021-04-16 | 天津光电通信技术有限公司 | Integrated digital demodulation method and device |
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| EP1484880A2 (en) * | 2003-06-05 | 2004-12-08 | Seiko Epson Corporation | Demodulation device and demodulation method for wireless data communication |
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| JPH1093527A (en) * | 1996-09-12 | 1998-04-10 | Kokusai Electric Co Ltd | Carrier regeneration circuit |
| US6795485B2 (en) * | 2000-12-04 | 2004-09-21 | Share Wave, Inc. | Integrated QPSK/FSK demodulator |
| CN2456377Y (en) * | 2000-12-12 | 2001-10-24 | 四川泰通智能电器有限公司 | Three phase power carrier wave signal transferrer |
| US6847255B2 (en) * | 2001-06-01 | 2005-01-25 | Broadband Innovations, Inc. | Zero IF complex quadrature frequency discriminator and FM demodulator |
| WO2005062915A2 (en) * | 2003-12-23 | 2005-07-14 | Arkados, Inc. | Power line communications device in which physical communications protocol layer operation is dynamically selectable |
| US20050259768A1 (en) * | 2004-05-21 | 2005-11-24 | Oki Techno Centre (Singapore) Pte Ltd | Digital receiver and method for processing received signals |
| CN101765985A (en) * | 2007-07-09 | 2010-06-30 | 赛米泰克创新有限公司 | Communication methods and devices |
| CN201114023Y (en) * | 2007-10-15 | 2008-09-10 | 上海埃德电子股份有限公司 | Modem |
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Address after: 266023, a, Jia Lu, 16, Shandong, Qingdao Patentee after: Qingdao Eastsoft Communication Technology Co., Ltd. Patentee after: SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD. Address before: 266023, a, Jia Lu, 16, Shandong, Qingdao Patentee before: Qingdao Eastsoft Communication Technology Co., Ltd. Patentee before: Shanghai Hair Group Integated Circuit Co., Ltd. |