CN102193850A - Time updating system of multi-mainboard server - Google Patents
Time updating system of multi-mainboard server Download PDFInfo
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- CN102193850A CN102193850A CN2010101385018A CN201010138501A CN102193850A CN 102193850 A CN102193850 A CN 102193850A CN 2010101385018 A CN2010101385018 A CN 2010101385018A CN 201010138501 A CN201010138501 A CN 201010138501A CN 102193850 A CN102193850 A CN 102193850A
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Abstract
The invention provides a time updating system of a multi-mainboard server, which is applied to a server system. By using the time updating system, a basic input/output system with multiple mainboards gives the mainboard time respectively, a base plate management controller acquires the mainboard time through a peripheral equipment interface controller, and the earliest acquired mainboard time is set as the system time of the server system. By using the time updating system, the system time can be accurately set or updated in the multi-mainboard server system in which the base plate management controller is not arranged on each mainboard.
Description
Technical field
The invention relates to a kind of many motherboards server, especially about a kind of baseboard management controller of many motherboards server.
Background technology
In known server system with a plurality of motherboards, all on each motherboard, install a baseboard management controller (Baseboard Management Controller, BMC).The technology of a plurality of motherboards of management control in known server system is to utilize set on each a motherboard baseboard management controller, and its motherboard at place is separately controlled in management.So in known baseboard management controller, system time all is the basic input/output (BIOS) by each motherboard, (Power On Self Test sends to baseboard management controller in POST) and sets at each power-on self-test.
Because a baseboard management controller all is installed on each motherboard, it is cumbersome again each motherboard to be done unified management, can improve the manufacturing cost of many server systems simultaneously.Therefore, need a kind of new server architecture, and can accurately set simultaneously or the update system time.
Summary of the invention
In view of this, the present invention mainly proposes a kind of time update system of many motherboards server, is applied in the server system management board that comprises a plurality of motherboards at least and have a baseboard management controller (BMC).
A plurality of motherboards are respectively coupled to a management board, and in order to carry out the data computing of server system, wherein each motherboard comprises a basic input/output, a peripherals interfacial level controller and a temporary storage location.Wherein, basic input/output can carry out a power-on self-test (POST) to the motherboard at its place, and the one motherboard time of motherboard at given its place.The peripherals interfacial level controller is connected to basic input/output, with obtain and the temporary motherboard time in temporary storage location.Baseboard management controller is located on the management board, and be connected to the peripherals interfacial level controller of each motherboard, to obtain the data that comprises the motherboard time from one of peripherals interfacial level controller of a plurality of motherboards, if the baseboard management controller detecting is less than the data of the system time of this server system, then obtain the data that comprises this motherboard time, and setting is the system time of server system with the motherboard time of obtaining at first from one of those peripherals interfacial level controllers.So, the purpose of upgrading with the system time of reaching many motherboards server.
Owing to need not just can accurately set or time of update service device system by the baseboard management controller of each motherboard, therefore use time update system of the present invention can need not one baseboard management controller to be installed, for the cost that reduces server system brings possibility for each motherboard.
Below will clearly demonstrate spirit of the present invention with graphic and detailed description, any those of ordinary skill in the art is after understanding preferred embodiment of the present invention, when can be by disclosed technology, change and modification, it does not break away from spirit of the present invention and scope.
Description of drawings
Fig. 1 illustrates the calcspar of time update system one embodiment of many motherboards server of the present invention;
Fig. 2 illustrates the time updating steps process flow diagram of many motherboards server of the present invention; And
Fig. 3 illustrates the details process flow diagram of the present invention from the step of the data of one of peripherals interfacial level controller reception motherboard time.
[primary clustering symbol description]
10: server system 200: management board
110-140: motherboard 210: baseboard management controller
111-141: basic input/output 300-360: steps flow chart
112-142: temporary storage location
113-143: peripherals interfacial level controller
Embodiment
Please cooperate with reference to Fig. 1, it is the calcspar of time update system one embodiment of many motherboards server of the present invention.The time update system of many motherboards server of the present invention is to be located in the server system 10, and at least by a plurality of motherboards 110～140, and baseboard management controller 210 is formed.
Motherboard 110～140 is respectively coupled to management board 200, in order to carry out the data computing of server system 10, wherein motherboard 110,120,130 and 140 comprises basic input/output 111～141, temporary storage location 112～142 and peripherals interfacial level controller 113～143 respectively.
Basic input/output 111 is in order to motherboard 110 is carried out a power-on self-test (POST), and in power-on self-test the given 110 1 motherboard times of motherboard.Basic input/output 121 is in order to motherboard 120 is carried out a power-on self-test, and in power-on self-test the given 120 1 motherboard times of motherboard.Basic input/output 131 is in order to motherboard 130 is carried out a power-on self-test, and in power-on self-test the given 130 1 motherboard times of motherboard.Basic input/output 141 is in order to motherboard 140 is carried out a power-on self-test, and in power-on self-test the given 140 1 motherboard times of motherboard.
Peripherals interfacial level controller 113 is connected to basic input/output 111, obtaining the motherboard time of 111 given motherboards 110 of basic input/output, and this motherboard time is temporary in the temporary storage location 112.Peripherals interfacial level controller 123 is connected to basic input/output 121, obtaining the motherboard time of 121 given motherboards 120 of basic input/output, and this motherboard time is temporary in the temporary storage location 122.Peripherals interfacial level controller 133 is connected to basic input/output 131, obtaining the motherboard time of 131 given motherboards 130 of basic input/output, and this motherboard time is temporary in the temporary storage location 132.Peripherals interfacial level controller 143 is connected to basic input/output 141, obtaining the motherboard time of 141 given motherboards 140 of basic input/output, and this motherboard time is temporary in the temporary storage location 142.
Baseboard management controller 210 is located on the management board 200, and is connected to the peripherals interfacial level controller 113～143 of motherboard 110～140.Therefore, baseboard management controller 210 can receive the data of the motherboard time that comprises motherboard 110 from peripherals interfacial level controller 113.Perhaps, baseboard management controller 210 can receive the data of the motherboard time that comprises motherboard 120 from peripherals interfacial level controller 123.Perhaps, baseboard management controller 210 can receive the data of the motherboard time that comprises motherboard 130 from peripherals interfacial level controller 133.Perhaps, baseboard management controller 210 can receive the data of the motherboard time that comprises motherboard 140 from peripherals interfacial level controller 143.
Yet baseboard management controller 210 is the data of the system time of detecting server system 10 earlier.If server system 10 is through outage, again after switching on again, baseboard management controller 210 is just detected the data less than the system time of server system 10, and then baseboard management controller 210 can be obtained the data of the motherboard time that comprises motherboard 110～140 from one of peripherals interfacial level controller 113～143.Before time, baseboard management controller 210 can send inquiry command to peripherals interfacial level controller 113～143 to baseboard management controller 210 repeatedly, is used for obtaining the motherboard time at the motherboard of not receiving one of peripherals interfacial level controller 113～143.Therefore, when peripherals interfacial level controller 113 has been received inquiry command from baseboard management controller 210, peripherals interfacial level controller 113 can be read motherboard 110 from temporary storage location 112 the motherboard time, and respond the data of the motherboard time of motherboard 110 and give baseboard management controller 210.When peripherals interfacial level controller 123 has been received inquiry command from baseboard management controller 210, peripherals interfacial level controller 123 can be read motherboard 120 from temporary storage location 122 the motherboard time, and respond the data of the motherboard time of motherboard 120 and give baseboard management controller 210.When peripherals interfacial level controller 133 has been received inquiry command from baseboard management controller 210, peripherals interfacial level controller 133 can be read motherboard 130 from temporary storage location 132 the motherboard time, and respond the data of the motherboard time of motherboard 130 and give baseboard management controller 210.When peripherals interfacial level controller 143 has been received inquiry command from baseboard management controller 210, peripherals interfacial level controller 143 can be read motherboard 140 from temporary storage location 142 the motherboard time, and respond the data of the motherboard time of motherboard 140 and give baseboard management controller 210.
Then, baseboard management controller 210 is again according to motherboard time of one of motherboard 110～140 of receiving at first, and is set at the system time of server system 10 with the motherboard time that this receives at first.So, the purpose of upgrading with the system time of reaching many motherboards server.
In addition, above-mentioned peripherals interfacial level controller 113～143rd, by a universal serial bus interface, for example: the I2C interface, join with this baseboard management controller 210.And baseboard management controller 210 is by this serial bus interface, for example: the I2C interface, carry out communication with peripherals interfacial level controller 113～143.Above-mentioned peripherals interfacial level controller 113～143 be a complex programmable logic device (ComplexProgrammable Logic Device, CPLD) or a programmable logic device (ProgrammableIntegrated Circuit, PIC).And be that (Intelligent PlatformManagement Bus, IPMB) transfer protocol carries out the data transmission by an Intelligent Platform Management Bus between aforesaid substrate Management Controller 210 and each the peripherals interfacial level controller 113～143.
Please cooperate with reference to Fig. 2, it is the time updating steps process flow diagram of many motherboards server of the present invention.About time of many motherboards server of the present invention new technological process 300 more, be to be applied to have in the server system 10 of a plurality of motherboards, because all identical,, below be example with motherboard 110 so be simplified illustration to the operation procedure of each motherboard.
At first, in server system 10, open a power-on self-test (POST) (step 310) of the motherboard 110 of one of a plurality of motherboards 110～140.Then, in the power-on self-test of motherboard 110, the basic input/output of motherboard 110 113 can the given 110 motherboard times (step 320) of motherboard, and this be the running time of motherboard 110 own.Then, by the peripherals interfacial level controller 111 of motherboard 110, obtain the motherboard time (step 330) that motherboard 110 operates itself.Treat in the step 330 that peripherals interfacial level controller 111 is obtained the motherboard of motherboard 110 after the time, the temporary transient peripherals interfacial level controller 111 that passes through is earlier kept in the motherboard time of these motherboards 110 in temporary storage location 112 (step 340).Then, provide baseboard management controller 210, receive the data (step 350) of the motherboard time of one of peripherals interfacial level controller 111～141.At last, setting the received motherboard time by baseboard management controller 210 again is the system time (step 360) of server system 10.Process ends then.
Yet, more comprise a details flow process about above-mentioned steps 350, below cooperate Fig. 3, the present invention describes the details flow process of step 350 in detail from the details process flow diagram of the step of the data of one of peripherals interfacial level controller reception motherboard time.As shown in Figure 3, repeatedly one of peripherals interfacial level controller 113～143 is sent in order to obtain respectively the inquiry command (step 351) about the motherboard time of motherboard 110～140 earlier by baseboard management controller 210.Then, respond respectively about the data of motherboard time of motherboard 110～140 by peripherals interfacial level controller 113～143 and give baseboard management controller 210 (step 352).Then, judge whether baseboard management controller 210 receives the data (step 353) of the motherboard time of one of motherboard 110～140.If in the step 353, baseboard management controller 210 is not received the data of the motherboard time of one of motherboard 110～140, then returns step 351, continue repeatedly one of peripherals interfacial level controller 113～143 to be sent an inquiry command; But in the step 352, if baseboard management controller 210 has been received the data of the motherboard time of one of motherboard 110～140, then being routed to the step 360 of Fig. 2, is the system time of server system 10 by baseboard management controller 210 settings with the motherboard time of receiving at first.So, the purpose of upgrading with the system time of reaching many motherboards server.
By the foregoing description as can be known, the baseboard management controller that uses the present invention can skip each motherboard just can accurately be set or time of update service device system, therefore use time update system of the present invention can need not one baseboard management controller to be installed, for the cost that reduces server system brings possibility for each motherboard.
Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also do various changes and replacement to the specific embodiment of the present invention.These changes and replace all drop in claims of the present invention institute restricted portion.
Claims (5)
1. the time update system of motherboard server more than a kind is located in the server system, it is characterized in that, the time update system of described many motherboards server comprises at least:
A plurality of motherboards are respectively coupled to a management board, and in order to carry out the data computing of described server system, wherein each described motherboard comprises:
One basic input/output can carry out a power-on self-test to described motherboard, and the one motherboard time of given described motherboard; And
One peripherals interfacial level controller is connected to described basic input/output, to obtain and to keep in the described motherboard time in a temporary storage location; And
One baseboard management controller, be located on the described management board, and be connected to the described peripherals interfacial level controller of each described motherboard, when described baseboard management controller does not detect the data of a system time of described server system, then obtain the data that comprises the described motherboard time, and set the described system time that the described motherboard time is described server system from one of described peripherals interfacial level controller.
2. the time update system of many motherboards server according to claim 1, it is characterized in that, before time, described baseboard management controller sends in order to obtain the inquiry command of described motherboard time described peripherals interfacial level controller described baseboard management controller repeatedly at the described motherboard of not receiving one of described peripherals interfacial level controller.
3. the time update system of many motherboards server according to claim 2 is characterized in that, described peripherals interfacial level controller can be responded the data of described motherboard time and give described baseboard management controller when receiving described inquiry command.
4. the time update system of many motherboards server according to claim 1, it is characterized in that, described peripherals interfacial level controller is to join by a universal serial bus interface and described baseboard management controller, and described baseboard management controller is to carry out communication by described serial bus interface and described peripherals interfacial level controller.
5. the time update system of many motherboards server according to claim 1 is characterized in that, described peripherals interfacial level controller is a complex programmable logic device or a programmable logic device.
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| CN2010101385018A CN102193850A (en) | 2010-03-19 | 2010-03-19 | Time updating system of multi-mainboard server |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101385018A CN102193850A (en) | 2010-03-19 | 2010-03-19 | Time updating system of multi-mainboard server |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106484031A (en) * | 2015-08-26 | 2017-03-08 | 鸿富锦精密工业（深圳）有限公司 | Server management system and method |
| CN109165047A (en) * | 2018-09-03 | 2019-01-08 | 英业达科技有限公司 | The method for maintaining the orthochronous of graphics processor mainboard |
| TWI702486B (en) * | 2018-09-07 | 2020-08-21 | 英業達股份有限公司 | Remote login method for server subsystem and remote login system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101192073A (en) * | 2006-11-22 | 2008-06-04 | 英业达股份有限公司 | Method for updating substrate management controller timing time |
| CN101251818A (en) * | 2008-04-14 | 2008-08-27 | 华硕电脑股份有限公司 | Mainboard of use time statistical apparatus and statistical method |
-
2010
- 2010-03-19 CN CN2010101385018A patent/CN102193850A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192073A (en) * | 2006-11-22 | 2008-06-04 | 英业达股份有限公司 | Method for updating substrate management controller timing time |
| CN101251818A (en) * | 2008-04-14 | 2008-08-27 | 华硕电脑股份有限公司 | Mainboard of use time statistical apparatus and statistical method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106484031A (en) * | 2015-08-26 | 2017-03-08 | 鸿富锦精密工业（深圳）有限公司 | Server management system and method |
| CN109165047A (en) * | 2018-09-03 | 2019-01-08 | 英业达科技有限公司 | The method for maintaining the orthochronous of graphics processor mainboard |
| CN109165047B (en) * | 2018-09-03 | 2021-10-12 | 英业达科技有限公司 | Method for maintaining correct time of graphics processor mainboard |
| TWI702486B (en) * | 2018-09-07 | 2020-08-21 | 英業達股份有限公司 | Remote login method for server subsystem and remote login system |
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Application publication date: 20110921 |