CN102193745A - Flash memory storage device, controller thereof and read-in management method - Google Patents
Flash memory storage device, controller thereof and read-in management method Download PDFInfo
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- CN102193745A CN102193745A CN2010101300378A CN201010130037A CN102193745A CN 102193745 A CN102193745 A CN 102193745A CN 2010101300378 A CN2010101300378 A CN 2010101300378A CN 201010130037 A CN201010130037 A CN 201010130037A CN 102193745 A CN102193745 A CN 102193745A
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Abstract
The invention discloses a flash memory storage device, a controller thereof and a read-in management method, wherein the controller and the read-in management method are used for the flash memory storage device which at least has a first execution thread and a second execution thread, and the flash memory storage device comprises a flash memory chip. The read-in management method comprises the following steps of: presetting a read-in unit; and receiving a first read-in instruction sent by a host computer. The read-in management method also comprises the following steps of: when the first execution thread is judged to be in charge of the execution of the first read-in instruction, allocating the control power of the flash memory chip to the first execution thread; and when the first execution thread finishes data read-in actions of a preset read-in unit, commanding the first execution thread to release the control power of the flash memory chip.
Description
Technical field
The present invention relates to a kind of application of flash memory, particularly relate to a kind of method of the write operation of managing flash memory and flash memory control and the flash memory device that uses the method.
Background technology
In general, the flash memory chip in the flash memory device (chip) can be divided into a plurality of physical blocks (block), and each physical blocks also is divided into a plurality of physical page (page).Wherein, physical blocks is that the minimum of flash memory is wiped (erase) unit, and physical page then is that the minimum of flash memory writes (program) unit.
Owing to when the storage unit of flash memory is programmed, only the value of storage unit can be programmed for 0 by 1, therefore the physical page that data can't be write direct and had been programmed.In other words, must be earlier just this page of Reprogrammable will be stored after the page erase of data.Yet, just because of wiping of flash memory is to be unit with the physical blocks, so in the time need wiping running, the whole physical blocks under this physical page must be wiped to the physical page execution that has legacy data.
Based on flash memory be with physical page as writing unit, and with physical blocks this characteristic as erase unit, the physical blocks in the flash memory chip can be divided into data field (data area) and spare area (spare area) haply.Wherein, the physical blocks that belongs to the data field is the physical blocks that has been used to storage data, and the physical blocks that belongs to the spare area then is the physical blocks that is not used.When the main frame desire write to flash memory device with data, the control circuit of flash memory device can extract physical blocks and write data from the spare area, and the physical blocks of being extracted is associated to the data field.And, after will wiping running, the physical blocks of having wiped is associated to the spare area to the physical blocks execution of data field.
Summary of the invention
The invention provides a kind of management method that writes of flash memory, in order to guarantee that writing instruction can finish in the time limit of regulation.
The invention provides a kind of flash memory device, the writing management method and can guarantee to write instruction and can in the time limit of regulation, finish of the flash memory that it is performed.
The invention provides a kind of flash memory control, the writing management method and can guarantee to write instruction and can in the time limit of regulation, finish of the flash memory that it is performed.
The present invention proposes a kind of management method that writes of flash memory, is used for existing at least the flash memory device of first execution thread and second execution thread, and this flash memory device comprises flash memory chip.The method comprises the default unit of writing of definition, receives first and writes instruction.The method also comprise when judge to be responsible for carry out first write instruction be first execution thread time, the control of flash memory chip is dispensed to first execution thread.Finish the data write activity of the default unit of writing at first execution thread after, make first execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein after the step of control to the first execution thread that distributes flash memory chip, the method also comprises as if during the data write activity of presetting the unit of writing at first execution thread, receiving needs second to write instruction by what second execution thread was responsible for carrying out, then after first execution thread discharges the control of flash memory chip, the control of flash memory chip is dispensed to second execution thread.After second execution thread writes instruction pairing second and writes data and write to flash memory chip second, make second execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein after the step of the control that makes second execution thread release flash memory chip, the method also comprises judges whether first execution thread has been finished first and write the write activity that instruction pairing first writes data.If not, then the control with flash memory chip is dispensed to first execution thread, finish the data write activity of the default unit of writing at first execution thread after, make first execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein after the step of control to the first execution thread that distributes flash memory chip, the method also comprises as if during the data write activity of presetting the unit of writing at first execution thread, do not receive other and write instruction, then after first execution thread discharges the control of flash memory chip, judge whether first execution thread has been finished first and write the write activity that instruction pairing first writes data.If not, then the control with flash memory chip is dispensed to first execution thread, and finish the data write activity of the default unit of writing at first execution thread after, makes first execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein first execution thread is in order to carry out smart card (smartcard) application program.The method also is included in first and writes instruction (Application Protocol Data Unit, APUD) when instruction judge and be responsible for carrying out first what write instruction is first execution thread for Application Protocol Data Unit.
In one example of the present invention embodiment, wherein second execution thread is in order to carry out secure digital (Secure Digital, SD) card read-write application program.
In one example of the present invention embodiment, wherein preset the included physical page quantity of the unit of writing less than the included physical page quantity of physical blocks in the flash memory chip.
From another viewpoint, the present invention proposes a kind of flash memory device.Wherein, have at least first execution thread and second execution thread to be present in this flash memory device.This flash memory device comprises flash memory chip, connector, and flash memory control.Connector is in order to coupling main frame, and receives the instruction that writes that main frame assigns.Flash memory control is coupled to flash memory chip and connector, in order to define the default unit of writing.Wherein, connector receive that main frame assigns first write instruction after, flash memory control judge to be responsible for carry out first write instruction be first execution thread time, the control of flash memory chip is dispensed to first execution thread, and finish the data write activity of the default unit of writing at first execution thread after, make first execution thread discharge the control of this flash memory chip.
In one example of the present invention embodiment, wherein as if during the data write activity of presetting the unit of writing at first execution thread, connector receives that main frame is assigned and needs and second writes instruction by what second execution thread was responsible for carrying out, after flash memory control discharges the control of flash memory chip at first execution thread, the control of flash memory chip is dispensed to second execution thread, and after second execution thread writes instruction pairing second and writes data and write to flash memory chip second, make second execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein after making second execution thread discharge the control of flash memory chip, flash memory control is judging that first execution thread do not finish first when writing instruction pairing first and writing the write activity of data as yet, the control of flash memory chip is dispensed to first execution thread, and finish the data write activity of the default unit of writing at first execution thread after, make first execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein behind control to the first execution thread that distributes flash memory chip, during the data write activity of presetting the unit of writing at first execution thread, connector do not receive that main frame assigns other write instruction, after flash memory control discharges the control of flash memory chip at first execution thread, judge whether first execution thread has been finished first and write the write activity that instruction pairing first writes data.If first execution thread is not finished first write activity that writes data as yet, flash memory control is dispensed to first execution thread with the control of flash memory chip, and finish the data write activity of the default unit of writing at first execution thread after, make first execution thread discharge the control of flash memory chip.
In one example of the present invention embodiment, wherein first execution thread is in order to carry out application program of intelligent card, flash memory control is when first writes instruction and instruct for Application Protocol Data Unit, and what judge that responsible execution first writes instruction is first execution thread.
In one example of the present invention embodiment, wherein second execution thread is in order to carry out safe digital card read-write application program.
In one example of the present invention embodiment, wherein preset the included physical page quantity of the unit of writing less than the included physical page quantity of physical blocks in the flash memory chip.
From another viewpoint, the present invention proposes a kind of flash memory control, is disposed in the flash memory device that is coupled to main frame.This flash memory device exists first execution thread and second execution thread at least, and comprises flash memory chip.Flash memory control comprises microprocessor unit, flash memory chip interface unit, host interface unit and resource allocation unit.The flash memory chip interface unit is coupled to microprocessor unit, in order to be coupled to flash memory chip.Host interface unit is coupled to microprocessor unit, in order to be coupled to main frame.Resource allocation unit is coupled to microprocessor unit, in order to define the default unit of writing.Wherein, what host interface unit received that main frame assigns first writes instruction, resource allocation unit judge to be responsible for carry out first write instruction be first execution thread time, the control of flash memory chip is dispensed to first execution thread, and finish the data write activity of the default unit of writing at first execution thread after, make first execution thread discharge the control of flash memory chip.
Based on above-mentioned, for the flash memory device that has these two kinds of execution threads of application program of intelligent card and safe digital card read-write application program simultaneously, the data write activity that the invention enables application program of intelligent card that flash memory chip is carried out can be read and write application program by safe digital card and interrupt.In view of the above, guarantee safe digital card read-write application program carry out from main frame write instruction the time, can not surpass that the safe digital card standard is defined to be write instruction and finish the time limit.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Figure 1A is the host computer system of the use flash memory device that illustrated according to one example of the present invention embodiment.
Figure 1B is the synoptic diagram of exemplary embodiment illustrated according to the present invention computing machine, input/output device and flash memory device.
Fig. 1 C is another exemplary embodiment illustrated according to the present invention the host computer system and the synoptic diagram of flash memory device.
Fig. 1 D is the summary calcspar of the flash memory device shown in the Figure 1A that illustrates.
Fig. 2 is the calcspar of the flash memory control that another exemplary embodiment illustrated according to the present invention.
Fig. 3 is the running synoptic diagram of the flash memory device shown in the Figure 1A that illustrates.
Fig. 4 A, 4B, 4C are the synoptic diagram of the operation of the merged entity block that one exemplary embodiment is illustrated according to the present invention.
Fig. 5 is the process flow diagram that writes management method of the flash memory that illustrated according to one example of the present invention embodiment.
Fig. 6 is the summary calcspar of the flash memory device that another exemplary embodiment illustrated according to the present invention.
The reference numeral explanation
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: coil with oneself
1214: storage card
1216: solid state hard disc
1310: digital still camera
The 1312:SD card
The 1314:MMC card
1316: memory stick
The 1318:CF card
1320: embedded storage device
100,600: flash memory device
102: connector
104,104 ', 604: flash memory control
1042: host interface unit
1044: microprocessor unit
1046: resource allocation unit
1048: the flash memory chip interface unit
106: flash memory chip
2002: memory buffer
2004: error correction unit
2006: Power Management Unit
310: the first execution threads
320: the second execution threads
A (0), A (1), A (2), B (0), B (1), B (2): the page
510～590: each step that writes management method of the described flash memory of one example of the present invention embodiment
6041: the intelligent card interface unit
607: intelligent card chip
Embodiment
Figure 1A is the synoptic diagram of the host computer system of the use flash memory device that illustrates according to exemplary embodiment of the present invention.
In exemplary embodiment of the present invention, flash memory device 100 is to couple by data transmission interface 1110 other assembly with host computer system 1000.Processing host system 1000 by microprocessor 1102, random access memory 1104 and input/output device 1106 can write to data flash memory device 100, or from flash memory device 100 reading of data.For example, flash memory device 100 can be shown in Figure 1B storage card 1214, coil 1212 or solid state hard disc (Solid State Drive, SSD) 1216 with oneself.
Generally speaking, but host computer system 1000 is any system of storage data.Though in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet in another exemplary embodiment of the present invention, host computer system 1000 can also be systems such as digital camera, video camera, communication device, message player or video signal player.For example, when host computer system is digital camera 1310, flash memory device then is its employed secure digital (Secure Digital, SD) card 1312, multimedia storage (Multimedia Card, MMC) card 1314, memory stick (Memory Stick) 1316, CF card 1318 or embedded storage device 1320 (shown in Fig. 1 C).Embedded storage device 1320 comprise the built-in multimedia card (Embedded MMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be coupled on the substrate of host computer system.
Fig. 1 D is the calcspar of the flash memory device 100 shown in the Figure 1A that illustrates.Please refer to Fig. 1 D, flash memory device 100 comprises connector 102, flash memory control 104 and flash memory chip 106.
Flash memory chip interface unit 1048 usefulness are so that flash memory control 104 is coupled to flash memory chip 106.Make the running of being correlated with of 104 pairs of flash memory chips 106 of flash memory control according to this.
Shown in Fig. 1 D, host interface unit 1042, resource allocation unit 1046 and flash memory chip interface unit 1048 all are coupled to microprocessor unit 1044, and microprocessor unit 1044 is main control units of flash memory control 104, in order to assembly synergistic cooperations such as host interface unit 1042, flash memory chip interface unit 1048 and resource allocation unit 1046, to carry out the various runnings of flash memory chip 106.
In this exemplary embodiment, resource allocation unit 1046 for example be real time operating system (Real TimeOperation System, RTOS).In another exemplary embodiment, resource allocation unit 1046 also can be implemented into flash memory control 104 with form of firmware.For example, the resource allocation unit 1046 that will comprise a plurality of steering orders is burned onto a program storage (ROM (read-only memory) (Read OnlyMemory, ROM)) for example, and this program storage is embedded in flash memory control 104.When flash memory device 100 runnings, microprocessor unit 1044 will be carried out a plurality of steering orders of resource allocation unit 1046, finish the read-write control distribution mechanism of flash memory chip 106 according to this.
In another example of the present invention embodiment, the flash memory control in the flash memory device 100 also comprises other functional module.Fig. 2 is the calcspar of the flash memory control that illustrated according to another example of the present invention embodiment, please refer to Fig. 2.In flash memory control 104 ', except comprising host interface unit 1042, microprocessor unit 1044, resource allocation unit 1046 and flash memory chip interface unit 1048, also comprise memory buffer 2002, error correction unit 2004 in addition, and Power Management Unit 2006.
In detail, memory buffer 2002 is coupled to microprocessor unit 1044, in order to the temporary data that come from host computer system 1000, or the temporary data that come from flash memory chip 106.
In this exemplary embodiment, have at least first execution thread and second execution thread to be present in flash memory device 100 (first execution thread 310 as shown in Figure 3 and second execution thread 320) simultaneously.That is memorizer memory devices 100 is to adopt many execution threads framework.First execution thread 310 and second execution thread 320 all can be read and write flash memory chip 106 by flash memory chip interface unit 1048.For example, the flash memory chip 106 of this exemplary embodiment is divided into the first cut section 106A and the second cut section 106B at least, wherein first execution thread 310 is in charge of the first cut section 106A, 320 of second execution threads are in charge of the second cut section 106B, and the execution thread that has only in order to manage this cut section could carry out the data write action to this cut section.What deserves to be mentioned is, first execution thread 310 does not have different flash memory management rules with 320 of second execution threads, therefore receive from host computer system 1000 write instruction after, logical blocks and the transformation rule between physical blocks that first execution thread 310 and second execution thread 320 are taked also can be different.
Because first execution thread 310 and second execution thread 320 all must be read and write flash memory chip 106 by flash memory chip interface unit 1048, therefore need the control of 1046 pairs of flash memory chips 106 of resource allocation unit to manage and distribute, to guarantee first execution thread 310 and the second execution thread 320 access flash memory chip 106 of all having an opportunity.
In this exemplary embodiment, resource allocation unit 1046 definition have a default unit of writing, and this presets the included physical page quantity of the unit of writing less than the included physical page quantity of physical blocks in the flash memory chip 106.For example, the default unit of writing can be a physical page.Obtained at first execution thread 310 under the situation of control of flash memory chip 106, resource allocation unit 1046 can be after first execution thread 310 be finished the data write activity of the default unit of writing at every turn, and which execution thread what the decision next one can be obtained flash memory chip 106 controls is.
Specifically, host interface unit 1042 receive that host computer systems 1000 assign first write instruction after, microprocessor unit 1044 can be judged according to first kind that writes instruction, the interior logical address of perhaps desiring to write data and is responsible for carrying out first which execution thread what write instruction be.When judge to be responsible for carry out first write instruction be first execution thread 310 time, microprocessor unit 1044 writes instruction with first and is sent to first execution thread 310, and resource allocation unit 1046 is dispensed to first execution thread 310 with the control of flash memory chip 106 simultaneously.At this moment, first execution thread 310 can write data the first cut section 106A of flash memory chip 106 by flash memory chip interface unit 1048.Yet no matter first write instruction pairing first and write data and whether intactly write to flash memory chip 106, in case first execution thread 310 is finished the data write activity of the default unit of writing, resource allocation unit 1046 just can make first execution thread 310 discharge the control of flash memory chip 106.
Then, whether resource allocation unit 1046 decisions will be delivered the power of energy access flash memory chip 106 to second execution thread 320, or the control of flash memory chip 106 is distributed to first execution thread 310 once more.
If preset at first execution thread 310 unit of writing the data write activity during, host interface unit 1042 receives that host computer system 1000 is assigned and needs and second write instruction by what second execution thread 320 was responsible for carrying out, resource allocation unit 1046 can be after first execution thread 310 discharges the control of flash memory chips 106, and the control of flash memory chip 106 is dispensed to second execution thread 320.This moment, second execution thread 320 can write data the second cut section 106B of flash memory chip 106 by flash memory chip interface unit 1048.After treating that second execution thread 320 writes instruction pairing second and writes data and write to flash memory chip 106 second, resource allocation unit 1046 just makes the control of second execution thread, 320 release flash memory chips 106.Thereafter, do not finish first as yet and write the write activity that instruction pairing first writes data if judge first execution thread 310, resource allocation unit 1046 is distributed to first execution thread 310 once more with the control of flash memory chip 106.Similarly, in case first execution thread 310 is finished the data write activity of the default unit of writing, resource allocation unit 1046 just makes first execution thread 310 discharge the control of flash memory chip 106.
If preset at first execution thread 310 unit of writing the data write activity during, host interface unit 1042 do not receive that host computer system 1000 assigns other write instruction, 1046 of resource allocation units can judge whether first execution thread 310 has been finished first and write the write activity that instruction pairing first writes data after first execution thread 310 discharges the control of flash memory chip 106.If not, resource allocation unit 1046 redistributes the control of flash memory chip 106 to first execution thread 310.And finish the data write activity of the default unit of writing at first execution thread 310 after, resource allocation unit 1046 makes first execution thread 310 discharge the control of flash memory chip 106.
As mentioned above, first execution thread 310 once only can write and meet the default data that write unit-sized, just discharge the control of flash memory chip 106 subsequently, and by resource allocation unit 1046 judge then can access flash memory chip 106 be which execution thread.During the data write activity of presetting the unit of writing at first execution thread 310, flash memory device 100 obtain that host computer system 1000 assigns another write instruction, and this writes instruction and needs to be responsible for execution by second execution thread 320, because having higher flash memory chip 106, second execution thread 320 uses right of priority, even if therefore first execution thread 310 do not finish as yet the action that writes instruction that it received (that is, this moment, first execution thread 310 and second execution thread 320 all needed data are write flash memory chip 106), resource allocation unit 1046 still can consign to the control of flash memory chip 106 second execution thread 320.
Also because the write activity of first execution thread 310 can be interrupted by second execution thread 320,, need to use at least two physical blocks to come data in the recording processing therefore writing of being responsible for of first execution thread 310 before instruction do not finish as yet.
In detail, suppose that the default unit of writing is a physical page.Obtain need to be responsible for carrying out by first execution thread 310 first write instruction after, if first write that the 0th to 2 physical page stored data among the physical blocks A that instruction desires to write, and first write that to instruct be the content that will upgrade the 2nd page.After first execution thread 310 is obtained the control of flash memory chip 106, shown in Fig. 4 A, need to extract a new physical blocks B from the spare area of flash memory chip 106, and the data that will be arranged in the page A (0) of physical blocks A write the page B (0) of physical blocks B, discharge the control of flash memory chip 106 subsequently.
If first execution thread 310 writes the process of the page B (0) of physical blocks B in the data of the page A (0) that will be arranged in physical blocks A, the host computer system 1000 of not obtaining flash memory device 100 transmit other write instruction, because first action that writes instruction is not finished as yet, so resource allocation unit 1046 is distributed to the control of flash memory chip 106 first execution thread 310 once again.Next shown in Fig. 4 B, the data that first execution thread 310 will be arranged in the page A (1) of physical blocks A write the page B (1) of physical blocks B, discharge the control of flash memory chip 106 subsequently.
If the data that will be arranged in the page A (1) of physical blocks A at first execution thread 310 write the process of the page B (1) of physical blocks B, flash memory device 100 is obtained to be needed to write instruction by second of second execution thread, 320 responsible execution, after first execution thread 310 discharged the control of flash memory chip 106, the control of flash memory chip 106 can be transferred to second execution thread 320 so.Treat that second execution thread 320 finishes second and write instruction, resource allocation unit 1046 just makes second execution thread 320 discharge the control of flash memory chips 106.
This moment is owing to first write instruction and do not finish as yet, so resource allocation unit 1046 then consigns to first execution thread 310 with the control of flash memory chip 106.Shown in Fig. 4 C, first execution thread 310 is after the new data that desire is upgraded writes to the page B (2) of physical blocks B, just first write instruction and finish.Because first execution thread 310 is once only done the data write activity of a page, therefore must wait for that finishing first writes after the instruction, just can wipe the legacy data among the physical blocks A, and physical blocks A logically is associated as the spare area.
In addition, in case microprocessor unit 1044 will need to transfer to 310 execution of first execution thread by the work order (as write, read or obliterated data) that first execution thread 310 is responsible in another exemplary embodiment, no matter whether this work order is finished, when host computer system 1000 inquiries, flash memory control 104 all will respond the restore message that host computer system 1000 receives work order, produce other restore message thereafter when first execution thread 310 is finished the work instruction no longer in addition.Yet, be responsible for the work order (as write, read or obliterated data) of execution by second execution thread 320 at need, then must after second execution thread 320 is fully finished this work order, (for example finish the data write activity that writes instruction), treat that host computer system 1000 just responds the restore message that host computer system 1000 has been finished the work when sending inquiry.
In addition, in another exemplary embodiment, first or second execution thread can initiatively be replied host computer system 1000 and receive a work order after receive work order, and first or second execution thread also can initiatively be replied host computer system 1000 these work and finish after the instruction of finishing the work.
Fig. 5 is the process flow diagram that writes management method according to one example of the present invention flash memory that embodiment illustrates.
See also Fig. 5, in step 510, flash memory device 100 receives and writes instruction from first of host computer system 1000.Shown in step 520, when judge to be responsible for carry out first write instruction be first execution thread 310 time, the resource allocation unit 1046 in the flash memory control 104 is distributed to first execution thread 310 with the control of flash memory chip 106.
In step 530, resource allocation unit 1046 judges whether first execution thread 310 has finished the data write activity of the default unit of writing.If then in step 540, resource allocation unit 1046 makes first execution thread 310 discharge the control of flash memory chip 106.
Then in step 550, resource allocation unit 1046 judge first execution thread 310 preset the unit of writing the data write activity during, whether flash memory device 100 receives that host computer system 1000 is assigned and need to be responsible for second of execution by second execution thread 320 write instruction.
During the data write activity of presetting the unit of writing at first execution thread 310, flash memory device 100 does not receive to be needed to write instruction by second of second execution thread, 320 responsible execution, and then the described flow process of this exemplary embodiment will enter step 580.
During the data write activity of presetting the unit of writing at first execution thread 310, flash memory device 100 has to receive to be needed to write instruction by second of second execution thread, 320 responsible execution, then in step 560, resource allocation unit 1046 is distributed to second execution thread 320 with the control of flash memory chip 106, and shown in step 570, after second execution thread 320 writes instruction pairing second and writes data and write to flash memory chip 106 second, resource allocation unit 1046 makes second execution thread 320 discharge the control of flash memory chip 106, then enters step 580.
In step 580, resource allocation unit 1046 judges whether first execution thread 310 has been finished first and write the write activity that instruction pairing first writes data.If then finish the flow process that writes management method of this flash memory.If not, then shown in step 590, resource allocation unit 1046 is distributed to first execution thread 310 with the control of flash memory chip 106.Next the flow process that writes management method of this flash memory will be got back to step 530, and repeatedly execution in step 530 to step 590 up to first execution thread 310 finish first write instruction till.
Fig. 6 is the summary calcspar of the flash memory device that another exemplary embodiment illustrated according to the present invention.See also Fig. 6, flash memory device 600 is similar to the flash memory device 100 shown in Fig. 1 D, difference is in the flash memory control 604 of flash memory device 600, except host interface unit 1042, microprocessor unit 1044, resource allocation unit 1046, and outside the flash memory chip interface unit 1048, also comprise smart card chip interface unit 6041.And flash memory control 604 is coupled to intelligent card chip 607 by smart card chip interface unit 6041 in addition except coupling the flash memory chip 106 by flash memory chip interface unit 1048.
In this exemplary embodiment, smart card chip interface unit 6041 meets ISO 7816 standards.Flash memory device 600 exists first execution thread and second execution thread at least simultaneously.Wherein, first execution thread is in order to carry out the application program of developing at specific purpose, smart card (smartcard) application program for example, and second execution thread is in order to carry out safe digital card (Secure Digital Card) read-write application program.In general, the data access amount of application program of intelligent card can be read and write application program less than safe digital card, and the access speed of application program of intelligent card is also slower.
Application program of intelligent card is in order to link up with intelligent card chip 607, the data in simultaneously also can access flash memory chip 106.Safe digital card read-write application program then is in order to the data in the access flash memory chip 106.Wherein, safe digital card read-write application program has higher flash memory chip 106 use right of priority.
If first data that write in the instruction desire renewal flash memory chip 106 that host interface unit 1042 is received, microprocessor unit 1044 writes instruction first and is Application Protocol Data Unit (Application Protocol Data Unit, when APUD) instructing, judge to be responsible for carrying out first, what write instruction is application program of intelligent card, and writes instruction with first and reach application program of intelligent card.Resource allocation unit 1046 also can be distributed to application program of intelligent card with the control of flash memory chip 106.
Because application program of intelligent card once can only be carried out the data write activity of the default unit of writing (the default unit of writing of this exemplary embodiment hypothesis is a physical page).Behind the data write activity of finishing the default unit of writing, just must discharge the control of flash memory chip 106.If finish at application program of intelligent card the default unit of writing the data write activity during, host computer system 1000 has been assigned to be needed to write instruction by second of safe digital card read-write application program execution, next just can read and write the control that application program obtains flash memory chip 106 by safe digital card.Because the detailed operation mode and the flash memory device 100 of flash memory device 600 are same or similar, so do not repeat them here.
In this exemplary embodiment, suppose that each physical blocks comprises 128 physical page in flash memory chip 106, and each physical page size is 4K byte (byte).Can follow under the situation of merging (merge) physical blocks writing instruction so, finish this and write the needed time of instruction and be approximately 150 milliseconds (ms).Wherein, the average read-write time of a page is about 1.15ms.
At present, in the standard of safe digital card, stipulated that each deadline that writes instruction all must be less than 250ms.In this exemplary embodiment, since application program of intelligent card once can only carry out a physical page the data write activity (that is, the merging action of physical blocks needs gradation to finish), even if at application program of intelligent card during just in write data, flash memory device 600 receives to be needed second to be write instruction and to carry out second and write instruction and need the merged entity block by what safe digital card read-write application program was responsible for, and safe digital card read-write application program second time that writes instruction of finishing can not surpass the defined 250ms of safe digital card standard yet.In detail, the safe digital card read-write is to write second with safe digital card read-write application program time of the application program of intelligent card data that write a physical page to instruct pairing second to write the summation that data write to the time of flash memory chip 106 application program second time that writes instruction of finishing.Wherein, safe digital card read-write application program writes the time that data write to flash memory chip 106 with second and is no more than 150ms at most.
What must specify is, though be to come with the flash memory device that has two execution threads simultaneously that the present invention will be described in above-mentioned exemplary embodiment, yet in other exemplary embodiment of the present invention, also can there be plural execution thread in flash memory device simultaneously, the kind and the quantity of execution thread is not limited at this.
In sum, flash memory device of the present invention, its controller and write management method and be applicable to simultaneously the flash memory device that has at least two execution threads.The present invention's order control that after specific execution thread is whenever finished the data write activity of the default unit of writing, discharges flash memory chip wherein, and then allow other execution thread have an opportunity to obtain the control of flash memory chip, wait for the time that specific execution thread is finished write activity with minimizing.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, so protection scope of the present invention is to be as the criterion with claim of the present invention.
Claims (15)
- A flash memory write management method, be used for existing at least a flash memory device of one first execution thread and one second execution thread, this flash memory device comprises a flash memory chip, this method comprises:The definition one default unit of writing;Receive one first and write instruction;When judge to be responsible for carry out this first write instruction be this first execution thread the time, the control of distributing this flash memory chip is to this first execution thread; AndFinish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
- Flash memory as claimed in claim 1 write management method, wherein in the control of distributing this flash memory chip to the step of this first execution thread, this method also comprises:During the data write activity that carries out this default unit of writing at this first execution thread, receiving one needs one second to write instruction by what this second execution thread was responsible for carrying out, then after this first execution thread discharged the control of this flash memory chip, the control of distributing this flash memory chip was to this second execution thread; AndThis second execution thread with this second write instruction pairing 1 second and write data and write to this flash memory chip after, make this second execution thread discharge the control of this flash memory chip.
- Flash memory as claimed in claim 2 write management method, wherein making after this second execution thread discharges the step of control of this flash memory chip, this method also comprises:Judge whether this first execution thread has been finished this and first write the write activity that instruction pairing 1 first writes data;If not, then distribute the control of this flash memory chip to this first execution thread; AndFinish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
- Flash memory as claimed in claim 1 write management method, wherein in the control of distributing this flash memory chip to the step of this first execution thread, this method also comprises:During the data write activity that carries out this default unit of writing at this first execution thread, do not receive other and write instruction, then after this first execution thread discharges the control of this flash memory chip, judge whether this first execution thread has been finished this and first write the write activity that instruction pairing 1 first writes data;If not, then distribute the control of this flash memory chip to this first execution thread; AndFinish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
- Flash memory as claimed in claim 1 write management method, wherein this first execution thread is in order to carry out an application program of intelligent card, this method also comprises:If first to write instruction be Application Protocol Data Unit instruction for this, then judge and be responsible for carrying out this first what write instruction is this first execution thread.
- Flash memory as claimed in claim 1 write management method, wherein this second execution thread is in order to carry out safe digital card read-write application program.
- Flash memory as claimed in claim 1 write management method, wherein should the default unit of writing included physical page quantity is less than the included physical page quantity of a physical blocks in this flash memory chip.
- 8. a flash memory device has at least one first execution thread and one second execution thread to be present in this flash memory device, and this flash memory device comprises:One flash memory chip;A connector in order to coupling a main frame, and receives the instruction that writes that this main frame assigns; AndOne flash memory control is coupled to this flash memory chip and this connector, presets the unit of writing in order to define one,Wherein this connector receive that this main frame assigns one first write instruction after, this flash memory control judge to be responsible for carry out this first write instruction be this first execution thread the time, the control of distributing this flash memory chip is to this first execution thread, and finish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
- 9. flash memory device as claimed in claim 8, wherein as if during the data write activity that carries out this default unit of writing at this first execution thread, this connector receives that this main frame is assigned and needs and one second writes instruction by what this second execution thread was responsible for carrying out, this flash memory control is after this first execution thread discharges the control of this flash memory chip, the control of distributing this flash memory chip is to this second execution thread, and this second execution thread with this second write instruction pairing 1 second and write data and write to this flash memory chip after, make this second execution thread discharge the control of this flash memory chip.
- 10. flash memory device as claimed in claim 9, wherein after making this second execution thread discharge the control of this flash memory chip, this flash memory control is judging that this first execution thread do not finish this first when writing instruction pairing 1 first and writing the write activity of data as yet, the control of distributing this flash memory chip is to this first execution thread, and finish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
- 11. flash memory device as claimed in claim 8; Wherein in the control of distributing this flash memory chip to this first execution thread; If carry out at this first execution thread this default unit of writing the data write activity during; This connector do not receive that this main frame assigns other write instruction; This flash memory control is after this first execution thread discharges the control of this flash memory chip; Judge whether this first execution thread has finished this first write activity that writes corresponding one first data writing of instructionIf this first execution thread is not finished this first write activity that writes data as yet, this flash memory control distributes the control of this flash memory chip to this first execution thread, and finish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
- 12. flash memory device as claimed in claim 8, wherein this first execution thread is in order to carry out an application program of intelligent card, first to write instruction be Application Protocol Data Unit when instruction to this flash memory control at this, judges to be responsible for carrying out this first what write instruction is this first execution thread.
- 13. flash memory device as claimed in claim 8, wherein this second execution thread is in order to carry out safe digital card read-write application program.
- 14. flash memory device as claimed in claim 8 wherein should be preset the included physical page quantity of the unit of writing less than the included physical page quantity of a physical blocks in this flash memory chip.
- 15. flash memory control, be disposed in the flash memory device that is coupled to a main frame, this flash memory device exists one first execution thread and one second execution thread at least, and comprises a flash memory chip, and this flash memory control comprises:One microprocessor unit;One flash memory chip interface unit is coupled to this microprocessor unit, in order to be coupled to this flash memory chip;One host interface unit is coupled to this microprocessor unit, in order to be coupled to this main frame; AndOne resource allocation unit is coupled to this microprocessor unit, presets the unit of writing in order to define one,What wherein this host interface unit received that this main frame assigns one first writes instruction, this microprocessor unit judge be responsible for carrying out this first write instruction be this first execution thread the time, this resource allocation unit distributes the control of this flash memory chip to this first execution thread, and finish the data write activity of this default unit of writing at this first execution thread after, make this first execution thread discharge the control of this flash memory chip.
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| CN104220991A (en) * | 2012-03-16 | 2014-12-17 | 马维尔国际贸易有限公司 | Architecture to allow efficient storage of data on nand flash memory |
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| CN102193745B (en) | 2015-01-14 |
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