CN102185590A

CN102185590A - Two-phase non-overlap clock generation circuit used for high-speed system

Info

Publication number: CN102185590A
Application number: CN2011100716573A
Authority: CN
Inventors: 虞君新; 吴明远
Original assignee: STEADICHIPS Inc
Current assignee: STEADICHIPS Inc
Priority date: 2011-03-24
Filing date: 2011-03-24
Publication date: 2011-09-14

Abstract

The invention provides a two-phase non-overlap clock generation circuit used for a high-speed system, leading the time clearance to be stable and preventing the time clearance from changing with the change of process and temperature. The two-phase non-overlap clock generation circuit comprises a clock generation circuit with a duty cycle of 50%; an input clock is connected with the input interface of the clock generation circuit with the duty cycle of 50%; the output interface of the clock generation circuit with the duty cycle of 50% is divided into two clock signals that are characterized in that one of the two clock signals is directly connected with the clock generation circuit A with the duty cycle of a%; the other clock signal is connected with a phase inverter and is subsequently connected with a clock generation circuit B with the duty cycle of a%; the cycle of the clock generation circuit A with the duty cycle of a% is identical to the cycle of one clock signal; the start point of the ascending edge of the signal generated by the clock generation circuit A with the duty cycle of a% is synchronized with the start point of the ascending edge of one clock signal, wherein a is less than 50.

Description

The two-phase that the is used for High Speed System clock generation circuit that do not overlap

Technical field

The present invention relates to the technical field of clock circuit, be specially the two-phase that the is used for High Speed System clock generation circuit that do not overlap.

Background technology

The two-phase clock generation circuit that do not overlap is widely used in the switched-capacitor circuit, mainly contains two input nand gates and inverter traditionally and forms.Because circuit is comparatively fixing and simple the use, so use comparatively extensive.Two-phase does not overlap the clock schematic diagram as shown in Figure 1.

Traditional two-phase does not overlap clock generation circuit as shown in Figure 2, and the time-delay of inverter among the figure 1 series connection has constituted the do not overlap gap of clock of two-phase.Respectively as the input of NAND gate, the output after the output of NAND gate is delayed time through inverter was connected to another input of NAND gate respectively as input after input clock and this clock were anti-phase.In process described above, form the do not overlap parameter of clock circuit performance of a significant effects two-phase: clock gap (Clock gap), that is: the time slot of the rising edge of the trailing edge of one road clock and another road clock, in considerable high-speed applications, the user wishes that this time slot can be comparatively stable, thereby can obtain overall performance preferably under various process conditions.

Along with developing rapidly that high-frequency clock is used, the clock speed of switched-capacitor circuit is also improving constantly, and the switched-capacitor circuit that reaches GHz has been arranged at present.The two-phase of finding traditional form in the middle of the actual design clock circuit that do not overlap can not adapt to the requirement of speed-sensitive switch condenser network.Shown in figure one, traditional method time-delay is produced by inverter, because the time-delay of inverter is along with flow-route and temperature can produce drift, the drift scope reaches more than 30%, along with clock speed reaches GHz, the drift of tens psecs all can produce fatal influence to the performance of circuit, so just gives in the high-speed applications and has brought challenge.

Summary of the invention

At the problems referred to above, the invention provides the two-phase that the is used for High Speed System clock generation circuit that do not overlap, it makes the clock gap stable, can not change along with the variation of flow-route and temperature.

The two-phase that the is used for High Speed System clock generation circuit that do not overlap, its technical scheme is such: it comprises that duty ratio is 50% clock forming circuit, input clock connects the input interface that described duty ratio is 50% clock forming circuit, described duty ratio is that the output interface of 50% clock forming circuit is divided into the two-way clock signal, it is characterized in that: wherein one tunnel clock signal of described two-way clock signal directly connects the clock forming circuit A that duty ratio is a%, connecting duty ratio behind another road clock signal connection inverter is the clock forming circuit B of a%, described duty ratio is that the cycle of the cycle of clock forming circuit A of a% and one tunnel clock signal wherein is identical, and described duty ratio is that the starting point of the starting point of rising edge of the signal that generated of the clock forming circuit A of a% and described wherein one tunnel rising edge of clock signal is synchronous; Described duty ratio is that cycle of clock forming circuit B of a% is identical with the cycle of described another road clock signal, and the starting point of the rising edge of the signal that the clock forming circuit B that described duty ratio is a% is generated and described another road clock signal are synchronous by the starting point of the rising edge of corresponding output signal behind the inverter; Wherein a ﹤ 50.

After adopting structure of the present invention, to preestablish the starting point of its rising edge and its duty ratio corresponding respectively be 50% clock synchronization because duty ratio is the clock forming circuit A of a%, clock forming circuit B that duty ratio is a%, promptly the time difference between the rising edge of the trailing edge of Shu Chu road clock and another road clock is fixed, time difference is not with the variation of flow-route and temperature, all the time proportional with the cycle of clock, so when the cycle of setting clock signal is T, then the clock gap is (50-a) %T, and this clock gap is stable.

Description of drawings

Fig. 1 is the do not overlap schematic diagram of clock of two-phase;

Fig. 2 is the existing two-phase clock generation circuit structural representation that do not overlap;

Fig. 3 is the do not overlap structural representation of clock generation circuit of two-phase of the present invention;

Fig. 4 is the oscillogram schematic diagram of each clock input, output after the employing structure of the present invention.

Embodiment

See Fig. 3, it comprises that duty ratio is 50% clock forming circuit, input clock CLKIN connects the input interface that duty ratio is 50% clock forming circuit, duty ratio is that the output interface of 50% clock forming circuit is divided into the two-way clock signal, wherein one tunnel clock signal Va of two-way clock signal directly connects the clock forming circuit A that duty ratio is a%, export one tunnel output signal CLKOUTA afterwards, another road clock signal Va generates clock signal Vb after connecting inverter, it is the clock forming circuit B of a% that clock signal Vb connects duty ratio, export another road output signal CLKOUTB afterwards, duty ratio is that cycle of clock forming circuit A of a% is identical with the cycle of clock signal Va, and duty ratio is that the starting point of rising edge of the starting point of rising edge of the signal that generated of the clock forming circuit A of a% and clock signal Va is synchronous; Duty ratio is that cycle of clock forming circuit B of a% is identical with the cycle of clock signal Vb, and duty ratio is that the starting point of the starting point of rising edge of the signal that generated of the clock forming circuit B of a% and clock signal Vb rising edge is synchronous; Wherein a ﹤ 50.

The oscillogram schematic diagram of each clock input, output is seen Fig. 4 after employing Fig. 3 structure, and the cycle of setting input clock CLKIN is T, and then the clock gap is (50-a) %T, and the clock gap is stable.

Claims

1. the two-phase that the is used for High Speed System clock generation circuit that do not overlap, it comprises that duty ratio is 50% clock forming circuit, input clock connects the input interface that described duty ratio is 50% clock forming circuit, described duty ratio is that the output interface of 50% clock forming circuit is divided into the two-way clock signal, it is characterized in that: wherein one tunnel clock signal of described two-way clock signal directly connects the clock forming circuit A that duty ratio is a%, connecting duty ratio behind another road clock signal connection inverter is the clock forming circuit B of a%, described duty ratio is that the cycle of the cycle of clock forming circuit A of a% and one tunnel clock signal wherein is identical, and described duty ratio is that the starting point of the starting point of rising edge of the signal that generated of the clock forming circuit A of a% and described wherein one tunnel rising edge of clock signal is synchronous; Described duty ratio is that cycle of clock forming circuit B of a% is identical with the cycle of described another road clock signal, and the starting point of the rising edge of the signal that the clock forming circuit B that described duty ratio is a% is generated and described another road clock signal are synchronous by the starting point of the rising edge of corresponding output signal behind the inverter; Wherein a ﹤ 50.