CN102185045B - SiO in light emitting semiconductor device manufacture process2the surface treatment method of layer - Google Patents

SiO in light emitting semiconductor device manufacture process2the surface treatment method of layer Download PDF

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CN102185045B
CN102185045B CN201110084922.1A CN201110084922A CN102185045B CN 102185045 B CN102185045 B CN 102185045B CN 201110084922 A CN201110084922 A CN 201110084922A CN 102185045 B CN102185045 B CN 102185045B
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sio
layer
nitrogen
light emitting
semiconductor device
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CN102185045A (en
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黄涛
张娟
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Jingneng Optoelectronics Jiangxi Co ltd
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Jingneng Optoelectronics Jiangxi Co ltd
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Abstract

The invention discloses SiO in a kind of light emitting semiconductor device manufacture process2The surface treatment method of layer, relates to the manufacture method of a kind of light emitting semiconductor device, is used for solving SiO2Layer surface photoresist in subsequent processing operations because of the problem of high temperature generation serious deformation.It comprises the following steps: grow SiO on wafer to be processed2Layer;SiO is processed with plasma nitrogen carrier gas body2The surface of layer, makes SiO2Surfaces nitrided;At the SiO through nitrogen treatment2Mask glue it is coated with on surface.The present invention can improve product quality, and time-consuming, improves production efficiency, has saved adhesive.The present invention is used as the SiO of mask2A series of SiO such as trimming technique, sapphire surface passivation process2Photomask surface processes technique.

Description

SiO in light emitting semiconductor device manufacture process2The surface treatment method of layer
Technical field
The present invention relates to the manufacture method of a kind of light emitting semiconductor device, particularly relate to the surface treatment method of silicon dioxide layer on wafer.
Background technology
After silicon substrate or Grown on Sapphire Substrates gallium nitride wafer, the pilot process before making chip also needs to repeatedly photoetching treatment, wherein photoetching process needs to be formed silicon dioxide (SiO on wafer2) layer.
Before the chip unit on wafer is carried out trimming process, need first to grow on table top the SiO for mask2Layer, then at SiO2Positive glue (photoresist) is got rid of on Ceng.In this technical scheme, positive glue is applied directly to SiO2On layer surface, it may occur that this photoresist comes off in development or corrosion process.
Currently in order to process the problem that photoresist comes off in subsequent technique, those skilled in the art first get rid of adhesive before using positive-glue removing, to increase positive glue and SiO2Viscosity between Ceng.The process getting rid of adhesive needs independent whirl coating and baking time.
Above-mentioned SiO2Layer process of surface treatment, in the case of getting rid of adhesive, in follow-up trimming technique, owing to trimming temperature is at 164 DEG C, photoresist because high temperature occurs expanding after-contraction phenomenon, thus can cause mask area to reduce or fall glue phenomenon during against corrosion.Referring to some chip unit 20 is distributed on wafer 10 shown in Fig. 1, the photoresist 30 on chip unit 20 presents the most contraction-like, owing to photoresist 30 becomes irregular, so this chip unit cannot realize successful trimming and process.Above-mentioned phenomenon the most generally exists in wafer processing procedure, and it directly contributes chip quality and declines and yield reduction.
Summary of the invention
The technical problem to be solved is: provide SiO in a kind of light emitting semiconductor device manufacture process2The surface treatment method of layer, is used for solving SiO2Layer surface photoresist in subsequent processing operations because of the problem of high temperature generation serious deformation.
In order to solve above-mentioned technical problem, the present invention proposes SiO in a kind of light emitting semiconductor device manufacture process2The surface treatment method of layer, comprises the following steps:
Wafer to be processed grows SiO2Layer;
SiO is processed with plasma nitrogen carrier gas body2The surface of layer, makes SiO2Surfaces nitrided;
At the SiO through nitrogen treatment2Mask glue it is coated with on surface.
Preferably, described SiO2Layer is as mask layer, and this processing method is further comprising the steps of:
After coating mask glue, the SiO that etching is not hidden by mask glue2Part;
Remove mask glue;
Wafer is carried out trimming process;
Remove the described SiO of mask2Layer.
This preferred version is in trimming technique.
Preferably, described SiO2Layer is as passivation layer, and this processing method is further comprising the steps of: after coating mask glue, the SiO that etching is not hidden by mask glue2Part;
Then remove mask glue, expose the SiO as passivation layer2Layer.
This preferred version is in passivation technology.
Preferably: described plasma nitrogen carrier gas body is nitrogen, laughing gas or their mixing.In prior art, some can provide the gaseous compound of plasma nitrogen-atoms all can require it is that other elements of compound are not involved in SiO as the raw material of the present invention simultaneously at the reaction temperatures2Bonding reaction effect, or do not produce interference impact.
Preferably: described plasma nitrogen carrier gas body source is the nitrogenous material that reaction generates simple substance nitrogen under plasma ambient.
Preferably, growth indium-gallium-aluminum-nitrogen epitaxial multilayer structure, is fabricated to described wafer to be processed on a silicon substrate.
Preferably, growth indium-gallium-aluminum-nitrogen epitaxial multilayer structure, is fabricated to described wafer to be processed on a sapphire substrate.
Preferably: the ambient temperature that described plasma nitrogen carrier gas body processes is 230~290 DEG C, and the reaction flow of simple substance nitrogen is 450~550SCCM.
Preferably: the ambient temperature that described plasma nitrogen carrier gas bromhidrosis processes is 260 DEG C, and the reaction flow of elemental nitrogen is 500SCCM, and the time is 2min.
Beneficial effects of the present invention:
Compared to existing technology, the present invention is at growth SiO2To SiO after Ceng2The surface of layer carries out plasma nitridation process, plasma nitrogen and SiO2There is bonding reaction, at SiO2Silicon nitrogen oxygen thing matter that Surface Creation is complicated and at SiO2Surface forms the structure of uniqueness, and beneficially photoresist is attached to SiO2Surface, under the hot environment in follow-up trimming technique, photoresist will not shrink, and is kept substantially and original-pack is attached to SiO2On.Technical solution of the present invention, compared with the scheme increasing adhesive used at present, has in subsequent machining technology: photoresist is indeformable, do not reduce or deform little;Do not fall glue;Tube core occurs without the good result of Pinhole-shaped surface corrosion, and can be time-consuming, improves production efficiency, has saved the further advantage of adhesive.The present invention is used as the SiO of mask2A series of SiO such as trimming technique, sapphire surface passivation process2Photomask surface processes technique.
Accompanying drawing explanation
Fig. 1 is in prior art, the schematic diagram that the photoresist mask of wafer surface deforms after high temperature.
After Fig. 2 is application the technology of the present invention, the schematic diagram of the photoresist mask of wafer surface.
Fig. 3 to Fig. 9 is the process schematic of the present invention, and wherein Fig. 3 is deposition SiO on wafer2Layer, Fig. 4 is at SiO2Whirl coating on layer, Fig. 5 is graphical photoresist, and Fig. 6 is graphical SiO2Layer, Fig. 7 is to remove photoresist, and Fig. 8 is to wafer cell trimming, and Fig. 9 is to remove SiO2Layer.
Identifier declaration in figure: wafer 10, chip unit 20, photoresist 30;
SiO2Layer 1, epitaxial multilayer construction unit 2, silicon substrate 3, positive glue 4, chip unit 5, groove 6.
Detailed description of the invention
The present invention proposes SiO in a kind of light emitting semiconductor device manufacture process2The surface treatment method of layer, it comprises the following steps: grow SiO on wafer to be processed2Layer;SiO is processed with plasma nitrogen carrier gas body2The surface of layer, makes SiO2Surfaces nitrided;At the SiO through nitrogen treatment2Mask glue it is coated with on surface.
Embodiments of the invention one, it is applied to the trimming technique of wafer.On silicon substrate 3, first grow indium-gallium-aluminum-nitrogen epitaxial multilayer structure, and the preparation process before a series of trimming techniques such as the operation completing cutting 6, being fabricated to the wafer of pending trimming processing, epitaxial multilayer structure is divided into epitaxial multilayer construction unit 2 on this wafer.
Then above-mentioned wafer is put in PECVD device, be passed through silane, nitrogen and laughing gas, referring to shown in Fig. 3, wafer to be processed grows SiO2Layer 1.At SiO2After the growth of layer 1 completes, stop being passed through silane, continue to be passed through nitrogen and laughing gas (N2O), ambient temperature is 230 DEG C~290 DEG C, and gas flow controls 450~550sccm, time about 2min;Wherein, optimum temperature is 260 DEG C, and gas flow is 500sccm, and the time is 2 minutes, processes SiO with plasma nitrogen carrier gas body2The surface of layer 1, makes SiO2Layer 1 surfaces nitrided.SiO is completed by above-mentioned technique2Layer surface plasma nitrogen takes out wafer, referring to Fig. 4, at the SiO through nitrogen treatment after processing2The positive glue 4 of mask it is coated with on layer surface.
Referring to Fig. 5, then align glue 4 and be patterned photoetching, referring to Fig. 6, further according to positive glue pattern to SiO2Layer is patterned process.Referring to Fig. 7, then remove SiO2Positive glue 4 on layer 1, referring to Fig. 8, further according to the SiO on epitaxial multilayer construction unit 22The mask scope of layer removes the burr edge of epitaxial multilayer construction unit 2.Referring to Fig. 9, after completing trimming, finally etch away the SiO as mask layer2Layer 1.
Referring to shown in Fig. 2, the photoresist (i.e. positive glue 4) on the wafer that the technology of the present invention processes, essentially without deforming, is so conducive to the enforcement of follow-up trimming operation.
In above-mentioned technique, it is also possible to complete SiO2After layer growth, only it is passed through nitrogen, and is not passed through laughing gas, i.e. stop being passed through silane and laughing gas.
Plasma nitrogen carrier gas body source is nitrogen, or the simple substance nitrogen decomposing out for laughing gas.Some can provide the compound of plasma nitrogen-atoms all can require it is that other elements of compound are not involved in SiO as the raw material of the present invention simultaneously at the reaction temperatures2Bonding reaction effect, or do not produce interference impact.Nitrogen carrier gas body is in addition to the above-mentioned nitrogen mentioned and laughing gas, and other common nitrogen carrier gas body of this area is included in the interior organic nitrogen compound in gaseous state of said temperature all in the nitrogen carrier gas body protection domain of indication of the present invention.
Above-mentioned example is the backing material of growth on silicon substrate, and the present invention program can also apply growth indium-gallium-aluminum-nitrogen epitaxial multilayer structure on a sapphire substrate, to be fabricated to wafer to be processed.Another embodiment of the presently claimed invention, is by SiO2Layer is as the application examples of sapphire chip surface passivation layer.
Complete epitaxial wafer cutting, do the series of processes such as electrode after, in order to prevent chip edge from leaking electricity, need chip is passivated to process.Passivation uses SiO2Insulant.Whole process is summarized as follows:
The wafer carry out electrode deposits SiO2Passivation layer.Then SiO is processed with plasma nitrogen carrier gas body2The surface of layer.Then at the SiO through nitrogen treatment2The photoresist of mask is coated on surface.After coating photoresist, it is patterned process, removes the part corresponding to electrode.Then it is not photo-etched, according to graphical photoresist etching, the SiO that glue hides2Part;Then remove photoresist, expose the SiO as passivation layer2Layer.

Claims (7)

1. SiO in a light emitting semiconductor device manufacture process2The surface treatment method of layer, including following step Rapid:
Wafer to be processed grows SiO2Layer;
SiO is processed with plasma nitrogen carrier gas body2The surface of layer, makes SiO2Surfaces nitrided;Described plasma carries Nitrogen is nitrogen, laughing gas or their mixing;
At the SiO through nitrogen treatment2Mask glue it is coated with on surface.
SiO in light emitting semiconductor device manufacture process the most according to claim 12The surface of layer Reason method, it is characterised in that described SiO2Layer is as mask layer, and this processing method is further comprising the steps of:
After coating mask glue, the SiO that etching is not hidden by mask glue2Part;
Remove mask glue;
Wafer is carried out trimming process;
Remove the described SiO of mask2Layer.
SiO in light emitting semiconductor device manufacture process the most according to claim 12The surface of layer Reason method, it is characterised in that described SiO2Layer is as passivation layer, and this processing method is further comprising the steps of: After coating mask glue, the SiO that etching is not hidden by mask glue2Part;
Then remove mask glue, expose the SiO as passivation layer2Layer.
SiO in light emitting semiconductor device manufacture process the most according to claim 12The surface of layer Reason method, it is characterised in that:
Growth indium-gallium-aluminum-nitrogen epitaxial multilayer structure, is fabricated to described wafer to be processed on a silicon substrate.
SiO in light emitting semiconductor device manufacture process the most according to claim 12The surface of layer Reason method, it is characterised in that:
Growth indium-gallium-aluminum-nitrogen epitaxial multilayer structure, is fabricated to described wafer to be processed on a sapphire substrate.
SiO in light emitting semiconductor device manufacture process the most according to claim 12The surface of layer Reason method, it is characterised in that: the ambient temperature that described plasma nitrogen carrier gas body processes is 230~290 DEG C, The reaction flow of simple substance nitrogen is 450~550SCCM.
SiO in light emitting semiconductor device manufacture process the most according to claim 12The surface of layer Reason method, it is characterised in that: the ambient temperature that described plasma nitrogen carrier gas bromhidrosis processes is 260 DEG C, single The reaction flow of matter nitrogen is 500SCCM, and the time is 2min.
CN201110084922.1A 2011-04-06 SiO in light emitting semiconductor device manufacture process2the surface treatment method of layer Active CN102185045B (en)

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CN102185045B true CN102185045B (en) 2016-12-14

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101295662A (en) * 2007-04-24 2008-10-29 中芯国际集成电路制造(上海)有限公司 Metallic silicide blocking structure forming method and semiconductor device thereof
CN101807527A (en) * 2010-03-23 2010-08-18 中国电子科技集团公司第十三研究所 Method for manufacturing SiC MESFET gate
CN101958234A (en) * 2009-07-16 2011-01-26 中芯国际集成电路制造(上海)有限公司 Photoetching manufacturing process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101295662A (en) * 2007-04-24 2008-10-29 中芯国际集成电路制造(上海)有限公司 Metallic silicide blocking structure forming method and semiconductor device thereof
CN101958234A (en) * 2009-07-16 2011-01-26 中芯国际集成电路制造(上海)有限公司 Photoetching manufacturing process
CN101807527A (en) * 2010-03-23 2010-08-18 中国电子科技集团公司第十三研究所 Method for manufacturing SiC MESFET gate

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Address after: 330029 No. 699, aixihu North Road, high tech Zone, Nanchang City, Jiangxi Province

Patentee after: Jingneng optoelectronics Co.,Ltd.

Address before: 330029 No. 699, aixihu North Road, high tech Zone, Nanchang City, Jiangxi Province

Patentee before: LATTICE POWER (JIANGXI) Corp.