CN102184847A - Semiconductor structure and forming method thereof, PMOS (P-channel Metal Oxide Semiconductor) transistor and forming method thereof - Google Patents
Semiconductor structure and forming method thereof, PMOS (P-channel Metal Oxide Semiconductor) transistor and forming method thereof Download PDFInfo
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Abstract
The invention relates to a semiconductor structure and a forming method thereof, a PMOS (P-channel Metal Oxide Semiconductor) transistor and a forming method thereof. The forming method of the semiconductor structure comprises the following steps of: providing a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate sequentially comprises a silicon base, an insulated buried layer and top layer silicon; etching the top layer silicon until the insulated buried layer is exposed to form an active region; forming insulated oxide layers on the side wall and the top of the top layer silicon in the active region; and performing thermal oxidization treatment to ensure that the top layer silicon is bent upwards. The invention further provides a semiconductor structure, a PMOS transistor structure formed on the semiconductor structure and a forming method of the PMOS transistor structure. The invention aims to perform thermal oxidization treatment on the top layer silicon in a PMOS transistor device region so that the edge of the top layer silicon is bent upwards, so that the compression stress of the top layer silicon is enhanced and the performance of a subsequently-manufactured PMOS device is enhanced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor structure and formation method, PMOS transistor and formation method.
Background technology
Along with constantly reducing of cmos device size, transistorized short-channel effect of CMOS and carrier mobility degradation effect become increasingly conspicuous.And, also become increasingly conspicuous to the inhibition ability of device short channel effect and to the demand of the hoisting power of carrier mobility along with raising to the semiconductor device performance requirement.
Existing short-channel effect for suppression device, the method that adopts is doping content, increase source/leakage light doping section (the LDD district) of improving substrate usually, perhaps adopts the thinner silicon substrate structure of thickness in silicon-on-insulator (SOI) structure.But the doping content that improves substrate can cause the dead resistance that the threshold voltage of device improves, increase LDD district then can increase device, the increase that the thinner silicon substrate structure of employing thickness can increase source/drain series resistance.
On the other hand, after device size enters into below the 100nm, make the short channel effect that improves device by the further reduction of device size difficulty more that becomes.In the prior art, under the situation that does not reduce device size, normally adopt strained silicon technology, in raceway groove, introduce stress, thereby improve the mobility of charge carrier (electronics and/or hole) and the performance of raising transistor device.The principle of described strained silicon technology is: by design device architecture, change device material and processing step, introduce stress at transistor channel region, change the lattice structure of channel region substrate, improve mobility of charge carrier rate in the raceway groove.
Another kind of improve the mobility of charge carrier (electronics and/or hole) and improve the method for performance of transistor device such as Chinese patent application number be in 200610164675.5 the patent application disclosed by implanting impurity ion on the silicon nitride layer that forms on the substrate (for example, chromium Ge), can reduce the lattice constant of silicon nitride layer like this, the crystal structure of silicon nitride layer is changed, thereby in the compression stress of silicon nitride layer generation towards grid; This compression stress passes to substrate by buffer oxide layer then, makes the silicon crystal lattice compression that exists in channel region, thereby can improve the mobility of charge carrier rate that moves in channel region.But such method not only makes whole process flow comparatively complicated, and ion implantation technology also can exert an adverse impact to substrate.
Therefore, need provide a kind of technical scheme preferably to solve the problems referred to above.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor structure and formation method, PMOS transistor and formation method, improves the mobility of charge carrier in the channel region of substrate, thereby improves the performance of the transistor device of follow-up making.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprise the steps: to provide silicon-on-insulator substrate, described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively; The described top layer silicon of etching is formed with the source region to exposing insulating buried layer; Insulating oxide is formed on top layer silicon sidewall and top at active area; Carry out thermal oxidation, the top layer silicon edge is bent upwards.
Alternatively, the time range of described thermal oxidation 5 seconds-4 hours, temperature range at 700-1050 degree centigrade.
Alternatively, described thermal oxidation technology is carried out in the stove heat pipe.
Alternatively, the method for the described top layer silicon of etching is a dry etching.
Alternatively, the material of described insulating buried layer is a silica.
Alternatively, the method for formation insulating oxide is that rapid thermal oxidation is handled.
A kind of semiconductor structure comprises silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively, and described top layer silicon is bent upwards.
Alternatively, the material of described insulating buried layer is a silica.
The transistorized formation method of a kind of PMOS comprises the steps: to provide silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively; The described top layer silicon of etching is formed with the source region to exposing insulating buried layer; Insulating oxide is formed on top layer silicon sidewall and top at active area; Carry out thermal oxidation, top layer silicon is bent upwards; On described top layer silicon, form gate dielectric layer and polysilicon gate successively; On the top layer silicon of described polysilicon gate both sides, form side wall; Formation source/drain electrode in the top layer silicon of described polysilicon gate and side wall both sides.
Alternatively, the time range of described thermal oxidation 5 seconds-4 hours, temperature range at 700-1050 degree centigrade.
Alternatively, described thermal oxidation technology is carried out in the stove heat pipe.
Alternatively, the method for the described top layer silicon of etching is a dry etching.
A kind of PMOS transistor arrangement comprises silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively, and described top layer silicon is bent upwards; On described top layer silicon, be formed with gate dielectric layer and polysilicon gate successively; Be formed with side wall in described polysilicon gate both sides; In the top layer silicon of described polysilicon gate and side wall both sides, form active/drain electrode.
Compared with prior art, technical scheme of the present invention has the following advantages: by the top layer silicon on silicon-on-insulator (SOI) substrate is carried out thermal oxidation, the silicon atom at the close insulating oxide place, edge in oxygen molecule and the top layer silicon is fully reacted, the volume of described top layer silicon is increased, make the top layer silicon edge warpage that makes progress, the top layer silicon that formation is bent upwards has strengthened the compression stress of described top layer silicon.
Further, make the PMOS transistor as substrate,, make the also corresponding raising of mobility of charge carrier (hole) in the substrate channel region, thereby improved the transistorized performance of PMOS because the compression in the top layer silicon strengthens with the make progress top layer silicon of warpage of edge.
Description of drawings
Fig. 1 is a kind of schematic flow sheet that forms the semiconductor structure embodiment of the present invention;
Fig. 2 to Fig. 5 is the forming process schematic diagram of a kind of semiconductor structure of the present invention;
Fig. 6 is the schematic flow sheet of the embodiment of a kind of PMOS of formation transistor arrangement of the present invention;
Fig. 7 to Fig. 8 is the forming process schematic diagram of the specific embodiment of a kind of PMOS transistor arrangement of the present invention;
Fig. 9 to Figure 18 is the forming process schematic diagram of the specific embodiment of a kind of cmos device structure of the present invention.
Embodiment
The inventor finds that after dimensions of semiconductor devices enters into below the 100nm short channel effect that improves device by further reduction of device size becomes difficult more.With the PMOS transistor is example, and the technical staff wishes to strengthen the compression stress of raceway groove in channel region, thereby improves the mobility of holoe carrier, finally improves the transistorized performance of PMOS.
At the problems referred to above, the invention provides a kind of semiconductor structure and formation method, PMOS transistor arrangement and formation method.
At first, with reference to shown in Figure 1, a kind of schematic flow sheet that forms the embodiment of semiconductor structure,
Step S1: silicon-on-insulator substrate is provided, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively.
Step S2: the described top layer silicon of etching is formed with the source region to exposing insulating buried layer.
Step S3: insulating oxide is formed on top layer silicon sidewall and top at active area.
Step S4: carry out thermal oxidation, the top layer silicon edge is bent upwards.
Semiconductor structure based on above-mentioned execution mode forms comprises silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively, and described top layer silicon is bent upwards.
Particularly, when carrying out thermal oxidation, oxygen molecule is easy to diffuse to top layer silicon by insulating oxide, make described oxygen molecule fully react the back with the part silicon at close insulating oxide place, top layer silicon edge and generate silica, owing in described top layer silicon, fed oxygen molecule, make the volume of described top layer silicon increase, and top layer silicon and oxygen molecule reaction the closer to insulating oxide are abundant more, and oxygen molecule can not react with the insulating oxide outside the described top layer silicon, therefore forms the top layer silicon that is bent upwards.
Need to prove that the top layer silicon that is bent upwards that above-mentioned technological process finally forms is used as the transistorized substrate of PMOS in subsequent technique on described silicon-on-insulator (SOI) substrate.Compare with existing silicon substrate, the described top layer silicon that is bent upwards has stronger compression stress, has improved the mobility of charge carrier in the substrate channel region, thereby has improved the transistorized performance of PMOS.
Be described in detail forming semiconductor structure below in conjunction with accompanying drawing.
Embodiment one
Fig. 2 to Fig. 5 is the embodiment schematic diagram that the present invention forms a kind of semiconductor structure.
At first, as shown in Figure 2, provide silicon-on-insulator substrate, described silicon-on-insulator substrate comprises silicon base 11, insulating buried layer 12 and top layer silicon 13 successively.
Alternatively, the material of wherein said insulating buried layer 12 is silica.
As shown in Figure 3, the described top layer silicon 13 of etching is formed with the source region to exposing insulating buried layer 12 on described insulating buried layer 12.Concrete technology is as follows: prior to applying one deck photoresist layer (not shown) on the described top layer silicon 103, through after the photoetching process, define the active area figure; Be mask again with the photoresist layer, to exposing described insulating buried layer 12, on described insulating buried layer 12, be formed with source region top layer silicon 13a along the described top layer silicon 13 of active area pattern etching.
Then, as shown in Figure 4, form insulating oxide 14a at sidewall and the top of active area top layer silicon 13a, the material of wherein said insulating oxide is a silica.
Alternatively, the method that forms described insulating oxide silicon layer is that rapid thermal oxidation is handled.Wherein, described rapid thermal oxidation temperature ranges is 400-1300 degree centigrade.
Then, as shown in Figure 5, carry out thermal oxidation, described active area top layer silicon 13a is bent upwards.
Alternatively, described thermal oxidation is carried out in the stove heat pipe, and the time of wherein said thermal oxidation is longer, and its concrete time range was at 5 seconds～4 hours; The temperature range of described thermal oxidation is at 700-1050 degree centigrade.
When carrying out thermal oxidation, oxygen molecule is easy to diffuse in the described active area top layer silicon 13a by insulating oxide 14a, makes described oxygen molecule fully react the back with the part silicon of the close insulating oxide 14 of active area top layer silicon 13a and generates silica.Owing in described active area top layer silicon 13a, fed oxygen molecule, make the volume of described active area top layer silicon 13a increase, and abundant more the closer to top layer silicon and the oxygen molecule reaction of insulating oxide 14a.Because oxygen molecule can not react with insulating oxide 14a, when the volume of described active area top layer silicon 13a increased, the volume of described insulating oxide 14a can not increase so again, therefore formed the active area top layer silicon 13a that the edge is bent upwards.
Need to prove that described thermal oxidation can be divided into by used oxidizing atmosphere: dry-oxygen oxidation, steam oxidation and wet-oxygen oxidation.Wherein, described dry-oxygen oxidation be with the pure oxygen of drying as oxidizing atmosphere, at high temperature oxygen molecule directly with pasc reaction generation silica.Described steam oxidation is to be oxidizing atmosphere with high purity water steam, generates silicon dioxide by the silicon atom and the water molecule reaction of silicon face.Described wet-oxygen oxidation is the mixing of dry-oxygen oxidation and steam oxidation, and oxidation rate is between between the two.Wet-oxygen oxidation is with water formed oxygen and the gas-vapor mix formation oxidizing atmosphere of dry oxygen by heating.When the method for the direct synthetic water steam of crystal reaction tube import department is carried out steam oxidation,, can regulate water vapor pressure with high-purity hydrogen and oxygen, improve the quality of the silica that generates by changing the ratio of hydrogen and oxygen.Those skilled in the art can select the thermal oxidation of above-mentioned any oxidizing atmosphere according to different technological requirements, do not repeat them here.
The semiconductor structure that forms based on the foregoing description as shown in Figure 5, described semiconductor structure comprises: silicon-on-insulator substrate, wherein said silicon-on-insulator substrate comprise silicon base 11, insulating buried layer 12 successively; Active area top layer silicon 13a is positioned on the insulating buried layer 12, and described active area top layer silicon 13a edge is bent upwards; Insulating oxide 14a is positioned at top and the sidewall of described active area top layer silicon 13a.
In addition to the implementation, before carrying out subsequent technique, can remove described insulating oxide 14a by dry method or wet etching.
Further, in subsequent technique, the active area top layer silicon 13a that present embodiment forms is used to make the transistorized substrate of PMOS.Compare with existing silicon substrate, the described top layer silicon that is bent upwards has stronger compression stress, has improved the mobility of charge carrier in the substrate channel region, thereby has improved the transistorized performance of PMOS.
Fig. 6 is the schematic flow sheet of the embodiment of a kind of PMOS of formation transistor arrangement of the present invention.As shown in Figure 6, execution in step S11 provides silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively; Execution in step S12, the described top layer silicon of etching is formed with the source region to exposing insulating buried layer; Execution in step S13 forms insulating oxide at the top layer silicon sidewall and the top of active area; Execution in step S14 carries out thermal oxidation, and the top layer silicon edge is bent upwards; Execution in step S15 forms gate dielectric layer and polysilicon gate successively on described top layer silicon; Execution in step S16 forms side wall on the top layer silicon of described polysilicon gate both sides; Execution in step S17, formation source/drain electrode in the top layer silicon of described polysilicon gate and side wall both sides.
The PMOS transistor arrangement that forms based on above-mentioned execution mode comprises: silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively, described top layer silicon is bent upwards; On described top layer silicon, be formed with gate dielectric layer and polysilicon gate successively; Be formed with side wall in described polysilicon gate both sides; In the top layer silicon of described polysilicon gate and side wall both sides, form active/drain electrode.
Be described forming the transistorized detailed process of PMOS below in conjunction with accompanying drawing.
Embodiment two
With reference to figure 7 to shown in Figure 8 be the schematic diagram of a kind of PMOS transistor forming process of the present invention.
As shown in Figure 7, provide silicon-on-insulator substrate, the active area top layer silicon 13a in the wherein said silicon-on-insulator substrate is bent upwards, and the concrete method that forms the active area top layer silicon 13a that is bent upwards does not repeat them here with described in the embodiment one.
Continuation forms gate dielectric layer 15 and polysilicon gate 16 with reference to figure 7 successively on described active area top layer silicon 13a; In the active area top layer silicon 13a of polysilicon gate 16 both sides, be formed with shallow doped region 14.Concrete formation technology is as follows: apply the first photoresist layer (not shown) on active area top layer silicon 13a; Through exposure imaging, define n trap figure; With first photoresist layer is mask, adopts ion implantation that active area top layer silicon 13a is mixed, and forms MOS trap (not shown); Remove first photoresist layer.On active area top layer silicon 13a, form one deck gate dielectric layer 15 with thermal oxidation method, on gate dielectric layer 15, form polysilicon layer; On polysilicon layer, apply the second photoresist layer (not shown),, define gate patterns through exposure imaging; To exposing active area top layer silicon 13a, form polysilicon gate 16 along gate patterns etch polysilicon layer and gate dielectric layer 15; Then, be mask with polysilicon gate 16, in active area top layer silicon 13a, carry out ion and inject, form shallow doped region 14.
Then, as shown in Figure 8, on the active area top layer silicon 13a of polysilicon gate 16 both sides, form side wall 17.Alternatively, the material of wherein said side wall 17 is silicon nitride, silica and silicon nitride combination, the perhaps combination of silica, silicon nitride and silica.Further, be mask with side wall 17 and polysilicon gate 16, in the active area top layer silicon 13a of both sides, inject ion, form source electrode 18a and drain electrode 18b, the doping depth of described source electrode 18a and drain electrode 18b is darker than shallow doped region 14.The final PMOS transistor as shown in Figure 8 that on described active area top layer silicon 13a, formed.
Compare with the existing P MOS transistor, because described active area top layer silicon 13a is bent upwards, so just increased the compression stress of active area top layer silicon 13a, thereby the mobility of charge carrier (hole) has finally improved the transistorized performance of formation PMOS in the transistorized channel region of PMOS that to have improved with described active area top layer silicon 13a be substrate.
The PMOS transistor that forms based on the foregoing description comprises: silicon-on-insulator substrate, described silicon-on-insulator substrate comprises silicon base 11, insulating buried layer 12 and active area top layer silicon 13a successively, wherein said active area top layer silicon 13a edge is bent upwards, in order to strengthen the compression of top layer silicon inside; Gate dielectric layer 15 is positioned on the active area top layer silicon 13a; Polysilicon gate 16 is positioned on the gate dielectric layer 15; Shallow doped region 14 is positioned at the active area top layer silicon 13a of polysilicon gate 16 both sides; Side wall 17 is positioned on the active area top layer silicon 13a of polysilicon gate 16 both sides; Source electrode 18a and drain electrode 18b are positioned at the active area top layer silicon 13a of described polysilicon gate 16 and side wall 17 both sides, and the shallow doped region of the depth ratio of described source electrode 18a and drain electrode 18b 14 is dark.
Further, in CMOS technology, can also realize technique effect of the present invention in the following way.
Embodiment three
Fig. 9 to Figure 18 forms the embodiment process schematic diagram of cmos device structure for the present invention.
At first, as shown in Figure 9, provide silicon-on-insulator substrate, wherein said silicon-on-insulator substrate comprises silicon base 11, insulating buried layer 12 and top layer silicon 13 successively.Alternatively, the material of wherein said insulating buried layer 12 is silica or silicon nitride.
As shown in figure 10, the described top layer silicon 13 of etching forms the active area top layer silicon 13a of PMOS device area and the active area top layer silicon 13b in nmos device zone to exposing insulating buried layer 12 on described insulating buried layer 12.Concrete technology is as follows: prior to applying one deck photoresist layer (not shown) on the described top layer silicon 103, through after the photoetching process, define the active area figure in PMOS device area and nmos device zone respectively; Be mask with this photoresist layer again, to the described insulating buried layer 12 of exposed portions serve, on described insulating buried layer 12, form the active area top layer silicon 13a of PMOS device area and the active area top layer silicon 13b in nmos device zone along the described top layer silicon 13 of active area pattern etching.
Then, as shown in figure 11, on the active area top layer silicon 13a of described PMOS device area, form insulating oxide 14a respectively, on the top layer silicon 13b in described nmos device zone, form insulating oxide 14b., the material of wherein said insulating oxide 14a, 14b is a silica.Alternatively, the method that forms described silicon oxide layer is that rapid thermal oxidation is handled.Wherein, described rapid thermal oxidation temperature ranges is 400-1300 degree centigrade.
Then, as shown in figure 12, on the insulating oxide 14b in the insulating oxide 14a of described PMOS device area, described nmos device zone and insulating buried layer 12, form silicon nitride layer 15.Alternatively, in the present embodiment, the method that forms described silicon nitride layer is chemical vapour deposition technique (CVD), perhaps also can be low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD) etc., does not repeat them here.
Then, as Figure 13 and shown in Figure 14, the silicon nitride layer of the described PMOS device area of etching is to exposing insulating oxide and insulating buried layer.Alternatively, the method for the silicon nitride layer of the described PMOS device area of etching is a wet etching.Concrete technology is as follows: prior to applying a photoresist layer 16 on the silicon nitride layer 15b in described nmos device zone and the insulating buried layer 12, then semiconductor structure is as shown in figure 13 soaked in reaction solution, the silicon nitride layer 15a of the described PMOS device area of erosion removal is to exposing oxide layer 14a and insulating buried layer 12.Alternatively, wherein said reaction solution is hydrofluoric acid (HF).
Next, as shown in figure 15, carry out thermal oxidation, in described PMOS device area, form the active area top layer silicon 13a that the edge is bent upwards.Alternatively, the time of wherein said thermal oxidation is longer, and its concrete time range was at 5 seconds-4 hours; The temperature range of described thermal oxidation is at 700-1050 degree centigrade.
Because in described PMOS device area; described insulating oxide 14a does not have the silicon nitride layer protection outward; therefore when carrying out thermal oxidation; oxygen molecule is easy to diffuse to active area top layer silicon 13a by described insulating oxide 14a, makes described oxygen molecule fully react the back with the silicon of close insulating oxide 14a among the active area top layer silicon 13a and generates silica.Further, owing in described active area top layer silicon 13a, fed oxygen molecule, make the volume of described active area top layer silicon 13a increase, and active area top layer silicon 13a and oxygen molecule reaction the closer to silicon oxide layer 14a are abundant more, again because oxygen molecule can not react with the insulating oxide 14a outside the described top layer silicon 13a, like this when the volume of described active area top layer silicon 13a increases, the volume of described insulating oxide 14a can not increase, the therefore final active area top layer silicon 13a that the formation edge is bent upwards in described PMOS device area.
In conjunction with Figure 15 and shown in Figure 16, the silicon nitride layer 15b in the described nmos device of etching zone forms smooth active area top layer silicon 13b to exposing silicon oxide layer 14b and insulating buried layer 12 in described nmos device zone.Alternatively, the method for the silicon nitride layer 15b in the described nmos device of etching zone is a wet etching, and its concrete technology can not repeat them here with reference to the description of the silicon nitride layer 15a of above-mentioned etching PMOS device area.
Because in carrying out the thermal oxidation process; silicon oxide layer 14b in the described nmos device zone has the protection of silicon nitride layer 15b outward; as well known to those skilled in the art; silicon nitride is a kind of material of very hard and compact; also be a kind of refractory material simultaneously; oxygen molecule reacts with silicon with regard to very difficult diffusing among its interior oxidation silicon layer 14b and the active area top layer silicon 13b by described silicon nitride layer 15b like this, and that therefore form in described nmos device zone is smooth active area top layer silicon 13b.
In actual process, those skilled in the art can also isolate above-mentioned two device areas by form shallow-trench isolation (STI) district (not shown) between described PMOS device area and described nmos device zone.Wherein, described shallow grooved-isolation technique is a prior art, does not repeat them here.
The described active area top layer silicon 13a that forms by above-mentioned technology is as the substrate of PMOS device area, and described active area top layer silicon 13b is as the substrate in nmos device zone.Further, before follow-up making PMOS device and nmos device, can remove the silicon oxide layer 14a of described top layer silicon 13a top and sidewall and the silicon oxide layer 14b of described top layer silicon 14a top and sidewall by dry etching, wherein said dry etching is a prior art, does not repeat them here.
Then, as shown in figure 17, on the active area top layer silicon 13a of described PMOS device area, form gate dielectric layer 15a and polysilicon gate 16a successively; In the active area top layer silicon 13a of polysilicon gate 16a both sides, be formed with shallow doped region 14a.Similar ground forms gate dielectric layer 15b and polysilicon gate 16b successively on the active area top layer silicon 13b in described nmos device zone; In the active area top layer silicon 13b of polysilicon gate 16b both sides, be formed with shallow doped region 14b.The description of above-mentioned specific embodiment in can reference example two do not repeat them here.
As shown in figure 18, in the described PMOS device area, form side wall 17a on the active area top layer silicon 13a of polysilicon gate 16a both sides, alternatively, the material of wherein said side wall 17a is the combination of silica, silicon nitride or silica and silicon nitride.Further, with side wall 17a and polysilicon gate 16a is mask, in the top layer silicon 13a of both sides, inject ion, form source electrode 181a and drain electrode 182a, the doping depth of described source electrode 181a and drain electrode 182a is darker than shallow doped region 14a, has finally formed the PMOS transistor on described active area top layer silicon 13a.
Similar ground in the described nmos device zone, forms side wall 17b on the active area top layer silicon 13b of polysilicon gate 16b both sides, alternatively, the material of wherein said side wall 17b is the combination of silica, silicon nitride or silica and silicon nitride.Further, with side wall 17b and polysilicon gate 16b is mask, in the top layer silicon 13b of both sides, inject ion, form source electrode 181b and drain electrode 182b, the doping depth of described source electrode 181b and drain electrode 182b is darker than shallow doped region 14b, has finally formed nmos pass transistor on described active area top layer silicon 13b.
Forming the cmos device structure based on the foregoing description comprises: silicon-on-insulator substrate, described silicon-on-insulator substrate comprise the active area top layer silicon 13a of silicon base 11, insulating buried layer 12, PMOS device area and the active area top layer silicon 13b in nmos device zone successively.Wherein, the edge of described active area top layer silicon 13a is bent upwards, in order to strengthen the compression stress of top layer silicon inside; Described active area top layer silicon 13b does not have bending.
In the PMOS device area, be formed with gate dielectric layer 15a on the described active area top layer silicon 13a; Polysilicon gate 16a is positioned on the gate dielectric layer 15; Shallow doped region 14a is positioned at the active area top layer silicon 13a of polysilicon gate 16a both sides; Side wall 17a is positioned on the active area top layer silicon 13a of polysilicon gate 16a both sides; Source electrode 181a and drain electrode 182a are positioned at the active area top layer silicon 13a of polysilicon gate 16a and side wall 17a both sides, and describedly have the shallow doped region 14a of depth ratio of source electrode 181a and drain electrode 182a dark.
In the nmos device zone, be formed with gate dielectric layer 15b on the described active area top layer silicon 13b; Polysilicon gate 16b is positioned on the gate dielectric layer 15a; Shallow doped region 14b is positioned at the active area top layer silicon 13b of polysilicon gate 16b both sides; Side wall 17b is positioned on the active area top layer silicon 13b of polysilicon gate 16b both sides; Source electrode 181b and drain electrode 182b are positioned at the active area top layer silicon 13b of polysilicon gate 16b and side wall 17b both sides, and the shallow doped region 14b of depth ratio of described source electrode 181b and drain electrode 182b is dark.
Embodiments of the invention are mainly by carrying out thermal oxidation to the active area top layer silicon in the PMOS device area on silicon-on-insulator (SOI) substrate, part silicon in oxygen molecule and the active area top layer silicon is fully reacted, the volume of described active area top layer silicon is increased, thereby form the active area top layer silicon that is bent upwards, strengthened the compression stress of described active area top layer silicon, with described active area top layer silicon is the PMOS transistor that substrate is made, can improve the mobility of charge carrier (hole) in the substrate channel region, thereby improve the transistorized performance of PMOS.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (14)
1. the formation method of a semiconductor structure is characterized in that, comprises the steps:
Silicon-on-insulator substrate is provided, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively;
The described top layer silicon of etching is formed with the source region to exposing insulating buried layer;
Insulating oxide is formed on top layer silicon sidewall and top at active area;
Carry out thermal oxidation, the top layer silicon edge is bent upwards.
2. method according to claim 1 is characterized in that, the time range of described thermal oxidation 5 seconds-4 hours, temperature range at 700-1050 degree centigrade.
3. method according to claim 2 is characterized in that, described thermal oxidation technology is carried out in the stove heat pipe.
4. method according to claim 1 is characterized in that the method for the described top layer silicon of etching is a dry etching.
5. method according to claim 1 is characterized in that, the material of described insulating buried layer is a silica.
6. method according to claim 1 is characterized in that, the material of described insulating oxide is a silica.
7. method according to claim 5 is characterized in that, the method that forms insulating oxide is that rapid thermal oxidation is handled.
8. a semiconductor structure comprises silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively, it is characterized in that, described top layer silicon edge is bent upwards.
9. semiconductor structure according to claim 8 is characterized in that the material of described insulating buried layer is a silica.
10. the transistorized formation method of PMOS is characterized in that, comprises the steps:
Silicon-on-insulator substrate is provided, and described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively;
The described top layer silicon of etching is formed with the source region to exposing insulating buried layer;
Insulating oxide is formed on top layer silicon sidewall and top at active area;
Carry out thermal oxidation, the top layer silicon edge is bent upwards;
On described top layer silicon, form gate dielectric layer and polysilicon gate successively;
On the top layer silicon of described polysilicon gate both sides, form side wall;
Formation source/drain electrode in the top layer silicon of described polysilicon gate and side wall both sides.
11. method according to claim 10 is characterized in that, the time range of described thermal oxidation 5 seconds-4 hours, temperature range at 700-1050 degree centigrade.
12. method according to claim 11 is characterized in that, described thermal oxidation technology is carried out in the stove heat pipe.
13. method according to claim 10 is characterized in that, the method for the described top layer silicon of etching is a dry etching.
14. a PMOS transistor arrangement comprises silicon-on-insulator substrate, described silicon-on-insulator substrate comprises silicon base, insulating buried layer and top layer silicon successively; On described top layer silicon, be formed with gate dielectric layer and polysilicon gate successively; Be formed with side wall in described polysilicon gate both sides; In the top layer silicon of described polysilicon gate and side wall both sides, form active/drain electrode, it is characterized in that described top layer silicon edge is bent upwards.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1507071A (en) * | 2002-12-12 | 2004-06-23 | �Ҵ���˾ | Field effect transistor with stressed channel and producing method thereof |
| US20040132267A1 (en) * | 2003-01-02 | 2004-07-08 | International Business Machines Corporation | Patterned strained silicon for high performance circuits |
| US20060138557A1 (en) * | 2002-12-02 | 2006-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel CMOS device |
| US20080116517A1 (en) * | 2006-11-20 | 2008-05-22 | Anderson Brent A | Dual stress device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060138557A1 (en) * | 2002-12-02 | 2006-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel CMOS device |
| CN1507071A (en) * | 2002-12-12 | 2004-06-23 | �Ҵ���˾ | Field effect transistor with stressed channel and producing method thereof |
| US20040132267A1 (en) * | 2003-01-02 | 2004-07-08 | International Business Machines Corporation | Patterned strained silicon for high performance circuits |
| US20080116517A1 (en) * | 2006-11-20 | 2008-05-22 | Anderson Brent A | Dual stress device and method |
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