CN102176128A

CN102176128A - Two-stage interface combined singlechip development board

Info

Publication number: CN102176128A
Application number: CN 201110033888
Authority: CN
Inventors: 王丁
Original assignee: Heilongjiang University
Current assignee: Heilongjiang University
Priority date: 2011-01-31
Filing date: 2011-01-31
Publication date: 2011-09-07
Anticipated expiration: 2031-01-31
Also published as: CN102176128B

Abstract

The invention discloses a two-stage interface combined singlechip development board, which relates to the combined singlechip development board and aims to solve the problems that the conventional singlechip development board has a single function and that an external functional interface cannot flexibly satisfy using needs. The power supply end of a stabilized power supply module is connected with the powered end of a core control module; the RS232 data output and input end of an RS232 interface module is connected with the RS232 data input and output end of the core control module; the sound storage data output and input end of a sound storage module is connected with the sound storage data input and output end of the core control module; the sound output data input end of a sound amplification output module is connected with the sound output data output end of the core control module; and the digital potential data output and input end of a digital potentiometer module is connected with the digital potential data input and output end of the core control module. The two-stage interface combined singlechip development board has the advantages of multifunction and the external functional interface capable of flexibly satisfying various using needs.

Description

The box-like microcomputer development plate of two-stage interface group

Technical field

The present invention relates to a kind of combined type microcomputer development plate.

Background technology

Employed exploitation version mainly contains two kinds in single-chip microcomputer is used, and a kind of is the single-chip minimum system plate, promptly all draws at the following mcu resource of the condition that is equipped with necessary power supply and emulator interface.Second kind is to be equipped with necessary bus interface to single-chip microcomputer, mainly is System Management Bus SMBUS (System Management Bus), Serial Peripheral Interface SPI ((serial peripheral interface), general-purpose serial bus USB (Universal Serial BUS) and serial data interface standard RS-232; Existing microcomputer development plate exists function singleness, and External Functionality Interface can not the flexible adaptation user demand and lacked sound and problem that character is handled.

Summary of the invention

The present invention is in order to solve the function singleness that existing microcomputer development plate exists, and External Functionality Interface can not be suitable for user demand flexibly and lack sound and the problem of character processing, and the box-like microcomputer development plate of two-stage interface group that proposes.

The box-like microcomputer development plate of two-stage interface group, it is made up of basic function interface module and expanded function interface module; Described basic function interface module is made up of power module of voltage regulation and kernel control module; The feeder ear of described power module of voltage regulation links to each other with the receiving end of kernel control module; Described expansion interface assembly amplifies output module, digital regulation resistance module, clock module, memory module, character cell module, usb data interface module, sound load module and basic functional components connection terminal module by RS232 interface module, sound storage module, sound and forms; The RS232 data I/O of described RS232 interface module links to each other with the RS232 data input/output terminal of kernel control module, the sound store data I/O of sound storage module links to each other with the sound store data input/output terminal of kernel control module, the voice output data input pin that sound amplifies output module links to each other with the voice output data output end of kernel control module, and the digital potential data I/O of digital regulation resistance module links to each other with the digital potential data input/output terminal of kernel control module; The clock data I/O of clock module links to each other with the clock data input/output terminal of kernel control module; The storage data I/O of memory module links to each other with the storage data input/output terminal of kernel control module; The character data I/O of character cell module links to each other with the character data input/output terminal of kernel control module; The usb data I/O of usb data interface module links to each other with the usb data input/output terminal of kernel control module; The sound input data output end of sound load module links to each other with the sound input data input pin of kernel control module; The wiring contact data signal input output end of basic functional components connection terminal module links to each other with the wiring contact data signal I/O of kernel control module; It is the single-chip microcomputer of C8051F020 that described kernel control module adopts model.

It is many that the present invention has function, External Functionality Interface can be applicable to the advantage of various user demands flexibly, directly use the basic function interface module, other parts are welding component not, then this development board has only the basic development board function of single-chip microcomputer, can constitute Full Featured Single Chip Microcomputer (SCM) system development board as using basic function interface module and expanded function interface module; As the one or more unit that use basic function interface module and expanded function interface module constitute the microcomputer development plate of specific function; And draw outward by the basic functional components connection terminal module 12 function pin that can realize kernel control module 2 that links to each other with the function pin of kernel control module 2, form the two-stage circuit structure; Not only make the user when using kernel control module 2 basic functions, make things convenient for plug-in mounting and dismounting, can also realize kernel control module 2 basic function circuit and expanded function interface module while or the two-stage circuit structure microcomputer development plate that uses separately.The present invention can be widely used in various one-chip computer developing systems.

Description of drawings

Fig. 1 is a modular structure synoptic diagram of the present invention; Fig. 2 is the circuit theory diagrams of kernel control module 2; Fig. 3 is the circuit theory diagrams of the 5V power supply unit of voltage regulation in the power module of voltage regulation 1; Fig. 4 is the circuit theory diagrams of the 3.3V power supply unit of voltage regulation in the power module of voltage regulation 1; Fig. 5 is the circuit theory diagrams of RS232 interface module 3; Fig. 6 is the circuit theory diagrams of sound storage module 4; Fig. 7 amplifies the circuit theory diagrams of output module 5 for sound; Fig. 8 is the circuit theory diagrams of digital regulation resistance module 6; Fig. 9 is the circuit theory diagrams of clock module 7; Figure 10 is the circuit theory diagrams of memory module 8; Figure 11 is the circuit theory diagrams of character cell module 9; Figure 12 is the circuit theory diagrams of usb data interface module 10; Figure 13 is the circuit theory diagrams of sound load module 11.

Embodiment

Embodiment one: in conjunction with Fig. 1 present embodiment is described, it is made up of basic function interface module and expanded function interface module; Described basic function interface module is made up of power module of voltage regulation 1 and kernel control module 2; The feeder ear of described power module of voltage regulation 1 links to each other with the receiving end of kernel control module 2; Described expansion interface assembly amplifies output module 5, digital regulation resistance module 6, clock module 7, memory module 8, character cell module 9, usb data interface module 10, sound load module 11 and basic functional components connection terminal module 12 by RS232 interface module 3, sound storage module 4, sound and forms; The RS232 data I/O of described RS232 interface module 3 links to each other with the RS232 data input/output terminal of kernel control module 2, the sound store data I/O of sound storage module 4 links to each other with the sound store data input/output terminal of kernel control module 2, the voice output data input pin that sound amplifies output module 5 links to each other with the voice output data output end of kernel control module 2, and the digital potential data I/O of digital regulation resistance module 6 links to each other with the digital potential data input/output terminal of kernel control module 2; The clock data I/O of clock module 7 links to each other with the clock data input/output terminal of kernel control module 2; The storage data I/O of memory module 8 links to each other with the storage data input/output terminal of kernel control module 2; The character data I/O of character cell module 9 links to each other with the character data input/output terminal of kernel control module 2; The usb data I/O of usb data interface module 10 links to each other with the usb data input/output terminal of kernel control module 2; The sound input data output end of sound load module 11 links to each other with the sound input data input pin of kernel control module 2; The wiring contact data signal input output end of basic functional components connection terminal module 12 links to each other with the wiring contact data signal I/O of kernel control module 2; It is the single-chip microcomputer of C8051F020 that described kernel control module 2 adopts model.

Embodiment two: in conjunction with Fig. 3 and Fig. 4 present embodiment is described, present embodiment and embodiment one difference are that described power module of voltage regulation 1 is made up of 5V power supply unit of voltage regulation and 3.3V power supply unit of voltage regulation; Described 5V power supply unit of voltage regulation is made up of first resistance R, 1 to the 5th resistance R 5, the first diode D1 to the, four diode D4, first capacitor C, 1 to the 3rd capacitor C 3, the first chip U1, first K switch 1 and the first plug connector J1; The anode of the first diode D1 links to each other with power supply ground GND, and the negative electrode of the first diode D1 links to each other with an end of first K switch 1, an end of first resistance R 1, an end of first capacitor C 1, the three-prong IN of the first chip U1 and the 4th crucial IN of the first chip U1 simultaneously; The other end of described first K switch 1 links to each other with the first grafting pin of the first plug connector J1; The other end of described first resistance R 1 links to each other with the anode of the second diode D2; The negative electrode of the described second diode D2 links to each other with power supply ground GND with the negative electrode of the 3rd diode D3 simultaneously; The anode of described the 3rd diode D3 links to each other with an end of the 3rd resistance R 3, and the other end of the 3rd resistance R 3 links to each other with+5V power supply with the negative electrode of an end of the 3rd capacitor C 3, the 4th diode D4 simultaneously; The anode of described the 4th diode D4 links to each other with power supply ground GND with the other end of the 3rd capacitor C 3 simultaneously; The pin GND of the first chip U1 links to each other with power supply ground GND with the pin EN of the first chip U1 simultaneously; The other end of described first capacitor C 1 links to each other with power supply ground GND with the second grafting pin of the first plug connector J1, an end of second resistance R 2 simultaneously; The other end of described second resistance R 2 links to each other with an end of second capacitor C 2; The other end of second capacitor C 2 links to each other with+5V power supply with an end of the pin SENSE of the 6th pin OUT, the first chip U1 of the 5th pin OUT, the first chip U1 of the first chip U1, the 4th resistance R 4 simultaneously; The other end of the 4th resistance R 4 links to each other with an end of the 5th resistance R 5, and the other end of the 5th resistance R 5 links to each other with the pin REST of the first chip U1; Described 3.3V power supply unit of voltage regulation is made up of the 6th resistance R 6 to the 9th resistance R 9, the 5th diode D5 to the six diode D6, the 4th capacitor C 4, the 5th capacitor C 5, the second chip U2, second switch K2, the 3rd K switch 3, the second plug connector J2 and the 3rd plug connector J3; Moving contact of described second switch K2 links to each other with+5V power supply; Another moving contact of second switch K2 links to each other with+5V power supply with the first grafting pin of the 3rd plug connector J3 simultaneously; The stationary contact of second switch K2 links to each other with+5V power supply with the 4th pin IN of the three-prong IN of an end of the 4th capacitor C 4, the second chip U2 and the second chip U2 simultaneously; The other end of the 4th capacitor C 4 links to each other with power supply ground GND with the 5th grafting pin of the 3rd plug connector, an end of the 6th resistance R 6 simultaneously; The other end of the 6th resistance R 6 links to each other with an end of the 5th capacitor C 5; The other end of the 5th capacitor C 5 links to each other with the 6th pin OUT of the 5th pin OUT, the second chip U2 of an end of an end of the 8th resistance R 8, the 3rd K switch 3, the second chip U2 and the pin SENSE of the second chip U2 simultaneously; The other end of the 8th resistance R 8 links to each other with an end of the 9th resistance R 9; The other end of the 9th resistance R 9 links to each other with the pin REST of the second chip U2; The other end of the 3rd K switch 3 links to each other with+3.3V power supply with the negative electrode of an end of the 7th resistance R 7, the 5th diode D5 simultaneously; The anode of the 5th diode D5 links to each other with power supply ground with the second grafting pin of the second plug connector J2 simultaneously; The first grafting pin of the second plug connector J2 links to each other with+5V power supply; The other end of the 7th resistance R 7 links to each other with the anode of the 6th diode D6; The negative electrode while of the 6th diode D6 links to each other with power supply ground GND with the pin EN of pin GND, the second chip U2 of the second chip U2; It is the TPS7350 chip that the described first chip U1 adopts model; It is the TPS7333 chip that the second chip U2 adopts model.Other composition is identical with embodiment one with connected mode.

Embodiment three: in conjunction with Fig. 2 present embodiment is described, present embodiment and embodiment two differences are that described kernel control module 2 is made up of the 7th diode D7 to the 14 diode D14, the tenth resistance R the 10 to the 20 resistance R the 20, the 38 resistance R 38, the 4th plug connector J4 to the seven plug connector J7, the 6th capacitor C 6 to the tenth capacitor C 10, the first crystal oscillator JZ1, the 3rd chip U3, reset button RST and ground wire contact resistance R 0; Described basic functional components connection terminal module 12 is made up of the tenth plug connector J10 to the 13 plug connector J13;

The anode of the 11 diode D11 links to each other with the anode of the 12 diode D12, the anode of the 13 diode D13, the anode of the 14 diode D14, the end of reset button RST, an end of the 6th capacitor C 6 and an end of the 7th capacitor C 7 simultaneously;

The other end of reset button RST links to each other with the other end of the 6th capacitor C 6, an end of the 12 resistance R 12 and an end of the 11 resistance R 11 simultaneously; The other end of the 12 resistance R 12 links to each other with+3.3V power supply;

The other end of the 7th capacitor C 7 links to each other with the other end of the 11 resistance R 11 and the pin RST of the 3rd chip U3 simultaneously;

The negative electrode of the 11 diode D11 links to each other with the anode of the 7th diode D7, an end of the tenth resistance R 10, the pin TCK of the 3rd chip U3 and the 4th grafting pin of the 4th plug connector J4 simultaneously;

The negative electrode of the 7th diode D7 links to each other with+3.3V power supply with the negative electrode of the negative electrode of the negative electrode of the 8th diode D8, the 9th diode D9, the tenth diode D10 simultaneously;

The anode of the 8th diode D8 links to each other with the negative electrode of the 12 diode D12 and the pin TMS of the 3rd chip U3 simultaneously;

The anode of the 9th diode D9 links to each other with the negative electrode of the 13 diode D13 and the pin TDO of the 3rd chip U3 simultaneously;

The anode of the tenth diode D10 links to each other with the negative electrode of the 14 diode D14 and the pin TDI of the 3rd chip U3 simultaneously;

The second grafting pin of the 4th plug connector J4 links to each other with power supply ground GND with the 3rd grafting pin of the 4th plug connector J4, the 9th grafting pin of the 4th plug connector J4 simultaneously;

The first grafting pin of the 4th plug connector J4 links to each other with an end of the 38 resistance R 38; The other end of the 38 resistance R 38 links to each other with+3.3V power supply;

One end of the 8th capacitor C 8 links to each other with power supply ground with an end of the 9th capacitor C 9 simultaneously, and the other end of the 9th capacitor C 9 links to each other with the other end of the 8th capacitor C 8 and the pin VREF of the 3rd chip U3 simultaneously;

The tenth pin AGND of the 3rd chip U3 links to each other with power supply ground with the tenth three-prong AGND of the 3rd chip U3 simultaneously; The 11 pin AV+ of the 3rd chip U3 links to each other with the 14 pin AV+ of the 3rd chip U3, an end of the 14 resistance R 14 and the first grafting pin of the 6th plug connector J6 simultaneously; The other end of the 14 resistance R 14 links to each other with+3.3V power supply;

The 6th pin CP-to the nine pin CP0+ of the 3rd chip U3 link to each other with the first grafting pin to the, the four grafting pins of the 5th plug connector J5 respectively;

The second grafting pin of the 6th plug connector J6 links to each other with the 3rd grafting pin of the 6th plug connector J6, the 5th grafting pin of the 6th plug connector J6 and the 7th grafting pin of the 6th plug connector J6 simultaneously; The 4th grafting pin of the 6th plug connector J6 links to each other with the pin VREFD of the 3rd chip U3; The 6th grafting pin of the 6th plug connector J6 links to each other with the pin VREF0 of the 3rd chip U3; The 8th grafting pin of the 6th plug connector J6 links to each other with the pin VREF1 of the 3rd chip U3;

The 18 pin AIN0.0 to the 25 pin AIN0.7 of the 3rd chip U3 link to each other with the first grafting pin to the, the eight grafting pins of the 7th plug connector J7 respectively;

The 4th wiring pin of the first crystal oscillator JZ1 links to each other with+3.3V power supply; The 3rd wiring pin of the first crystal oscillator JZ1 links to each other with an end of the 13 resistance R 13; The other end of the 13 resistance R 13 links to each other with the pin XTAL1 of the 3rd chip U3; The second wiring pin of the first crystal oscillator JZ1 links to each other with power supply ground GND with an end of the tenth capacitor C 10 simultaneously; The other end of the tenth capacitor C 10 links to each other with+3.3V power supply with the pin MONEN of the 3rd chip U3 simultaneously;

The 29 pin AIN1.7/A15/P1.7 to the 36 pin AIN1.0/A8/P1.0 of the 3rd chip U3 link to each other with the 16 grafting pin to the nine grafting pins of the 11 plug connector J11 respectively; The 37 pin VDD of the 3rd chip U3 links to each other with+3.3V power supply; The 38 pin GND of the 3rd chip U3 links to each other with power supply ground GND; The 39 pin A15m/A7/P2.7 to the 46 pin A8m/A0/P2.0 of the 3rd chip U3 link to each other with the 8th grafting pin to the first grafting pin of the 11 plug connector J11 respectively; The 47 pin AD7/D7/P3.7 to the 50 pin AD4/D4/P3.4 of the 3rd chip U3 link to each other with the 32 grafting pin to the 29 grafting pins of the tenth plug connector J10 respectively;

The 51 pin AD3/D3/P3.3 to the 54 pin AD0/D0/P3.0 of the 3rd chip U3 link to each other with the 25 grafting pin to the 28 grafting pins of the tenth plug connector J10 respectively;

The 55 pin WR/P0.7 of the 3rd chip U3 links to each other with an end of the 16 resistance R 16 and the 24 grafting pin of the tenth plug connector J10 simultaneously;

The 56 pin RD/P0.6 of the 3rd chip U3 links to each other with an end of the 15 resistance R 15 and the 23 grafting pin of the tenth plug connector J10 simultaneously;

The 57 pin ALE/P0.5 of the 3rd chip U3 links to each other with an end of the 20 resistance R 20 and the 22 grafting pin of the tenth plug connector J10 simultaneously;

The 58 pin P0.4 of the 3rd chip U3 links to each other with an end of the 19 resistance R 19 and the 21 grafting pin of the tenth plug connector J10 simultaneously;

The 59 pin P0.3 of the 3rd chip U3 links to each other with an end of the 18 resistance R 18 and the 20 grafting pin of the tenth plug connector J10 simultaneously;

The 60 pin P0.2 of the 3rd chip U3 links to each other with an end of the 17 resistance R 17 and the 19 grafting pin of the tenth plug connector J10 simultaneously;

The 61 pin P0.1 of the 3rd chip U3 links to each other with the 17 grafting pin with the 18 grafting pin of the tenth plug connector J10 respectively with the 62 pin P0.0;

The 60 three-prong GND of the 3rd chip U3 links to each other with power supply ground GND;

The 64 pin VDD of the 3rd chip U3 links to each other with+3.3V power supply;

The 65 pin AD7/D7/P7.7 to the 75 pin A13m/A5/P6.5 of the 3rd chip U3 link to each other with the 16 grafting pin to the six grafting pins of the tenth plug connector J10 respectively;

The 76 pin A12m/A4/P6.4 to the 80 pin A8m/A0/P6.0 of the 3rd chip U3 link to each other with the 5th grafting pin to the first grafting pin of the tenth plug connector J10 respectively;

The 81 pin A15/P5.7 to the 88 pin A8/P5.0 of the 3rd chip U3 link to each other with the 16 grafting pin to the nine grafting pins of the 12 plug connector J12 respectively;

The 89 pin GND of the 3rd chip U3 links to each other with power supply ground;

The 90 pin VDD of the 3rd chip U3 links to each other with+3.3V power supply;

The 91 pin WR/P4.7 to the 98 pin P4.0 of the 3rd chip U3 link to each other with the 8th grafting pin to the first grafting pin of the 12 plug connector J12 respectively;

The 99 pin DAC1 of the 3rd chip U3 links to each other with the first grafting pin with the second grafting pin of the 13 plug connector J13 respectively with the 100 pin DAC0;

One end of ground wire contact resistance R 0 is connected with power supply ground, and the other end of ground wire contact resistance R 0 links to each other with ground wire;

It is the single-chip microcomputer of C8051F020 that the 3rd chip U3 adopts model.

Other composition is identical with embodiment two with connected mode.

Embodiment four: in conjunction with Fig. 5 present embodiment is described, present embodiment and embodiment three differences are that described RS232 interface module 3 is made up of the 11 capacitor C the 11 to the 15 capacitor C 15, four-core sheet U4 and DB9 terminal block;

The two ends of the 11 capacitor C 11 link to each other with three-prong C1-with the first pin C1+ of four-core sheet U4 respectively;

The two ends of the 13 capacitor C 13 link to each other with the 5th pin C2-with the 4th pin C2+ of four-core sheet U4 respectively;

One end of the 14 capacitor C 14 links to each other with power supply ground, and the other end of ground 14 capacitor C 14 links to each other with the 6th pin V-of four-core sheet U4;

One end of the 12 capacitor C 12 links to each other with the second pin V+ of four-core sheet U4, and the 12 capacitor C 12 links to each other with+5V power supply with the 16 pin Vcc of an end of the 15 capacitor C 15, four-core sheet U4 simultaneously; The other end of the 15 capacitor C 15 links to each other with power supply ground with the 15 pin GND of four-core sheet U4 simultaneously;

The 14 pin T1out of four-core sheet U4 links to each other with the second wiring pin of DB9 terminal block; The tenth three-prong R1in of four-core sheet U4 links to each other with the 3rd wiring pin of DB9 terminal block;

The 12 pin R1out of four-core sheet U4 links to each other with the 17 grafting pin with the 18 grafting pin of the tenth plug connector J10 respectively with the 11 pin T1in; The 5th wiring pin of DB9 terminal block links to each other with power supply ground; It is the chip of MAX232 that four-core sheet U4 adopts model.

Other composition is identical with embodiment three with connected mode.

Embodiment five: in conjunction with Fig. 6 present embodiment is described, present embodiment and embodiment four differences are that described sound storage module 4 is made up of the 5th chip U5, the 16 capacitor C the 16 to the 21 capacitor C the 21, the 21 resistance R the 21, the 22 resistance R 22 and the second crystal oscillator JZ2;

The first pin VDD of described the 5th chip U5 links to each other with+3.3V power supply; The second pin VSS of the 5th chip U5 links to each other with power supply ground with an end of the 16 capacitor C 16 simultaneously; The other end of the 16 capacitor C 16 links to each other with the pin RST of the 5th chip U5; The 7th pin X1 of the 5th chip U5 links to each other with an end of the 21 resistance R 21, and the other end of the 21 resistance R 21 links to each other with the 3rd wiring pin of the second crystal oscillator JZ2; The second wiring pin of the second crystal oscillator JZ2 links to each other with power supply ground, and the 4th wiring pin of the second crystal oscillator JZ2 links to each other with+3.3V power supply with an end of the 17 capacitor C 17 simultaneously; The other end of the 17 capacitor C 17 links to each other with power supply ground GND; The 8th pin VSS of the 5th chip U5 and the 9th pin VDD link to each other with+3.3V power supply with power supply ground respectively;

The 12 pin AVDD of the 5th chip U5 links to each other with an end of the 18 capacitor C 18 and an end of the 22 resistance R 22 simultaneously; The other end of the 22 resistance R 22 links to each other with+3.3V power supply; The other end of the 18 capacitor C 18 links to each other with power supply ground with the 16 pin AVSS of the 5th chip U5 simultaneously; The 14 pin CAP2 of the 5th chip U5 links to each other with an end of the 19 capacitor C 19; The other end of the 19 capacitor C 19 links to each other with power supply ground GND; The 34 pin VSS of the 5th chip U5 links to each other with power supply ground; The 36 pin RDY of the 5th chip U5 links to each other with the 32 grafting pin of the tenth plug connector J10; The 40 pin RXD of the 5th chip U5 links to each other with the 17 grafting pin of the tenth plug connector J10; The 42 pin TXD of the 5th chip U5 links to each other with the 18 grafting pin of the tenth plug connector J10; The 44 pin VDD of the 5th chip U5 links to each other with+3.3V power supply with an end of an end of the 21 capacitor C 21, the 20 capacitor C 20 simultaneously; The other end of the 20 capacitor C 20 links to each other with power supply ground GND with the other end of the 21 capacitor C 21 simultaneously; The model of the 5th chip U5 is the chip of XF-S3011.

Other composition is identical with embodiment four with connected mode.

Embodiment six: in conjunction with Fig. 7 present embodiment is described, present embodiment and embodiment five differences are that described sound amplifies output module 5 and is made up of the 23 resistance R the 23 to the 25 resistance R the 25, the 22 capacitor C the 22 to the 25 capacitor C 25, loudspeaker SP2, the 6th chip U6, calibrating terminal and earphone socket PHONEJACK; The first wiring pin of calibrating terminal links to each other with an end of the 23 capacitor C 23, and second pin-Vin of the other end the 6th chip U6 of the 23 capacitor C 23 links to each other; The second wiring pin of calibrating terminal links to each other with power supply ground GND with an end of the 22 capacitor C 22 simultaneously, and the other end while of the 22 capacitor C 22 and the first pin VDD of the 6th chip U6 link to each other with+3.3V power supply; The three-prong HPSense of the 6th chip U6 links to each other with an end of the 23 resistance R 23 and an end of the 24 resistance R 24 simultaneously; The other end of the 23 resistance R 23 links to each other with+3.3V power supply; The other end of the 24 R24 links to each other with the second wiring pin of earphone socket PHONEJACK; The 5th pin Vo1 of the 6th chip U6 links to each other with the terminals of loudspeaker SP2; The 6th pin GND of the 6th chip U6 links to each other with power supply ground GND; The 7th pin Bypass of the 6th chip U6 links to each other with an end of the 24 capacitor C 24; The other end of the 24 capacitor C 24 links to each other with power supply ground GND; The 8th pin Vo2 of the 6th chip U6 links to each other with another terminals of loudspeaker SP2 and an end of the 25 capacitor C 25 simultaneously; The other end of the 25 capacitor C 25 links to each other with an end of the 25 resistance R 25 and the first wiring pin of earphone socket PHONEJACK simultaneously; The other end of the 25 resistance R 25 links to each other with the 3rd wiring pin of power supply ground GND and earphone socket PHONEJACK simultaneously; It is the chip of LM4875 that the 6th chip U6 adopts model.Other composition is identical with embodiment five with connected mode.

Embodiment seven: in conjunction with Fig. 8 present embodiment is described, present embodiment and embodiment six differences are that described digital regulation resistance module 6 is made up of the 26 capacitor C the 26 to the 29 capacitor C 29, the 7th chip U7, the 8th chip U8 and the 8th plug connector J8; One end of the 26 capacitor C 26 links to each other with+3.3V power supply with the second pin VDD of an end of the 27 capacitor C 27, the 7th chip U7 simultaneously; The other end of the 26 capacitor C 26 links to each other with power supply ground GND with the other end of the 27 capacitor C 27 simultaneously; The first pin W of the 7th chip U7 links to each other with the first grafting pin of the 8th plug connector J8; The three-prong GND of the 7th chip U7 links to each other with power supply ground GND; The 4th pin SCL of the 7th chip U7 links to each other with the 24 grafting pin of the tenth plug connector J10; The 5th pin SDA of the 7th chip U7 links to each other with the 23 grafting pin of the tenth plug connector J10; The 6th pin AD0 of the 7th chip U7 links to each other with power supply ground GND with the 7th pin B of the 7th chip U7 simultaneously; The 8th pin of the 7th chip U7 links to each other with+3.3V power supply;

One end of the 28 capacitor C 28 links to each other with power supply ground GND with an end of the 29 capacitor C 29 simultaneously; The other end of the 28 capacitor C 28 links to each other with+3.3V power supply with the second pin VDD of the other end of the 29 capacitor C 29, the 8th chip U8 simultaneously; The three-prong GND of the 8th chip U8 links to each other with power supply ground GND; The first pin W of the 8th chip U8 links to each other with the second grafting pin of the 8th plug connector J8; The 4th pin SCL of the 8th chip U8 links to each other with the 24 grafting pin of the tenth plug connector J10; The 5th pin SDA of the 8th chip U8 links to each other with the 23 grafting pin of the tenth plug connector J10; The 6th pin AD0 of the 8th chip U8 links to each other with+3.3V power supply with the 8th pin A of the 8th chip U8 simultaneously; The 7th pin of the 8th chip U8 links to each other with power supply ground GND; It is the chip of AD5245 that described the 7th chip U7 adopts model, and it is the chip of AD5245 that the 8th chip U8 adopts model.

Other composition is identical with embodiment six with connected mode.

Embodiment eight: in conjunction with Fig. 9 present embodiment is described, present embodiment and embodiment seven differences are that described clock module 7 is made up of the 26 resistance R the 26 to the 33 resistance R the 33, the 30 capacitor C the 30 to the 32 capacitor C 32, the 3rd crystal oscillator JZ3, the 15 diode D15 and the 9th chip U9; One end of the 26 resistance R 26 links to each other with an end of the 31 resistance R 31 and the 31 grafting pin of the tenth plug connector J10 simultaneously; The other end of the 31 resistance R 31 links to each other with the 5th pin INTRA of the 9th chip U9; The other end of the 26 resistance R 26 links to each other with+3.3V power supply with an end of an end of an end of the 27 resistance R 27, the 32 resistance R 32, the 30 capacitor C 30 simultaneously; The other end of the 27 resistance R 27 links to each other with an end of the 28 resistance R 28 and the 30 grafting pin of the tenth plug connector J10 simultaneously; The other end of the 28 resistance R 28 links to each other with the first pin INTRB of the 9th chip U9; The second pin SCL of the 9th chip U9 links to each other with an end of the 29 resistance R 29; The other end of the 29 resistance R 29 links to each other with the 24 grafting pin of the tenth plug connector J10; The three-prong SDA of the 9th chip U9 links to each other with an end of the 30 resistance R 30, and the other end of the 30 resistance R 30 links to each other with the 23 grafting pin of the tenth plug connector J10; The 4th pin GND of the 9th chip U9 links to each other with power supply ground GND; The other end of the 30 capacitor C 30 links to each other with power supply ground GND with an end of the 31 capacitor C 31 simultaneously; The other end of the 32 resistance R 32 links to each other with the anode of the 15 diode D15; The negative electrode of the 15 diode D15 links to each other with the other end of the 31 capacitor C 31 and the 8th pin VDD of the 9th chip U9 simultaneously; The 7th pin OSCIN of the 9th chip U9 links to each other with an end of the 33 resistance R 33; The other end of the 33 resistance R 33 links to each other with the 3rd wiring pin of the 3rd crystal oscillator JZ3; The second wiring pin of the 3rd crystal oscillator JZ3 links to each other with power supply ground GND, and the 4th wiring pin of the 3rd crystal oscillator JZ3 links to each other with+3.3V power supply with an end of the 32 capacitor C 32 simultaneously; The other end of the 32 capacitor C 32 links to each other with power supply ground GND; It is the chip of SD2098 that the 9th chip U9 adopts model.

Other composition is identical with embodiment seven with connected mode.

Embodiment nine: in conjunction with Figure 10 and Figure 11 present embodiment is described, present embodiment and embodiment eight differences are that described memory module 8 is made up of the 34 capacitor C 34 and the 11 chip U11; One end of described the 34 capacitor C 34 links to each other with the 4th pin CS of the 11 chip U11; The other end of the 34 capacitor C 34 links to each other with power supply ground GND with the first pin GND of the 11 chip U11 simultaneously; The 5th pin SCK of the 11 chip U11 links to each other with the 19 grafting pin of the tenth plug connector J10; The 6th pin SI of the 11 chip U11 links to each other with the 21 grafting pin of the tenth plug connector J10; The 7th pin SO of the 11 chip U11 links to each other with the 20 grafting pin of the tenth plug connector J10; The 20 three-prong RDY of the 11 chip U11 links to each other with the 28 grafting pin of the tenth plug connector J10; The 25 pin WP of the 11 chip U11 links to each other with+3.3V power supply with the 28 pin VCC of the 11 chip U11 simultaneously;

Described character library unit module 9 is made up of the 33 capacitor C the 33, the 34 resistance R 34 and the tenth chip U10; The first pin SO of the tenth chip U10 links to each other with the 20 grafting pin of the tenth plug connector J10; The second pin VSS of the tenth chip U10 links to each other with power supply ground GND with an end of the 33 capacitor C 33 simultaneously; The other end of the 33 capacitor C 33 simultaneously and the 7th pin VCC of the tenth chip U10 link to each other with+3.3V power supply; The 8th pin VSS of the tenth chip U10 links to each other with power supply ground GND with the 9th pin VSS simultaneously; The 12 pin VSS of the tenth chip U10 links to each other with power supply ground GND; The pin CLK of the tenth chip U10 links to each other with the 19 grafting pin of the tenth plug connector J10; The 14 pin HOLD of the tenth chip U10 links to each other with an end of the 34 resistance R 34; The other end of the 34 resistance R 34 links to each other with+3.3V power supply; The 19 pin CS# of the tenth chip U10/link to each other with the 29 grafting pin of the tenth plug connector J10; The 20 pin SI of the tenth chip U10 links to each other with the 21 grafting pin of the tenth plug connector J10; It is the chip of GT23L32S4W that the tenth chip U10 adopts model, and it is the chip of AT45DB081 that the 11 chip U11 adopts model.

Other composition is identical with embodiment eight with connected mode.

Embodiment ten: in conjunction with Figure 12 and Figure 13 present embodiment is described, present embodiment and embodiment nine differences are that described usb data interface module 10 is made up of the 35 resistance R the 35, the 35 capacitor C the 35 to the 37 capacitor C 37, the 9th plug connector J9 and twelve-core sheet U12; One end of the 36 capacitor C 36 links to each other with+3.3V power supply with the 6th pin VDD of an end of the 35 capacitor C 35, twelve-core sheet U12 simultaneously; The other end of the 36 capacitor C 36 links to each other with power supply ground GND with the other end of the 35 capacitor C 35, the three-prong GND of twelve-core sheet U12 simultaneously; The first pin DCD of twelve-core sheet U12 links to each other with the 4th grafting pin of the 9th plug connector J9; The 4th pin of twelve-core sheet U12 links to each other with the 3rd grafting pin of the 3rd plug connector J3; The 5th pin of twelve-core sheet U12 links to each other with the second grafting pin of the 3rd plug connector J3; The 7th pin REGIN of twelve-core sheet U12 links to each other with+5V power supply with the 8th pin VBUS of an end of an end of the 37 capacitor C 37, the 35 resistance R 35, twelve-core sheet U12 simultaneously; The other end of the 35 resistance R 35 links to each other with the 9th pin RST of twelve-core sheet U12; The other end of the 37 capacitor C 37 links to each other with power supply ground GND; The 11 pin of twelve-core sheet U12 links to each other with the 5th grafting pin of the 9th plug connector J9; The 12 pin of twelve-core sheet U12 links to each other with the 6th grafting pin of the 9th plug connector J9; The 20 three-prong CTS of twelve-core sheet U12 links to each other with the 8th grafting pin of the 9th plug connector J9; The 24 pin RTS of twelve-core sheet U12 links to each other with the 7th grafting pin of the 9th plug connector J9; The 27 pin DSR of twelve-core sheet U12 links to each other with the second grafting pin of the 9th plug connector J9; The 28 pin DTR of twelve-core sheet U12 links to each other with the first grafting pin of the 9th plug connector J9;

Described sound load module 11 is made up of the 38 capacitor C the 38 to the 40 capacitor C the 40, the 13 chip U13, the tenth four-core sheet U14, the 36 resistance R 36 and the 37 resistance R 37; One end of the 38 capacitor C 38 links to each other with power supply ground GND, and the other end of the 38 capacitor C 38 links to each other with+3.3V power supply with an end of the first pin VDD of the 13 chip U13, the 40 capacitor C 40 simultaneously; First terminals of the 36 resistance R 36 link to each other with power supply ground GND, and second terminals of the 36 resistance R 36 link to each other with+3.3V power supply; The 3rd terminals of the 36 resistance R 36 link to each other with the 4th pin DCVol/SD of the 13 chip U13; The other end of the 40 capacitor C 40 links to each other with the 4th pin POWER of the tenth four-core sheet U14 and an end of the 37 resistance R 37 simultaneously; The other end of the 37 resistance R 37 links to each other with power supply ground GND; The second pin GND of the tenth four-core sheet U14 links to each other with power supply ground GND with the three-prong GND of the tenth four-core sheet U14 simultaneously; The 4th pin OUTPUT of the tenth four-core sheet U14 links to each other with+3.3V power supply; The 6th pin GND of the 13 chip U13 links to each other with power supply ground GND; The 7th pin of the 13 chip U13 links to each other with an end of the 39 capacitor C 39, and the other end of the 39 capacitor C 39 links to each other with power supply ground GND; It is the chip of LM4875 that the 13 chip U13 adopts model; It is the microphone chip of MSM2C that the tenth four-core sheet U14 adopts model.

Other composition is identical with embodiment nine with connected mode.

Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For this person of an ordinary skill in the technical field, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to the definite scope of patent protection of claims that the present invention submits to.

Claims

1. the box-like microcomputer development plate of two-stage interface group is characterized in that it is made up of basic function interface module and expanded function interface module; Described basic function interface module is made up of power module of voltage regulation (1) and kernel control module (2); The feeder ear of described power module of voltage regulation (1) links to each other with the receiving end of kernel control module (2); Described expansion interface assembly amplifies output module (5), digital regulation resistance module (6), clock module (7), memory module (8), character cell module (9), usb data interface module (10), sound load module (11) and basic functional components connection terminal module (12) by RS232 interface module (3), sound storage module (4), sound and forms; The RS232 data I/O of described RS232 interface module (3) links to each other with the RS232 data input/output terminal of kernel control module (2), the sound store data I/O of sound storage module (4) links to each other with the sound store data input/output terminal of kernel control module (2), the voice output data input pin that sound amplifies output module (5) links to each other with the voice output data output end of kernel control module (2), and the digital potential data I/O of digital regulation resistance module (6) links to each other with the digital potential data input/output terminal of kernel control module (2); The clock data I/O of clock module (7) links to each other with the clock data input/output terminal of kernel control module (2); The storage data I/O of memory module (8) links to each other with the storage data input/output terminal of kernel control module (2); The character data I/O of character cell module (9) links to each other with the character data input/output terminal of kernel control module (2); The usb data I/O of usb data interface module (10) links to each other with the usb data input/output terminal of kernel control module (2); The sound input data output end of sound load module (11) links to each other with the sound input data input pin of kernel control module (2); The wiring contact data signal input output end of basic functional components connection terminal module (12) links to each other with the wiring contact data signal I/O of kernel control module (2); It is the single-chip microcomputer of C8051F020 that described kernel control module (2) adopts model.

2. the box-like microcomputer development plate of two-stage interface group according to claim 1 is characterized in that described power module of voltage regulation (1) is made up of 5V power supply unit of voltage regulation and 3.3V power supply unit of voltage regulation;

Described 5V power supply unit of voltage regulation is made up of first resistance (R1) to the 5th resistance (R5), first diode (D1) to the 4th diode (D4), first electric capacity (C1) to the 3rd electric capacity (C3), first chip (U1), first switch (K1) and first plug connector (J1);

The anode of first diode (D1) links to each other with power supply ground GND, and the negative electrode of first diode (D1) links to each other with an end of first switch (K1), an end of first resistance (R1), an end of first electric capacity (C1), the three-prong IN of first chip (U1) and the 4th pin IN of first chip (U1) simultaneously;

The other end of described first switch (K1) links to each other with the first grafting pin of first plug connector (J1);

The other end of described first resistance (R1) links to each other with the anode of second diode (D2);

The negative electrode of described second diode (D2) links to each other with power supply ground GND with the negative electrode of the 3rd diode (D3) simultaneously;

The anode of described the 3rd diode (D3) links to each other with an end of the 3rd resistance (R3), and the other end of the 3rd resistance (R3) links to each other with+5V power supply with the negative electrode of an end of the 3rd electric capacity (C3), the 4th diode (D4) simultaneously;

The anode of described the 4th diode (D4) links to each other with power supply ground GND with the other end of the 3rd electric capacity (C3) simultaneously;

The pin GND of first chip (U1) links to each other with power supply ground GND with the pin EN of first chip (U1) simultaneously;

The other end of described first electric capacity (C1) links to each other with power supply ground GND with the second grafting pin of first plug connector (J1), an end of second resistance (R2) simultaneously; The other end of described second resistance (R2) links to each other with an end of second electric capacity (C2);

The other end of second electric capacity (C2) links to each other with+5V power supply with an end of the pin SENSE of the 6th pin OUT of the 5th pin OUT of first chip (U1), first chip (U1), first chip (U1), the 4th resistance (R4) simultaneously;

The other end of the 4th resistance (R4) links to each other with an end of the 5th resistance (R5), and the other end of the 5th resistance (R5) links to each other with the pin REST of first chip (U1);

Described 3.3V power supply unit of voltage regulation is made up of the 6th resistance (R6) to the 9th resistance (R9), the 5th diode (D5) to the 6th diode (D6), the 4th electric capacity (C4), the 5th electric capacity (C5), second chip (U2), second switch (K2), the 3rd switch (K3), second plug connector (J2) and the 3rd plug connector (J3);

Moving contact of described second switch (K2) links to each other with+5V power supply; Another moving contact of second switch (K2) links to each other with+5V power supply with the first grafting pin of the 3rd plug connector (J3) simultaneously; The stationary contact of second switch (K2) links to each other with+5V power supply with the 4th pin IN of the three-prong IN of an end of the 4th electric capacity (C4), second chip (U2) and second chip (U2) simultaneously;

The other end of the 4th electric capacity (C4) links to each other with power supply ground GND with the 5th grafting pin of the 3rd plug connector (J3), an end of the 6th resistance (R6) simultaneously;

The other end of the 6th resistance (R6) links to each other with an end of the 5th electric capacity (C5);

The other end while of the 5th electric capacity (C5) is with an end, an end of the 3rd switch (K3) of the 8th resistance (R8), (the pin SENSE's second chip of the 5th pin OUT of U2, the 6th pin OUT of second chip (U2) and second chip (U2) links to each other;

The other end of the 8th resistance (R8) links to each other with an end of the 9th resistance (R9); The other end of the 9th resistance (R9) links to each other with the pin REST of second chip (U2);

The other end of the 3rd switch (K3) links to each other with+3.3V power supply with the negative electrode of an end of the 7th resistance (R7), the 5th diode (D5) simultaneously;

The anode of the 5th diode (D5) links to each other with power supply ground with the second grafting pin of second plug connector (J2) simultaneously;

The first grafting pin of second plug connector (J2) links to each other with+5V power supply;

The other end of the 7th resistance (R7) links to each other with the anode of the 6th diode (D6);

The negative electrode of the 6th diode (D6) links to each other with power supply ground GND with the pin GND of second chip (U2), the pin EN of second chip (U2) simultaneously;

It is the TPS7350 chip that described first chip (U1) adopts model; It is the TPS7333 chip that second chip (U2) adopts model.

3. the box-like microcomputer development plate of two-stage interface group according to claim 2, it is characterized in that described kernel control module (2) by the 7th diode (D7) to the 14 diode (D14), the tenth resistance (R10) to the 20 resistance (R20), the 38 resistance (R38), the 4th plug connector (J4) to the 7th plug connector (J7), the 6th electric capacity (C6) to the tenth electric capacity (C10), first crystal oscillator (JZ1), the 3rd chip (U3), reset button (RST) and ground wire contact resistance (R0) forms; Described basic functional components connection terminal module (12) is made up of the tenth plug connector (J10) to the 13 plug connector (J13);

The anode of the 11 diode (D11) links to each other with the anode of the 12 diode (D12), the anode of the 13 diode (D13), the anode of the 14 diode (D14), an end of reset button (RST), an end of the 6th electric capacity (C6) and an end of the 7th electric capacity (C7) simultaneously;

The other end of reset button (RST) links to each other with the other end of the 6th electric capacity (C6), an end of the 12 resistance (R12) and an end of the 11 resistance (R11) simultaneously; The other end of the 12 resistance (R12) links to each other with+3.3V power supply;

The other end of the 7th electric capacity (C7) links to each other with the other end of the 11 resistance (R11) and the pin RST of the 3rd chip (U3) simultaneously;

The negative electrode of the 11 diode (D11) links to each other with the anode of the 7th diode (D7), an end of the tenth resistance (R10), the pin TCK of the 3rd chip (U3) and the 4th grafting pin of the 4th plug connector (J4) simultaneously;

The negative electrode of the 7th diode (D7) links to each other with+3.3V power supply with the negative electrode of the negative electrode of the negative electrode of the 8th diode (D8), the 9th diode (D9), the tenth diode (D10) simultaneously;

The anode of the 8th diode (D8) links to each other with the negative electrode of the 12 diode (D12) and the pin TMS of the 3rd chip (U3) simultaneously;

The anode of the 9th diode (D9) links to each other with the negative electrode of the 13 diode (D13) and the pin TDO of the 3rd chip (U3) simultaneously;

The anode of the tenth diode (D10) links to each other with the negative electrode of the 14 diode (D14) and the pin TDI of the 3rd chip (U3) simultaneously;

The second grafting pin of the 4th plug connector (J4) links to each other with power supply ground GND with the 3rd grafting pin of the 4th plug connector (J4), the 9th grafting pin of the 4th plug connector (J4) simultaneously;

The first grafting pin of the 4th plug connector (J4) links to each other with an end of the 38 resistance (R38); The other end of the 38 resistance (R38) links to each other with+3.3V power supply;

One end of the 8th electric capacity (C8) links to each other with power supply ground with an end of the 9th electric capacity (C9) simultaneously, and the other end of the 9th electric capacity (C9) links to each other with the other end of the 8th electric capacity (C8) and the pin VREF of the 3rd chip (U3) simultaneously;

The tenth pin AGND of the 3rd chip (U3) links to each other with power supply ground with the tenth three-prong AGND of the 3rd chip (U3) simultaneously; The 11 pin AV+ of the 3rd chip (U3) links to each other with the 14 pin AV+ of the 3rd chip (U3), an end of the 14 resistance (R14) and the first grafting pin of the 6th plug connector (J6) simultaneously; The other end of the 14 resistance (R14) links to each other with+3.3V power supply;

The 6th pin CP-to the nine pin CP0+ of the 3rd chip (U3) link to each other with the first grafting pin to the, the four grafting pins of the 5th plug connector (J5) respectively;

The second grafting pin of the 6th plug connector (J6) links to each other with the 3rd grafting pin of the 6th plug connector (J6), the 5th grafting pin of the 6th plug connector (J6) and the 7th grafting pin of the 6th plug connector (J6) simultaneously; The 4th grafting pin of the 6th plug connector (J6) links to each other with the pin VREFD of the 3rd chip (U3); The 6th grafting pin of the 6th plug connector (J6) links to each other with the pin VREF0 of the 3rd chip (U3); The 8th grafting pin of the 6th plug connector (J6) links to each other with the pin VREF1 of the 3rd chip (U3);

The 18 pin AIN0.0 to the 25 pin AIN0.7 of the 3rd chip (U3) link to each other with the first grafting pin to the, the eight grafting pins of the 7th plug connector (J7) respectively;

The 4th wiring pin of first crystal oscillator (JZ1) links to each other with+3.3V power supply; The 3rd wiring pin of first crystal oscillator (JZ1) links to each other with an end of the 13 resistance (R13); The other end of the 13 resistance (R13) links to each other with the pin XTAL1 of the 3rd chip (U3); The second wiring pin of first crystal oscillator (JZ1) links to each other with power supply ground GND with an end of the tenth electric capacity (C10) simultaneously; The other end of the tenth electric capacity (C10) links to each other with+3.3V power supply with the pin MONEN of the 3rd chip (U3) simultaneously;

The 29 pin AIN1.7/A15/P1.7 to the 36 pin AIN1.0/A8/P1.0 of the 3rd chip (U3) link to each other with the 16 grafting pin to the nine grafting pins of the 11 plug connector (J11) respectively; The 37 pin VDD of the 3rd chip (U3) links to each other with+3.3V power supply; The 38 pin GND of the 3rd chip (U3) links to each other with power supply ground GND; The 39 pin A15m/A7/P2.7 to the 46 pin A8m/A0/P2.0 of the 3rd chip (U3) link to each other with the 8th grafting pin to the first grafting pin of the 11 plug connector (J11) respectively; The 47 pin AD7/D7/P3.7 to the 50 pin AD4/D4/P3.4 of the 3rd chip (U3) link to each other with the 32 grafting pin to the 29 grafting pins of the tenth plug connector (J10) respectively;

The 51 pin AD3/D3/P3.3 to the 54 pin AD0/D0/P3.0 of the 3rd chip (U3) link to each other with the 25 grafting pin to the 28 grafting pins of the tenth plug connector (J10) respectively;

The 55 pin WR/P0.7 of the 3rd chip (U3) links to each other with an end of the 16 resistance (R16) and the 24 grafting pin of the tenth plug connector (J10) simultaneously;

The 56 pin RD/P0.6 of the 3rd chip (U3) links to each other with an end of the 15 resistance (R15) and the 23 grafting pin of the tenth plug connector (J10) simultaneously;

The 57 pin ALE/P0.5 of the 3rd chip (U3) links to each other with an end of the 20 resistance (R20) and the 22 grafting pin of the tenth plug connector (J10) simultaneously;

The 58 pin P0.4 of the 3rd chip (U3) links to each other with an end of the 19 resistance (R19) and the 21 grafting pin of the tenth plug connector (J10) simultaneously;

The 59 pin P0.3 of the 3rd chip (U3) links to each other with an end of the 18 resistance (R18) and the 20 grafting pin of the tenth plug connector (J10) simultaneously;

The 60 pin P0.2 of the 3rd chip (U3) links to each other with an end of the 17 resistance (R17) and the 19 grafting pin of the tenth plug connector (J10) simultaneously;

The other end of the other end to the 20 resistance (R20) of the 15 resistance (R15) links to each other with+3.3V power supply simultaneously;

The 61 pin P0.1 of the 3rd chip (U3) links to each other with the 17 grafting pin with the 18 grafting pin of the tenth plug connector (J10) respectively with the 62 pin P0.0;

The 60 three-prong GND of the 3rd chip (U3) links to each other with power supply ground GND;

The 64 pin VDD of the 3rd chip (U3) links to each other with+3.3V power supply;

The 65 pin AD7/D7/P7.7 to the 75 pin A13m/A5/P6.5 of the 3rd chip (U3) link to each other with the 16 grafting pin to the six grafting pins of the tenth plug connector (J10) respectively;

The 76 pin A12m/A4/P6.4 to the 80 pin A8m/A0/P6.0 of the 3rd chip (U3) link to each other with the 5th grafting pin to the first grafting pin of the tenth plug connector (J10) respectively;

The 81 pin A15/P5.7 to the 88 pin A8/P5.0 of the 3rd chip (U3) link to each other with the 16 grafting pin to the nine grafting pins of the 12 plug connector (J12) respectively;

The 89 pin GND of the 3rd chip (U3) links to each other with power supply ground;

The 90 pin VDD of the 3rd chip (U3) links to each other with+3.3V power supply;

The 91 pin WR/P4.7 to the 98 pin P4.0 of the 3rd chip (U3) link to each other with the 8th grafting pin to the first grafting pin of the 12 plug connector (J12) respectively;

The 99 pin DAC1 of the 3rd chip (U3) links to each other with the first grafting pin with the second grafting pin of the 13 plug connector (J13) respectively with the 100 pin DAC0;

One end of ground wire contact resistance (R0) is connected with power supply ground, and the other end of ground wire contact resistance (R0) links to each other with ground wire;

It is the single-chip microcomputer of C8051F020 that the 3rd chip (U3) adopts model.

4. the box-like microcomputer development plate of two-stage interface group according to claim 3 is characterized in that described RS232 interface module (3) is made up of the 11 electric capacity (C11) to the 15 electric capacity (C15), four-core sheet (U4) and DB9 terminal block;

The two ends of the 11 electric capacity (C11) link to each other with three-prong C1-with the first pin C1+ of four-core sheet (U4) respectively;

The two ends of the 13 electric capacity (C13) link to each other with the 5th pin C2-with the 4th pin C2+ of four-core sheet (U4) respectively;

One end of the 14 electric capacity (C14) links to each other with power supply ground, and the other end of the 14 electric capacity (C14) links to each other with the 6th pin V-of four-core sheet (U4);

One end of the 12 electric capacity (C12) links to each other with the second pin V+ of four-core sheet (U4), and the 12 electric capacity (C12) links to each other with+5V power supply with the 16 pin Vcc of an end of the 15 electric capacity (C15), four-core sheet (U4) simultaneously; The other end of the 15 electric capacity (C15) links to each other with power supply ground with the 15 pin GND of four-core sheet (U4) simultaneously;

The 14 pin T1out of four-core sheet (U4) links to each other with the second wiring pin of DB9 terminal block; The tenth three-prong R1in of four-core sheet (U4) links to each other with the 3rd wiring pin of DB9 terminal block;

The 12 pin R1out of four-core sheet (U4) links to each other with the 17 grafting pin with the 18 grafting pin of the tenth plug connector (J10) respectively with the 11 pin T1in; The 5th wiring pin of DB9 terminal block links to each other with power supply ground; It is the chip of MAX232 that four-core sheet (U4) adopts model.

5. the box-like microcomputer development plate of two-stage interface group according to claim 4 is characterized in that described sound storage module (4) is made up of the 5th chip (U5), the 16 electric capacity (C16) to the 21 electric capacity (C21), the 21 resistance (R21), the 22 resistance (R22) and second crystal oscillator (JZ2);

The first pin VDD of described the 5th chip (U5) links to each other with+3.3V power supply; The second pin VSS of the 5th chip (U5) links to each other with power supply ground with an end of the 16 electric capacity (C16) simultaneously; The other end of the 16 electric capacity (C16) links to each other with the pin RST of the 5th chip (U5); The 7th pin X1 of the 5th chip (U5) links to each other with an end of the 21 resistance (R21), and the other end of the 21 resistance (R21) links to each other with the 3rd wiring pin of second crystal oscillator (JZ2); The second wiring pin of second crystal oscillator (JZ2) links to each other with power supply ground, and the 4th wiring pin of second crystal oscillator (JZ2) links to each other with+3.3V power supply with an end of the 17 electric capacity (C17) simultaneously; The other end of the 17 electric capacity (C17) links to each other with power supply ground GND; The 8th pin VSS of the 5th chip (U5) and the 9th pin VDD link to each other with+3.3V power supply with power supply ground respectively;

The 12 pin AVDD of the 5th chip (U5) links to each other with an end of the 18 electric capacity (C18) and an end of the 22 resistance (R22) simultaneously; The other end of the 22 resistance (R22) links to each other with+3.3V power supply; The other end of the 18 electric capacity (C18) links to each other with power supply ground with the 16 pin AVSS of the 5th chip (U5) simultaneously; The 14 pin CAP2 of the 5th chip (U5) links to each other with an end of the 19 electric capacity (C19); The other end of the 19 electric capacity (C19) links to each other with power supply ground GND; The 34 pin VSS of the 5th chip (U5) links to each other with power supply ground; The 36 pin RDY of the 5th chip (U5) links to each other with the 32 grafting pin of the tenth plug connector (J10); The 40 pin RXD of the 5th chip (U5) links to each other with the 17 grafting pin of the tenth plug connector (J10); The 42 pin TXD of the 5th chip (U5) links to each other with the 18 grafting pin of the tenth plug connector (J10); The 44 pin VDD of the 5th chip (U5) links to each other with+3.3V power supply with an end of an end of the 21 electric capacity (C21), the 20 electric capacity (C20) simultaneously; The other end of the 20 electric capacity (C20) links to each other with power supply ground GND with the other end of the 21 electric capacity (C21) simultaneously; The model of the 5th chip (U5) is the chip of XF-S3011.

6. the box-like microcomputer development plate of two-stage interface group according to claim 5 is characterized in that described sound amplifies output module (5) and is made up of the 23 resistance (R23) to the 25 resistance (R25), the 22 electric capacity (C22) to the 25 electric capacity (C25), loudspeaker (SP2), the 6th chip (U6), calibrating terminal and earphone socket (PHONEJACK); The first wiring pin of calibrating terminal links to each other with an end of the 23 electric capacity (C23), and the second pin-Vin of the other end the 6th chip (U6) of the 23 electric capacity (C23) links to each other; The second wiring pin of calibrating terminal links to each other with power supply ground GND with an end of the 22 electric capacity (C22) simultaneously, and the other end while of the 22 electric capacity (C22) and the first pin VDD of the 6th chip (U6) link to each other with+3.3V power supply; The three-prong HPSense of the 6th chip (U6) links to each other with an end of the 23 resistance (R23) and an end of the 24 resistance (R24) simultaneously; The other end of the 23 resistance (R23) links to each other with+3.3V power supply; The other end of the 24 (R24) links to each other with the second wiring pin of earphone socket (PHONEJACK); The 5th pin Vo1 of the 6th chip (U6) links to each other with terminals of loudspeaker (SP2); The 6th pin GND of the 6th chip (U6) links to each other with power supply ground GND; The 7th pin Bypass of the 6th chip (U6) links to each other with an end of the 24 electric capacity (C24); The other end of the 24 electric capacity (C24) links to each other with power supply ground GND; The 8th pin Vo2 of the 6th chip (U6) links to each other with another terminals of loudspeaker (SP2) and an end of the 25 electric capacity (C25) simultaneously; The other end of the 25 electric capacity (C25) links to each other with an end of the 25 resistance (R25) and the first wiring pin of earphone socket (PHONEJACK) simultaneously; The other end of the 25 resistance (R25) links to each other with the 3rd wiring pin of power supply ground GND and earphone socket (PHONEJACK) simultaneously; It is the chip of LM4875 that the 6th chip (U6) adopts model.

7. the box-like microcomputer development plate of two-stage interface group according to claim 6 is characterized in that described digital regulation resistance module (6) is made up of the 26 electric capacity (C26) to the 29 electric capacity (C29), the 7th chip (U7), the 8th chip (U8) and the 8th plug connector (J8); One end of the 26 electric capacity (C26) links to each other with+3.3V power supply with the second pin VDD of an end of the 27 electric capacity (C27), the 7th chip (U7) simultaneously; The other end of the 26 electric capacity (C26) links to each other with power supply ground GND with the other end of the 27 electric capacity (C27) simultaneously; The first pin W of the 7th chip (U7) links to each other with the first grafting pin of the 8th plug connector (J8); The three-prong GND of the 7th chip (U7) links to each other with power supply ground GND; The 4th pin SCL of the 7th chip (U7) links to each other with the 24 grafting pin of the tenth plug connector (J10); The 5th pin SDA of the 7th chip (U7) links to each other with the 23 grafting pin of the tenth plug connector (J10); The 6th pin AD0 of the 7th chip (U7) links to each other with power supply ground GND with the 7th pin B of the 7th chip (U7) simultaneously; The 8th pin of the 7th chip (U7) links to each other with+3.3V power supply;

One end of the 28 electric capacity (C28) links to each other with power supply ground GND with an end of the 29 electric capacity (C29) simultaneously; The other end of the 28 electric capacity (C28) links to each other with+3.3V power supply with the second pin VDD of the other end of the 29 electric capacity (C29), the 8th chip (U8) simultaneously; The three-prong GND of the 8th chip (U8) links to each other with power supply ground GND; The first pin W of the 8th chip (U8) links to each other with the second grafting pin of the 8th plug connector (J8); The 4th pin SCL of the 8th chip (U8) links to each other with the 24 grafting pin of the tenth plug connector (J10); The 5th pin SDA of the 8th chip (U8) links to each other with the 23 grafting pin of the tenth plug connector (J10); The 6th pin AD0 of the 8th chip (U8) links to each other with+3.3V power supply with the 8th pin A of the 8th chip (U8) simultaneously; The 7th pin of the 8th chip (U8) links to each other with power supply ground GND; It is the chip of AD5245 that described the 7th chip (U7) adopts model, and it is the chip of AD5245 that the 8th chip (U8) adopts model.

8. the box-like microcomputer development plate of two-stage interface group according to claim 7 is characterized in that described clock module (7) is made up of the 26 resistance (R26) to the 33 resistance (R33), the 30 electric capacity (C30) to the 32 electric capacity (C32), the 3rd crystal oscillator (JZ3), the 15 diode (D15) and the 9th chip (U9); One end of the 26 resistance (R26) links to each other with an end of the 31 resistance (R31) and the 31 grafting pin of the tenth plug connector (J10) simultaneously; The other end of the 31 resistance (R31) links to each other with the 5th pin INTRA of the 9th chip (U9); The other end of the 26 resistance (R26) links to each other with+3.3V power supply with an end of an end of an end of the 27 resistance (R27), the 32 resistance (R32), the 30 electric capacity (C30) simultaneously; The other end of the 27 resistance (R27) links to each other with an end of the 28 resistance (R28) and the 30 grafting pin of the tenth plug connector (J10) simultaneously; The other end of the 28 resistance (R28) links to each other with the first pin INTRB of the 9th chip (U9); The second pin SCL of the 9th chip (U9) links to each other with an end of the 29 resistance (R29); The other end of the 29 resistance (R29) links to each other with the 24 grafting pin of the tenth plug connector (J10); The three-prong SDA of the 9th chip (U9) links to each other with an end of the 30 resistance (R30), and the other end of the 30 resistance (R30) links to each other with the 23 grafting pin of the tenth plug connector (J10); The 4th pin GND of the 9th chip (U9) links to each other with power supply ground GND; The other end of the 30 electric capacity (C30) links to each other with power supply ground GND with an end of the 31 electric capacity (C31) simultaneously; The other end of the 32 resistance (R32) links to each other with the anode of the 15 diode (D15); The negative electrode of the 15 diode (D15) links to each other with the other end of the 31 electric capacity (C31) and the 8th pin VDD of the 9th chip (U9) simultaneously; The 7th pin OSCIN of the 9th chip (U9) links to each other with an end of the 33 resistance (R33); The other end of the 33 resistance (R33) links to each other with the 3rd wiring pin of the 3rd crystal oscillator (JZ3); The second wiring pin of the 3rd crystal oscillator (JZ3) links to each other with power supply ground GND, and the 4th wiring pin of the 3rd crystal oscillator (JZ3) links to each other with+3.3V power supply with an end of the 32 electric capacity (C32) simultaneously; The other end of the 32 electric capacity (C32) links to each other with power supply ground GND; It is the chip of SD2098 that the 9th chip (U9) adopts model.

9. the box-like microcomputer development plate of two-stage interface group according to claim 8 is characterized in that described memory module (8) is made up of the 34 electric capacity (C34) and the 11 chip (U11); One end of described the 34 electric capacity (C34) links to each other with the 4th pin CS of the 11 chip (U11); The other end of the 34 electric capacity (C34) links to each other with power supply ground GND with the first pin GND of the 11 chip (U11) simultaneously; The 5th pin SCK of the 11 chip (U11) links to each other with the 19 grafting pin of the tenth plug connector (J10); The 6th pin SI of the 11 chip (U11) links to each other with the 21 grafting pin of the tenth plug connector (J10); The 7th pin SO of the 11 chip (U11) links to each other with the 20 grafting pin of the tenth plug connector (J10); The 20 three-prong RDY of the 11 chip (U11) links to each other with the 28 grafting pin of the tenth plug connector (J10); The 25 pin WP of the 11 chip (U11) links to each other with+3.3V power supply with the 28 pin VCC of the 11 chip (U11) simultaneously;

Described character library unit module (9) is made up of the 33 electric capacity (C33), the 34 resistance (R34) and the tenth chip (U10); The first pin SO of the tenth chip (U10) links to each other with the 20 grafting pin of the tenth plug connector (J10); The second pin VSS of the tenth chip (U10) links to each other with power supply ground GND with an end of the 33 electric capacity (C33) simultaneously; The other end of the 33 electric capacity (C33) simultaneously and the 7th pin VCC of the tenth chip (U10) link to each other with+3.3V power supply; The 8th pin VSS of the tenth chip (U10) links to each other with power supply ground GND with the 9th pin VSS simultaneously; The 12 pin VSS of the tenth chip (U10) links to each other with power supply ground GND; The pin CLK of the tenth chip (U10) links to each other with the 19 grafting pin of the tenth plug connector (J10); The 14 pin HOLD of the tenth chip (U10) links to each other with an end of the 34 resistance (R34); The other end of the 34 resistance (R34) links to each other with+3.3V power supply; The 19 pin CS# of the tenth chip (U10)/link to each other with the 29 grafting pin of the tenth plug connector (J10); The 20 pin SI of the tenth chip (U10) links to each other with the 21 grafting pin of the tenth plug connector (J10); It is the chip of GT23L32S4W that the tenth chip (U10) adopts model, and it is the chip of AT45DB081 that the 11 chip (U11) adopts model.

10. the box-like microcomputer development plate of two-stage interface group according to claim 9 is characterized in that described usb data interface module (10) is made up of the 35 resistance (R35), the 35 electric capacity (C35) to the 37 electric capacity (C37), the 9th plug connector (J9) and twelve-core sheet (U12); One end of the 36 electric capacity (C36) links to each other with+3.3V power supply with the 6th pin VDD of an end of the 35 electric capacity (C35), twelve-core sheet (U12) simultaneously; The other end of the 36 electric capacity (C36) links to each other with power supply ground GND with the other end of the 35 electric capacity (C35), the three-prong GND of twelve-core sheet (U12) simultaneously; The first pin DCD of twelve-core sheet (U12) links to each other with the 4th grafting pin of the 9th plug connector (J9); The 4th pin of twelve-core sheet (U12) links to each other with the 3rd grafting pin of the 3rd plug connector (J3); The 5th pin of twelve-core sheet (U12) links to each other with the second grafting pin of the 3rd plug connector (J3); The 7th pin REGIN of twelve-core sheet (U12) links to each other with+5V power supply with the 8th pin VBUS of an end of an end of the 37 electric capacity (C37), the 35 resistance (R35), twelve-core sheet (U12) simultaneously; The other end of the 35 resistance (R35) links to each other with the 9th pin RST of twelve-core sheet (U12); The other end of the 37 electric capacity (C37) links to each other with power supply ground GND; The 11 pin of twelve-core sheet (U12) links to each other with the 5th grafting pin of the 9th plug connector (J9); The 12 pin of twelve-core sheet (U12) links to each other with the 6th grafting pin of the 9th plug connector (J9); The 20 three-prong CTS of twelve-core sheet (U12) links to each other with the 8th grafting pin of the 9th plug connector (J9); The 24 pin RTS of twelve-core sheet (U12) links to each other with the 7th grafting pin of the 9th plug connector (J9); The 27 pin DSR of twelve-core sheet (U12) links to each other with the second grafting pin of the 9th plug connector (J9); The 28 pin DTR of twelve-core sheet (U12) links to each other with the first grafting pin of the 9th plug connector (J9);

Described sound load module (11) is made up of the 38 electric capacity (C38) to the 40 electric capacity (C40), the 13 chip (U13), the tenth four-core sheet (U14), the 36 resistance (R36) and the 37 resistance (R37); One end of the 38 electric capacity (C38) links to each other with power supply ground GND, and the other end of the 38 electric capacity (C38) links to each other with+3.3V power supply with an end of the first pin VDD of the 13 chip (U13), the 40 electric capacity (C40) simultaneously; First terminals of the 36 resistance (R36) link to each other with power supply ground GND, and second terminals of the 36 resistance (R36) link to each other with+3.3V power supply; The 3rd terminals of the 36 resistance (R36) link to each other with the 4th pin DCVol/SD of the 13 chip (U13); The other end of the 40 electric capacity (C40) links to each other with the 4th a pin POWER of the tenth four-core sheet (U14) and an end of the 37 resistance (R37) simultaneously; The other end of the 37 resistance (R37) links to each other with power supply ground GND; The second pin GND of the tenth four-core sheet (U14) links to each other with power supply ground GND with the three-prong GND of the tenth four-core sheet (U14) simultaneously; The 4th pin OUTPUT of the tenth four-core sheet (U14) links to each other with+3.3V power supply; The 6th pin GND of the 13 chip (U13) links to each other with power supply ground GND; The 7th pin of the 13 chip (U13) links to each other with an end of the 39 electric capacity (C39), and the other end of the 39 electric capacity (C39) links to each other with power supply ground GND; It is the chip of LM4875 that the 13 chip (U13) adopts model; It is the microphone chip of MSM2C that the tenth four-core sheet (U14) adopts model.