[embodiment]
The mutual method of testing of a kind of lcd controller and video input controller, the data wire of described lcd controller is divided into 3 the tunnel to be tested, external hardware circuit by lcd controller carries out after acquisition time promptly selects the first via to carry out image data and data analysis earlier, switch to the second the tunnel and carry out same image data and data analysis, at last Third Road is carried out same image data and data analysis, earlier lcd controller is produced the RGB sequential of horizontal-drive signal VSYNC negate, and the interface of employing lcd controller is as the dateout interface, the dateout of gathering lcd controller by described video input controller acquisition interface, each circuit-switched data that obtains on the lcd screen in the process of gathering each circuit-switched data all is presented on the same screen, whether the data of more described lcd controller output are consistent with the data that described video input controller collects, thereby finish test.
The invention will be further described below in conjunction with a specific embodiment.
By lcd controller sequential and video input controller sequential as can be known, the horizontal-drive signal VSYNC negate in the RGB sequential of lcd controller, the sequential that obtains is just in full accord with the sequential of video input controller, therefore utilize this point, allow the RGB sequential of the frame synchronizing signal VSYNC negate that lcd controller produces, the dateout of gathering lcd controller by video input controller acquisition interface, relatively the data sent of lcd controller and the video input controller data of adopting just can verify whether lcd controller module and video input controller module be working properly, because wherein any one holding wire or data wire are made mistakes, can cause that all the data of adopting make mistakes.
What note in its test process is: the data wire of video input controller has only 8, and the data wire of lcd controller has 24 (or 16,8), the way that addresses this problem is that the data wire with lcd controller is divided into 3 batches, survey as one group for each 8, do acquisition time by the external hardware circuit, just select the first via earlier, gathered, behind the compare OK, switch to the second the tunnel and carry out same collection and data analysis, Third Road also is the same by that analogy, the data that at every turn refresh on the screen in the process of image data are data on the same screen, so just can guarantee that the data of adopting for three times are one group of stable values.
In order to test the situation whether the lcd controller data wire can exist short circuit or open circuit, need give some special data on the lcd controller data wire in addition, these data can be found whether short circuit or open circuit of data wire.The data that can select to send are { 0xFFFFFF, 0x000000,0xAAAAAA, 0x555555,0x5A5A5A, 0xA5A5A5,0x999999,0x666666}.These data are not to send on delegation, and whole screen is divided into 8, and each sheet is sent one group of data wherein respectively, as shown in Figure 1, why send like this, are simple on the software processes, and can not influence the checking of data wire again.
That Fig. 2 describes is lcd controller (LCD Control) and the mutual testing principle figure of video input controller, and wherein, the left side is a lcd controller, and the right is the video input controller; The lcd controller data bit of 24bit is divided into the data of 3 groups of 8bit after by variable connector, link to each other with the 8bit data wire of video input controller respectively, LCDC_CLK, HSYNC, VSYNC link to each other with VIP_CLK, Href, the VSYNC of video input controller respectively, the lcd controller data that the video input controller adopts the method for time-sharing operation to remove to gather 3 groups of 8bit;
After process VSYNC is reverse, lcd controller will be sent sequential as shown in Figure 3:
When as shown in Figure 3 this sequential of video input controller collection, on the sequential as can be seen:
1) (non-CCIR656 signal is because the CCIR656 signal is not have independent capable field sync signal to each frame, and be included on 8 the data wire, just do not have blanking) several row in front of beginning, frame final blanking just, the data of adopting are not the data of sending, and may all be 0.Just because of this, when comparing data, be that the place from nline=v bp begins.
2) several row in back of each frame (non-CCIR656 signal) end, blanking before the frame just, the data of adopting are not the data of sending, and may all be 0.
3) several pixels of each row front, just capable final blanking, the data of adopting are not the data of sending, and may all be 0.Just because of this, when comparing data, be that the place from nPixel=(h_bp/2) begins.Why will remove 2, be because the data of adopting are stored at Y0_array and two application heaps of UV0_array to have gone.
4) several pixels of each row end, blanking before the row just, the data of adopting are not the data that will send, may all be 0.
5) data from sending can be seen, in data in the effective time, DB[7:0], DB[15:8], DB[23:16] value all equate, such as sending 0xA5A5A5, DB[7:0], DB[15:8], DB[23:16] all equal 0xA5 as shown in Figure 4.
6) from the angle of video input controller, the data that lcd controller is sent, the video input controller is thought the camera data sent with the UYVY order, gathers, so the data that lcd controller is sent will clocklike be placed in Y0_array and two application heaps of UV0_array.Because the video input controller just begins image data when uprising from HSYNC, after just HSYNC uprises, the video input controller just thinks that the data on the data wire are to send with UYVY, when therefore really being active data, that first data correspondence is Y or U or V on earth, will see the clock DOTCLK number of pulses of capable final blanking.
As everyone knows, the lcd controller interface is data and sequential output interface, the video input controller then is the data inputs, sequential then is the interface that can be set to the input mode or the way of output, and lcd controller interface and video input controller have the part of intersection on the work clock size simultaneously.Therefore this method of testing is according to these characteristics of these two interfaces, adopt the lcd controller interface as output interface, video input controller interface judges by the data that analysis video input controller is adopted whether lcd controller and video input controller have problem as input interface.What be worth emphasizing is, if just wherein a certain side to be measured, as the lcd controller interface, the video input controller interface that must guarantee subtest so before test is (gathering as adopting known main control chip out of question and band video input controller interface) out of question, otherwise too.
Above content measurement is simple pin binding situation test thinking, but for the lcd controller in the practical application, have and much enrich very much output signal type, data format, display mode etc., these can be adjusted by adjusting dateout and output mode, form, to reach test, for example following adjustment output mode combination to the relevant controller in inside:
1) common layer 10: on WIN0, show the data combination of the independent rgb format output of above describing: { 0xFFFFFF, 0x000000,0xAAAAAA, 0x555555,0x5A5A5A, 0xA5A5A5,0x999999,0x666666}, but be the reduction capability of test WIN0, therefore when adopt dwindle pattern output after on screen this part less than demonstration;
2) WIN0 dwindles 20: this part is on the data basis of common layer, has used the final displaying contents of reduction capability of WIN0;
3) WIN0, WIN1 (transparent) 30: present most lcd controller has all designed can survey display mode more, suppose to have two windows, for the test window overlapping controller whether normal, can do such design, basic lcd controller has all designed the transparency conditioning controller, main also is to be applied under the situation of window stack, the value of a transparency also can be set, in output in the corresponding way simultaneously;
How such three groups of different patterns are shown to (above " data that at every turn refresh on the screen in the process of image data are on the same screen " also is to realize with such method) on the screen simultaneously, be such realization in fact: suppose at first that screen is 800 * 480 RGB screen, be ready to two groups of data, one group is the data to common layer (WIN0 window) output, another group is two data that the window stack will be exported, and uses window that two kinds of displaying contents of function setup are set;
LCDCSetWin0 (); //WIN0 dwindles twice
LCDCSetWin1 (); The transparent mode of //WIN1
When starting clear screen, the data of actual output are exactly the same as described in Figure 5 on screen afterwards.This is a kind of by exporting the scheme preferably that screen data are tested numerous mode controllers.
In test, it should be noted that:
When 1, pin is tested, guarantee that the data of final output must guarantee to have tested two kinds of level states of every pin, also to get rid of simultaneously the situation that short circuit appears in adjacent one or more pin, so must comprise following data (0xff, 0x00,0xaa, 0x55,0x5a, 0xa5,0x66,0x99) in the data of test.
2, some controller test can merge, such as the stack of the window of some product support, window amplify with dwindle, the whether transparent controller of window, some then is mutual exclusion, different-format such as the form controller of dateout can't once realized in the test, needs many wheel tests to realize.
3, will guarantee when circuit connects that the row field sync signal does not have and disturbed by other, generally, the HSYNC signal will possess the filter capacitor that suitable size is arranged, and occurrence needs go to regulate according to the rule of hardware circuit and fabric swatch.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.