CN102163131B - Data access method for flash memory and flash memory device - Google Patents
Data access method for flash memory and flash memory device Download PDFInfo
- Publication number
- CN102163131B CN102163131B CN 201010136426 CN201010136426A CN102163131B CN 102163131 B CN102163131 B CN 102163131B CN 201010136426 CN201010136426 CN 201010136426 CN 201010136426 A CN201010136426 A CN 201010136426A CN 102163131 B CN102163131 B CN 102163131B
- Authority
- CN
- China
- Prior art keywords
- block
- data
- address
- fat
- flash memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Read Only Memory (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to a data access method for a flash memory and a flash memory device. The method comprises the following steps of: firstly, receiving a write-in command, a write-in address and write-in data from a host; secondly, determining a target block corresponding to the write-in address; thirdly, searching whether data are stored in a storage space corresponding to the write-in address in the target block; if the data are not stored in the storage space of the target block, writing the write-in data into the storage space of the target block; otherwise, checking whether the target block has a corresponding sub block in the flash memory; if the sub block exists, checking whether the write-in address follows a final address of the stored data in the sub block; if the write-in address follows the final address, writing the write-in data into the sub block; otherwise, checking whether the target block has a corresponding file allocation table block in the flash memory; and finally, if the file allocation table block exits, writing the write-in data into the file allocation table block.
Description
Technical field
The present invention relates to the memory technology field, more particularly, relate to a kind of data access method and flash memory device of flash memory.
Background technology
Flash memory (flash memory) comprises a plurality of blocks (block), and each block comprises that a plurality of pages or leaves (page) are for data storing.When the flash memory self-controller receives when writing order, just according to the indication of controller and writing address with data storing some page or leaf to these blocks.When the flash memory self-controller is received reading order, just according to the indication of controller and reading address from some page sense data of these blocks and return data to controller.
Yet a blank page of a block of flash memory only can be written into a secondary data.After this blank page was written into data, blank page just became a data storing page or leaf.The data of the whole block that comprises this data storing page or leaf of erasing unless controller is issued orders, and make this data storing page or leaf be reduced into blank page, otherwise this data storing page or leaf can not be written into data again.Yet, therefore because a block comprises number with the page or leaf of thousand notes, need spend a lot of time from the block data of erasing, also therefore controller can't be with the erase data of block of high-frequency.
When main frame to writing order under the controller with stores new to a writing address, and controller finds that a specific page of the corresponding particular block of this writing address has stored legacy data, and then controller just can't will write from the new data that main frame receives this specific page again.Yet main frame still need be carried out the above-mentioned order that writes.Generally speaking, controller this moment just can choose a blank block from a plurality of blocks of flash memory, with substituting storage from new data that main frame was received.The block of stores new and this particular block correspond to this writing address equally, so between the block of this particular block and stores new one corresponding relation are arranged.This particular block is called as female block (mother block), in order to store the raw data of an address realm; And the block of stores new is called as sub-block (child block), in order to store the more new data of this address realm.
Fig. 1 is the synoptic diagram of female block 102 and corresponding sub-block 104 in the flash memory of known techniques.The corresponding address realm of a plurality of pages or leaves of female block 102 has stored respectively raw data A0, B0, C0 and D0 from 0～1000.When main frame requires controller more during new data B1 writing address 400～600, because female block 102 has stored raw data B0 corresponding to the storage area of address 400～600, controller can't be again writes female block 102 with new data B1 more.At this moment, controller just can be chosen a blank block of flash memory as the sub-block 104 of female block 102, the raw data A0 of address 0～400 by copying to sub-block 104 in female block 102, and will be write from the more new data B1 that main frame receives the address realm 400～600 of sub-block 104.Same, if main frame require once again controller will be more new data C1 writing address 601～700 o'clock, because controller can't be again new data C1 is more write female block 102, controller just directly will write from the more new data C1 that main frame receives the address realm 601～700 of sub-block 104.
Yet, if main frame require once again controller will be more new data writing address 0～700 o'clock, because the address realm 0～700 of sub-block 104 has stored more new data and can't write new data again, controller just can't be finished by new data more writes sub-block 104 order that writes of main frame.Therefore, need a kind of data access method of flash memory, the problem that exists to solve known techniques.
Summary of the invention
The technical problem to be solved in the present invention is, for the defects of prior art, provides a kind of data access method and flash memory device of flash memory, the problem that exists to solve known techniques.
One of the technical solution adopted for the present invention to solve the technical problems is: the data access method of constructing a kind of flash memory.At first, receive one from a main frame and write order, a writing address and data writing.Then, determine the target block that this writing address is corresponding.Then, check in this target block corresponding to a storage area of this writing address storage data whether.If this storage area of this target block is storage data not yet, this data writing is write this storage area of this target block.If this storage area of this target block is storage data, check whether this target block has a corresponding sub-block (childblock) and be present in this flash memory.If this sub-block exists, check whether this writing address is connected in a most end address of storage data in this sub-block.If this writing address is connected in this most end address, this data writing is write this sub-block.If this writing address is not connected in this most end address, check whether this target block has a corresponding FAT (file allocation table, FAT) block and be present in this flash memory.At last, if this FAT block exists, this data writing is write this FAT block.
The data access method of the described flash memory of the invention described above, wherein the method more comprises:
When if this sub-block does not exist, this flash memory is chosen a blank block as this sub-block certainly; And
This data writing is write this sub-block.
The data access method of the described flash memory of the invention described above, wherein the method more comprises:
When if this FAT block does not exist, this flash memory is chosen a blank block as this FAT block certainly; And
This data writing is write this FAT block.
The data access method of the described flash memory of the invention described above, the step that wherein this data writing is write this FAT block comprises:
This data writing is write this FAT block; And
The corresponding table of one scheduler is write this FAT block;
The corresponding relation of a scheduler of this data writing of storage in one original address that wherein should store this data writing in corresponding this target block of table record of this scheduler and this FAT block.
The data access method of the described flash memory of the invention described above, the step that wherein this data writing is write this sub-block comprises:
Check whether this target block has this corresponding FAT block and be present in this flash memory;
Check whether this FAT block has stored the more new data of this writing address;
When this FAT block exists and this FAT block when having stored the data of this writing address, this writing address by the corresponding list deletion of a scheduler of this FAT block, is supplied to be stored in this FAT block to obtain the corresponding table of a new scheduler; And
This data writing is write one of this sub-block storage area that continues;
The corresponding relation of the scheduler of the corresponding more new data that wherein stores in the original address of corresponding this target block of table record of this scheduler and this FAT block.
The data access method of the described flash memory of the invention described above, wherein the start address of this storage area that continues is connected in this most end address of storage data in this sub-block.
The data access method of the described flash memory of the invention described above, wherein the method more comprises:
Receive a reading order and a reading address from this main frame;
Determine that this reading address corresponding reads target block;
Check that this reads target block and whether has corresponding one and read the FAT block and be present in this flash memory;
When if this reads the FAT block and exists, check that this reads one first new data more whether the FAT block stores this reading address; And
If this reads the FAT block and stores this first new data more, this reads the FAT block and reads this first new data more certainly.
The data access method of the described flash memory of the invention described above, wherein the method more comprises:
Block does not exist if this reads FAT, if or this read the FAT block and do not store this first new data more, check that this reads target block and whether has corresponding one and read sub-block and be present in this flash memory; And
Do not exist if this reads sub-block, this reads target block and reads one second new data more that stores with this reading address certainly.
The data access method of the described flash memory of the invention described above, wherein the method more comprises:
Exist if this reads sub-block, check this read sub-block whether store this reading address one the depth of the night new data;
If this reads sub-block and stores this new data depth of the night, this reads sub-block and reads this new data depth of the night certainly; And
If this reads sub-block and does not store this new data the depth of the night, this reads target block and reads this second new data more that stores with this reading address certainly.
Two of the technical solution adopted for the present invention to solve the technical problems is: construct a kind of flash memory device.This quick flashing memory device comprises a flash memory and a controller.This flash memory comprises that a plurality of blocks (block) are with the storage data.This controller receives one from a main frame and writes order, one writing address, and data writing, determine the target block that this writing address is corresponding, check in this target block corresponding to a storage area of this writing address storage data whether, when this storage area of this target block not yet writes this data writing during storage data this storage area of this target block, when this storage area of this target block storage data, check whether this target block has a corresponding sub-block (child block) and be present in this flash memory, when existing, this sub-block checks whether this writing address is connected in a most end address of storage data in this sub-block, when this writing address is connected in this most end address, this data writing is write this sub-block, when not being connected in this most end address, this writing address checks whether this target block has a corresponding FAT (file allocation table, FAT) block is present in this flash memory, and this data writing is write this FAT block when this FAT block exists.
The described flash memory device of the invention described above, wherein when this sub-block did not exist, this controller was chosen a blank block as this sub-block from this flash memory, and this data writing is write this sub-block.
The described flash memory device of the invention described above, wherein when this FAT block did not exist, this controller was chosen a blank block as this FAT block from this flash memory, and this data writing is write this FAT block.
The described flash memory device of the invention described above, wherein when this controller writes this FAT block with this data writing, this controller writes this FAT block with this data writing, and the corresponding table of a scheduler write this FAT block, the corresponding relation of a scheduler of this data writing of storage in an original address that wherein should store this data writing in corresponding this target block of table record of this scheduler and this FAT block.
The described flash memory device of the invention described above, wherein when this controller writes this sub-block with this data writing, this controller checks whether this target block has this corresponding FAT block and be present in this flash memory, check whether this FAT block has stored the more new data of this writing address, when this FAT block exist and this FAT block a new scheduler is corresponding to be shown for being stored in this FAT block to obtain by the corresponding list deletion of a scheduler of this FAT block with this writing address when having stored the data of this writing address, and this data writing write one of this sub-block storage area that continues, the corresponding relation of the scheduler of the corresponding more new data that wherein stores in the original address of corresponding this target block of table record of this scheduler and this FAT block.
The described flash memory device of the invention described above, wherein the start address of this storage area that continues is connected in this most end address of storage data in this sub-block.
The described flash memory device of the invention described above, wherein this controller receives a reading order and a reading address from this main frame, determine that this reading address corresponding reads target block, check that this reads target block and whether has corresponding one and read the FAT block and be present in this flash memory, check when the FAT block exists that when this reads this reads one first new data more whether the FAT block stores this reading address, and store this and first more read the FAT block from this during new data and read this first new data more when this reads the FAT block.
The described flash memory device of the invention described above, wherein when this reads the FAT block and does not exist, maybe when reading the FAT block, this does not store this first more during new data, this controller checks that this reads target block and whether has corresponding one and read sub-block and be present in this flash memory, and when this read sub-block and does not exist, this controller read target block from this and reads one second new data more that stores with this reading address.
The described flash memory device of the invention described above, wherein when this reads sub-block and exists this controller check this read sub-block whether store this reading address one the depth of the night new data, when this read sub-block store this depth of the night during new data this controller read sub-block from this and read this new data the depth of the night, and when this read sub-block do not store this depth of the night during new data this controller read target block from this and read this second new data more that stores with this reading address
Implement data access method and the flash memory device of flash memory of the present invention, have following beneficial effect:, in flash memory, choose a blank block as the FAT block corresponding with this particular block, and latest data write the FAT block, even the renewal Data duplication of same address realm is write the FAT block, the FAT block can also a scheduler latest data record position of corresponding this address realm of table record, therefore solved the problem that overrides data that sub-block in the known techniques can't be accepted same address realm.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the synoptic diagram of female block and corresponding sub-block in the flash memory of known techniques;
Fig. 2 is the block diagram of a data storage system of the present invention;
Fig. 3 is the process flow diagram of the method for writing data of flash memory of the present invention;
Fig. 4 A shows a succession of embodiment that writes order that main frame sends to quick flashing memory device;
Fig. 4 B shows the female block that writes the access of order institute and corresponding sub-block and the FAT block thereof of Fig. 4 A;
Fig. 5 is the corresponding embodiment who shows of scheduler that FAT block of the present invention stores;
Fig. 6 is the process flow diagram of the method for reading data of flash memory of the present invention.
[primary clustering symbol description]
200～data storage system;
202～main frame;
204～quick flashing memory device;
212～controller;
214～flash memory;
221,222 ..., 22K～female block;
231,232 ..., 23K～sub-block;
241,242 ..., 24K～FAT block.
Embodiment
Fig. 2 is the block diagram of a data storage system 200 of the present invention.Data storage system 200 comprises a main frame 202 and a quick flashing memory device 204.Quick flashing memory device 204 is main frame 202 storage datas.In an embodiment, quick flashing memory device 204 comprises a controller 212 and a flash memory 214.Flash memory 214 comprises a plurality of blocks (block), and each block comprises a plurality of pages or leaves (page), for storage data.Write order when main frame 202 sends to quick flashing memory device 204, controller 212 writes to flash memory 214 according to the order that writes that main frame 202 sends with data.When main frame 202 sends reading orders to quick flashing memory device 204, the reading order that controller 212 sends according to main frame 202 is from flash memory 214 reading out datas.
When certain address scope of a particular block of flash memory 214 storage data, and main frame 202 requires controller 212 will more new data writes this address realm once again the time, and controller 212 just can't write new data the more same address realm of this particular block.In known techniques, controller 212 can be chosen a blank block as the sub-block (child block) of this particular block, to store the more new data of this address realm in flash memory 214.Yet, when this address realm of sub-block has stored more new data, if when main frame required that once again latest data write this address realm, controller also can't write sub-block with latest data.
At this moment, controller 212 of the present invention can be chosen a blank block as FAT (file allocation table, the FAT) block corresponding with this particular block in flash memory 214, and latest data is write the FAT block.As shown in Figure 2, the female block 221 in the flash memory 214, sub-block 231, FAT block 241 correspond to same address realm, and female block 22K, sub-block 23K, FAT block 24K correspond to same address realm.The character of FAT block is not identical with sub-block.Sub-block only can store the continuous more new data in address, but and the more new data of the arbitrary address fragment in the FAT block storage area block address scope.Even controller 212 writes the FAT block with the renewal Data duplication of same address realm, the FAT block can also a scheduler latest data record position of corresponding this address realm of table record, therefore solved the problem that overrides data that sub-block in the known techniques can't be accepted same address realm.
Fig. 3 is the process flow diagram of the method for writing data 300 of flash memory of the present invention.Controller 212 is according to the write order of method 300 execution from main frame 202 receptions.At first, controller 212 receives from main frame 202 and writes order, writing address and data (step 302).Then, controller 212 determines the corresponding target block of this writing address (step 304), this target block be flash memory 214 a plurality of blocks one of them.Then, whether controller 212 checks in target block the corresponding storage area of this writing address storage data (step 306).If the corresponding storage area of this writing address storage data not yet in this target block, then controller 212 directly writes the corresponding storage area of this writing address (step 308) in the target block with the data that main frame 202 transmits.
Yet if the corresponding storage area of writing address has stored data in this target block, controller 212 can't write data this storage area of target block once again.At this moment, controller 212 checks whether target block has a corresponding sub-block to be present in the flash memory 214 (step 310).Do not exist if target block does not have a corresponding sub-block, then controller 212 is chosen a blank block of flash memory 214 as the sub-block (step 312) of target block, and the data that main frame 202 is transmitted write this sub-block (step 314).Otherwise, if having a corresponding sub-block, target block has (step 310), then controller 212 checks whether the writing address of the data that main frame 202 transmits is connected in the most end address (step 316) of storage data in this sub-block.
If writing address is connected in the most end address (step 316) of storage data in this sub-block, then controller 212 continues the FAT block whether the inspection target block has a correspondence, and whether this FAT block has stored the more new data (step 318) of this writing address.If target block does not have the FAT block of a correspondence, or the FAT block of target block not yet stores the more new data of this writing address, and then controller 212 directly writes sub-block (step 314) with the data that main frame 202 transmits.If having the FAT block of a correspondence, target block is present in this flash memory, and this FAT block has stored the more new data (step 318) of this writing address, then with the scheduler correspondence list deletion (step 320) of writing address from this FAT block, the data that again main frame 202 transmitted write sub-block (step 314) to controller 212 first.
If writing address is not the most end address (step 316) that is connected in storage data in this sub-block, then controller 212 checks whether target block has the FAT block of a correspondence to be present in the flash memory 214 (step 322).If target block does not have the FAT block of a correspondence, then controller 212 is chosen a blank block as the sub-block (step 326) of target block in flash memory 214, and the data that main frame 202 is transmitted write this sub-block (step 328).If target block has the FAT block (step 322) of a correspondence, then controller 212 directly writes this FAT block (step 324) with the data that main frame 202 transmits.When controller 212 writes the FAT block with data (step 324,328), controller 212 can write this FAT block with the corresponding table of a scheduler in the lump, wherein should store in the original address of the data that write and this FAT block corresponding relation in order to a scheduler that stores these data in the corresponding table record target block of this scheduler.
The method for writing data 300 of above-mentioned flash memory can Fig. 4 A and Fig. 4 B shown in embodiment describe.Fig. 4 A shows a succession of embodiment that writes order that main frame 202 sends to quick flashing memory device 204.Fig. 4 B shows the female block 402 that writes the access of order institute of Fig. 4 A and corresponding sub-block 404 and FAT block 406 thereof.Supposing that controller 212 is at first received from main frame 202 writes order 1, this write order 1 require controller 212 more new data H write the address realm 101～200 of flash memory 214.Suppose that female block 402 of flash memory 214 stores the raw data of address realm 0～1000, therefore write the address realm of order 1 corresponding to female block 402.Yet because the address realm 101～200 of female block 402 has stored data, so controller 212 can't write female block 402 with new data more.
Because female block 402 does not have corresponding FAT block 406 and sub-block 404 at the beginning the time, therefore controller 212 is chosen a blank block as the sub-block 404 of female block 402, the address is copied to sub-block 404 between 0～100 raw data, will be write by the more new data H that main frame 202 receives the address realm 101～200 of sub-block 404 again.Then, main frame 202 transmits to controller 212 and writes order 2, requires data I writing address scope 201～300.Because the address realm 101～200 of female block 402 has stored data, and address realm 201～300 corresponding to data I is connected in the most end writing address 200 of sub-block 404, and this moment, female block 402 did not have corresponding FAT block 406, so controller 212 will upgrade the address realm 201～300 that data I writes sub-block 404.
Then, main frame 202 transmits to controller 212 and writes order 3, requires data J writing address scope 251～400.Data J can be divided into the data J corresponding to address realm 251～300
1Reach the data J corresponding to address realm 301～400
2, data J wherein
2Corresponding address realm 301～400 is connected in the most end writing address 300 of sub-block 404, so controller 212 is incited somebody to action more new data J
2Write the address realm 301～400 of sub-block 404.Because data J
1Corresponding address realm 251～300 overlaps with the address realm of the data I that sub-block 404 stores, so controller 212 can't be with data J
1Be stored into sub-block 404.Therefore, controller 212 is chosen a blank block as the FAT block 406 of female block 402 correspondences, more new data J
1 Write FAT block 406, and incite somebody to action more new data J
1The corresponding Table I of corresponding scheduler writes FAT block 406.
Then, main frame 202 transmits to controller 212 and writes order 4, requires data K writing address scope 451～500.Because the address realm 451～500 of data K is not connected in the most end data address 400 in the sub-block 404, and this moment, female block 402 had corresponding FAT block 406, therefore controller 212 direct more new data K write FAT block 406, and the more new data J before more new data K reaches
1The corresponding Table II of corresponding scheduler writes FAT block 406.Then, main frame 202 transmits to controller 212 and writes order 5, requires data M writing address scope 401～500.Because address realm 401～500 was connected in sub-block 404 and stored the more most end address 400 of new data this moment, so controller 212 directly will upgrade data M and write sub-block 404.Yet, because FAT block 406 has stored the more new data K of address realm 451～500, overlap mutually with the address realm of new data K more and upgrade data M, therefore controller 212 will upgrade data M and be deleted by the corresponding Table II of scheduler before with the overlapping address realm 451～500 of new data K more, thereby produce a new scheduler correspondence Table III to write FAT block 406.
Fig. 5 is an embodiment of the corresponding table 500 of scheduler of FAT block storage of the present invention.The all more new datas that store in the save File allocation list block in the scheduler table 500 are in the original address of female block and the corresponding relation of the actual address that stores in the FAT block at present.The corresponding table 500 of scheduler comprises two corresponding hurdles.Suppose the FAT block of the corresponding table 500 of storage scheduler corresponding to a female block, and should address realm 0～1000 corresponding to mother's block.Therefore, the first hurdle of the corresponding table 500 of scheduler is address realm corresponding to this mother's block 0～1000.The actual address that the second hurdle of the corresponding table 500 of scheduler stores in the FAT block for the more new data in order to the address that substitutes female block.If store in the FAT block in order to substitute the more new data of the original address X that is stored in female block, and this more the address that in the FAT block, stores of new data be Y, then corresponding second hurdle of original address X of female block on the first hurdle of the corresponding table 500 of scheduler has stored the address Y of FAT block.For instance, in the corresponding table 500 of scheduler, original address 0～2 there is no corresponding renewal data storing address, so there is no the more new data that stores original address 0～2 in the FAT block.In the corresponding table 500 of scheduler, original address 998
9 have corresponding renewal data storing address 353 and 354, so the address 353 of FAT block stored the more new data of original address 998, and the address 354 of FAT block has stored the more new data of original address 999.Therefore, controller 212 can be by stored all of fixed this FAT block of the corresponding voting of the stored up-to-date scheduler of a FAT the block more original address of new data and the actual address of storage.
Fig. 6 is the process flow diagram of the method for reading data 600 of flash memory of the present invention.Controller 212 is carried out the reading order that receives from main frame 202 according to method 600.At first, controller 212 receives a reading order and a reading address (step 602) from main frame 202.Then, controller 212 determines target block (step 604) corresponding to this reading address.Then, controller 212 checks that FAT (FAT) block whether these target block have a correspondence is present in the flash memory 214 (step 606).If target block has the FAT block of a correspondence, controller 212 checks that the corresponding table of the stored up-to-date scheduler of this FAT block is to determine whether this FAT block stores the more new data (step 612) of this reading address.If this FAT block stores the more new data of this reading address, then controller 212 reads the more new data (step 614) of this reading address from this FAT block.
Yet, if controller 212 finds that the FAT block does not store the more new data (step 612) of this reading address, or target block does not have the FAT block (step 606) of a correspondence, and then controller 212 checks that the sub-block whether these target block have a correspondence is present in the flash memory 214 (step 608).If this target block does not have the sub-block of a correspondence, then controller 212 directly reads the raw data (step 610) of this reading address from this target block.If this target block has the sub-block (step 608) of a correspondence, then controller 212 continues to check whether this sub-block stores the more new data (step 616) of this reading address.If this sub-block stores the more new data of this reading address, then controller 212 reads the more new data (step 618) of this reading address from this sub-block.Otherwise if this sub-block does not store the more new data (step 616) of this reading address, then controller 212 directly reads the raw data (step 610) of this reading address from this target block.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; any those who familiarize themselves with the technology; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (16)
1. the data access method of a flash memory is characterized in that, comprising:
S100) receive one from a main frame and write order, a writing address and data writing;
S200) determine the target block that this writing address is corresponding, wherein this target block be this flash memory a plurality of blocks one of them;
S300) check in this target block corresponding to a storage area of this writing address storage data whether;
S400) if this storage area of this target block storage data not yet writes this data writing this storage area of this target block;
S500) if this storage area of this target block storage data checks whether this target block has a corresponding sub-block and be present in this flash memory;
S600) if this sub-block exists, check whether this writing address is connected in a most end address of storage data in this sub-block;
S700) if this writing address is connected in this most end address, this data writing is write this sub-block;
S800) if this writing address is not connected in this most end address, check whether this target block has a corresponding FAT block and be present in this flash memory; And
If this FAT block exists, this data writing is write this FAT block;
The step that wherein this data writing is write this sub-block comprises:
S710) check whether this target block has this corresponding FAT block and be present in this flash memory;
S720) check whether this FAT block has stored the more new data of this writing address;
S730) exist and this FAT block when having stored the more new data of this writing address when this FAT block, this writing address by the corresponding list deletion of a scheduler of this FAT block, is supplied to be stored in this FAT block to obtain the corresponding table of a new scheduler; And
S740) this data writing is write one of this sub-block storage area that continues;
The corresponding relation of the scheduler of the corresponding more new data that S750) wherein stores in the original address of corresponding this target block of table record of this scheduler and this FAT block.
2. the data access method of flash memory according to claim 1 is characterized in that, wherein the method more comprises:
When if this sub-block does not exist, this flash memory is chosen a blank block as this sub-block certainly; And
This data writing is write this sub-block.
3. the data access method of flash memory according to claim 1 is characterized in that, wherein the method more comprises:
In step S800, if when this FAT block does not exist, this flash memory is chosen a blank block as this FAT block certainly; And
This data writing is write this FAT block.
4. the data access method of flash memory according to claim 1 is characterized in that, in step S800, the step that this data writing is write this FAT block comprises:
This data writing is write this FAT block; And
The corresponding table of one scheduler is write this FAT block;
The corresponding relation of a scheduler of this data writing of storage in one original address that wherein should store this data writing in corresponding this target block of table record of this scheduler and this FAT block.
5. the data access method of flash memory according to claim 1 is characterized in that, wherein the start address of this storage area that continues is connected in this most end address of storage data in this sub-block.
6. the data access method of flash memory according to claim 1 is characterized in that, wherein the method more comprises:
Receive a reading order and a reading address from this main frame;
Determine that this reading address corresponding reads target block;
Check that this reads target block and whether has corresponding one and read the FAT block and be present in this flash memory;
When if this reads the FAT block and exists, check that this reads one first new data more whether the FAT block stores this reading address; And
If this reads the FAT block and stores this first new data more, this reads the FAT block and reads this first new data more certainly.
7. the data access method of flash memory according to claim 6 is characterized in that, wherein the method more comprises:
Block does not exist if this reads FAT, if or this read the FAT block and do not store this first new data more, check that this reads target block and whether has corresponding one and read sub-block and be present in this flash memory; And
Do not exist if this reads sub-block, this reads target block and reads one second new data more that stores with this reading address certainly.
8. the data access method of flash memory according to claim 7 is characterized in that, wherein the method more comprises:
Exist if this reads sub-block, check this read sub-block whether store this reading address one the depth of the night new data;
If this reads sub-block and stores this new data depth of the night, this reads sub-block and reads this new data depth of the night certainly; And
If this reads sub-block and does not store this new data the depth of the night, this reads target block and reads this second new data more that stores with this reading address certainly.
9. the data access arrangement of a flash memory is characterized in that, comprising:
The first module receives one from a main frame and writes order, a writing address and data writing;
The second module is determined the target block that this writing address is corresponding, wherein this target block be this flash memory a plurality of blocks one of them;
Whether the 3rd module checks in this target block corresponding to a storage area of this writing address storage data;
Four module is when this storage area of this target block not yet writes this data writing during storage data this storage area of this target block;
The 5th module checks whether this target block has a corresponding sub-block and be present in this flash memory when this storage area of this target block storage data;
The 6th module checks when this sub-block exists whether this writing address is connected in a most end address of storage data in this sub-block;
The 7th module writes this sub-block with this data writing when this writing address is connected in this most end address;
The 8th module checks when this writing address is not connected in this most end address whether this target block has a corresponding FAT block and be present in this flash memory;
The 9th module writes this data writing this FAT block when this FAT block exists;
Wherein the 7th module also comprises:
The tenth module checks whether this target block has this corresponding FAT block and be present in this flash memory;
The 11 module checks whether this FAT block has stored the more new data of this writing address;
The 12 module, when this FAT block exist and this FAT block a new scheduler is corresponding to be shown for being stored in this FAT block to obtain by the corresponding list deletion of a scheduler of this FAT block with this writing address when having stored the more new data of this writing address;
The 13 module writes one of this sub-block storage area that continues with this data writing, the corresponding relation of the scheduler of the corresponding more new data that wherein stores in the original address of corresponding this target block of table record of this scheduler and this FAT block.
10. the data access arrangement of flash memory according to claim 9 is characterized in that, also comprises:
The tenth four module, when this sub-block did not exist, this flash memory was chosen a blank block as this sub-block certainly, and this data writing is write this sub-block.
11. the data access arrangement of flash memory according to claim 9 is characterized in that, also comprises:
The 15 module, when the 8th module judged that this FAT block does not exist, this flash memory was chosen a blank block as this FAT block certainly, and this data writing is write this FAT block.
12. the data access arrangement of flash memory according to claim 9 is characterized in that, also comprises:
The 16 module, when the 9th module writes this FAT block with this data writing, this data writing is write this FAT block, and the corresponding table of a scheduler write this FAT block, the corresponding relation of a scheduler of this data writing of storage in an original address that wherein should store this data writing in corresponding this target block of table record of this scheduler and this FAT block.
13. the data access arrangement of flash memory according to claim 12 is characterized in that, wherein the start address of this storage area that continues is connected in this most end address of storage data in this sub-block.
14. the data access arrangement of flash memory according to claim 9 is characterized in that, also comprises:
The 17 module, receive a reading order and a reading address from this main frame, determine that this reading address corresponding reads target block, check that this reads target block and whether has corresponding one and read the FAT block and be present in this flash memory, check when the FAT block exists that when this reads this reads one first new data more whether the FAT block stores this reading address, and store this and first more read the FAT block from this during new data and read this first new data more when this reads the FAT block.
15. the data access arrangement of flash memory according to claim 14 is characterized in that, also comprises:
The 18 module, when this reads the FAT block and does not exist, maybe when reading the FAT block, this does not store this first more during new data, check that this reads target block and whether has corresponding one and read sub-block and be present in this flash memory, and when this read sub-block and does not exist, this read target block and reads one second new data more that stores with this reading address certainly.
16. the data access arrangement of flash memory according to claim 15 is characterized in that, also comprises:
The 19 module, when this reads sub-block and exists, check this read sub-block whether store this reading address one the depth of the night new data, store this and read sub-block from this during new data the depth of the night and read this new data the depth of the night when this reads sub-block, and do not store this and read target block from this during new data the depth of the night and read this second new data more that stores with this reading address when this reads sub-block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010136426 CN102163131B (en) | 2010-02-24 | 2010-02-24 | Data access method for flash memory and flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010136426 CN102163131B (en) | 2010-02-24 | 2010-02-24 | Data access method for flash memory and flash memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102163131A CN102163131A (en) | 2011-08-24 |
| CN102163131B true CN102163131B (en) | 2013-03-06 |
Family
ID=44464380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010136426 Active CN102163131B (en) | 2010-02-24 | 2010-02-24 | Data access method for flash memory and flash memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102163131B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI697778B (en) * | 2019-06-17 | 2020-07-01 | 慧榮科技股份有限公司 | A data storage device and a data processing method |
| CN110989927B (en) * | 2019-11-11 | 2024-03-01 | 宜鼎国际股份有限公司 | Data storage device with self-access file data capability |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549133A (en) * | 2003-05-22 | 2004-11-24 | 群联电子股份有限公司 | Parallel double-track using method for quick flashing storage |
| CN1549134A (en) * | 2003-05-19 | 2004-11-24 | 群联电子股份有限公司 | Alternative execution new control method for raising processing speed of plastic fast flash storage |
| CN1617109A (en) * | 2003-11-11 | 2005-05-18 | 群联电子股份有限公司 | Linking method for establishing subarea block detection page and logic page under mother and sun structure |
| CN101030167A (en) * | 2007-01-17 | 2007-09-05 | 忆正存储技术(深圳)有限公司 | Flash-memory zone block management |
-
2010
- 2010-02-24 CN CN 201010136426 patent/CN102163131B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549134A (en) * | 2003-05-19 | 2004-11-24 | 群联电子股份有限公司 | Alternative execution new control method for raising processing speed of plastic fast flash storage |
| CN1549133A (en) * | 2003-05-22 | 2004-11-24 | 群联电子股份有限公司 | Parallel double-track using method for quick flashing storage |
| CN1617109A (en) * | 2003-11-11 | 2005-05-18 | 群联电子股份有限公司 | Linking method for establishing subarea block detection page and logic page under mother and sun structure |
| CN101030167A (en) * | 2007-01-17 | 2007-09-05 | 忆正存储技术(深圳)有限公司 | Flash-memory zone block management |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102163131A (en) | 2011-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9405675B1 (en) | System and method for managing execution of internal commands and host commands in a solid-state memory | |
| US7937523B2 (en) | Memory system with nonvolatile semiconductor memory | |
| US7461198B2 (en) | System and method for configuration and management of flash memory | |
| CN101699406B (en) | Data storage system and method | |
| CN101382918B (en) | NAND flash memory optimizing and managing method based on data interchange zone | |
| CN102063943B (en) | Nand flash memory parameter automatic detecting system | |
| EP2034414A1 (en) | Semiconductor storage device and method of controlling semiconductor storage device | |
| JP5708216B2 (en) | Flash memory device, memory control device, memory control method, and storage system | |
| CN103136108B (en) | Flash memory devices and method for reading data thereof | |
| CN103631536B (en) | A kind of method utilizing the invalid data of SSD to optimize RAID5/6 write performance | |
| US20120198131A1 (en) | Data writing method for rewritable non-volatile memory, and memory controller and memory storage apparatus using the same | |
| CN102033814B (en) | Method for accessing flash memory and relevant memory device | |
| CN101576852A (en) | Wrap-around sequence numbers for recovering from power-fall in non-volatile memory | |
| CN102999430A (en) | Handling unclean shutdowns for system having non-volatile memory | |
| CN101901189A (en) | Data updating and recovering methods for a non-volatile memory array | |
| CN101944115A (en) | Method and system for searching logs | |
| CN107608625A (en) | A kind of method for lifting solid storage device reading performance | |
| US8380920B2 (en) | Flash storage device and data access method of flash memory | |
| CN102163131B (en) | Data access method for flash memory and flash memory device | |
| CN103514101A (en) | Method for accessing flash memory and related memory device | |
| CN101446922A (en) | Memory card and method for handling data updating of a flash memory | |
| CN104240758A (en) | Data storage apparatus and management method thereof | |
| CN101894077B (en) | Data storage method and system | |
| US8209472B2 (en) | Data writing method for flash memory and control circuit and storage system using the same | |
| CN102163132B (en) | Data access method of flash memory and flash memory apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |