CN102157600A - Interdigital ultraviolet enhanced selective silicon photoelectric diode and manufacture method thereof - Google Patents
Interdigital ultraviolet enhanced selective silicon photoelectric diode and manufacture method thereof Download PDFInfo
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- CN102157600A CN102157600A CN2011100789786A CN201110078978A CN102157600A CN 102157600 A CN102157600 A CN 102157600A CN 2011100789786 A CN2011100789786 A CN 2011100789786A CN 201110078978 A CN201110078978 A CN 201110078978A CN 102157600 A CN102157600 A CN 102157600A
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Abstract
The invention discloses an interdigital ultraviolet enhanced selective silicon photoelectric diode and a manufacture method thereof. The photoelectric diode comprises a P-type substrate, wherein an n well is disposed on the P-type substrate; photosensitive windows on the n well are interdigital or in an array arrangement of interdigital structure; the doping type of the interdigital structure is n-type and p-type alternatively. In the invention, the array arrangement of the interdigital structure is used, the depletion layer area of the diode is increased, and the absorption coefficient of ultrasonic lights is improved, so that the performances of the ultrasonic silicon selective photoelectric diode in the aspects of responsiveness and quantum efficiency are greatly improved; and the diode has wide application prospects in ultrasonic detectors.
Description
Technical field
The present invention relates to a kind of photodiode, particularly a kind of interdigitated ultraviolet enhancement selective silicon photodiode and preparation method thereof.
Background technology
Through research about ten years, the ultraviolet light photo diode has been obtained tangible improvement in the performance of aspects such as responsiveness, quantum efficiency, integrated level.Wherein topmost three kinds is photoelectric emission ultraviolet light photo diode, wide band gap semiconductor ultraviolet light photo diode and p-n junction type ultraviolet light photo diode.
Photoelectric emission ultraviolet light photo diode costs an arm and a leg, volume is big and fragile, their fatiguabilities and aging, make their sensitivity reduce, they will avoid highdensity radiation, need be placed on shady place during storage, and need add very high reversed bias voltage, these shortcomings are restricted their application.
Wide band gap semiconductor, as SiC, GaN, GaP, AlN, ZnS and diamond etc., these materials are difficult to technical process, crystal mass costs an arm and a leg also not as Si, instability, and can not with the microelectronic technique compatibility.These drawbacks limit their development.
P-n junction type ultraviolet light photo diode mainly comprises striated photodiode and ultraviolet enhancement photodiode at present, because this photodiode volume is little, technical process is simple, and can with the microelectronic technique compatibility, become the main flow of present photodiode development.But because the starting of p-n junction type ultraviolet light photo diode soon, striated photodiode that proposes and the performance of ultraviolet enhancement photodiode aspect responsiveness and quantum efficiency have influenced the performance of ultraviolet detector not enough at present.
Summary of the invention
In order to solve the above-mentioned technical problem that existing photodiode exists, the invention provides interdigitated ultraviolet enhancement selective silicon photodiode of a kind of high-responsivity, high selectivity and preparation method thereof.
The technical scheme that the present invention solves the problems of the technologies described above is: comprise P type substrate, P type substrate is provided with the n trap, it is characterized in that: the photosensitive window on the n trap is an interdigitated configuration, and the doping type of interdigitated configuration is that the n type is alternate with the p type.
In the above-mentioned high speed enhancement mode ultraviolet silicon selectivity avalanche photodide, described photosensitive window is the array arrangement of a plurality of interdigitated configuration.
A kind of manufacture method of high speed enhancement mode ultraviolet silicon selectivity avalanche photodide may further comprise the steps:
1) on P type silicon substrate, injects one deck n trap;
2) inject two P on the P type silicon substrate
+Doped region;
3) inject two N at n trap edge
+Doped region;
4) on the n trap, use the interdigitated mask as lithography mask version, make the interdigitated window by lithography, carry out the boron ion and inject, annealing, the activated boron ion forms interdigitated P
+Anode;
5) at interdigitated P
+Inject the boron ion around the anode, form the p trap;
6) in the upper surface of device growth layer of oxide layer;
7) use the interdigitated mask as lithography mask version, P is fallen in photoetching
+Oxide layer on the anode;
8) method by the evaporation plating aluminium film generates one deck aluminium lamination at device surface;
9) use the interdigitated mask as lithography mask version, P is fallen in photoetching
+Aluminium lamination on the anode obtains the aluminium electrode.
In the manufacture method of above-mentioned high speed enhancement mode ultraviolet silicon selectivity avalanche photodide, make the array arrangement of a plurality of interdigitated configuration in the described step 4) of the interdigitated mask, and form interdigitated P
+The array arrangement of anode.
Technique effect of the present invention is: 1) the present invention adopts the array arrangement of interdigital structure, and the depletion layer area of photodiode increases, and the absorption coefficient of ultraviolet light is improved, and responsiveness and quantum efficiency improve.2) the adjacent P of the interdigital structure among the present invention
+Distance between the doped region is less, has reduced the diffusion time of charge carrier, has improved response speed.
The present invention is further illustrated below in conjunction with figure.
Description of drawings
Accompanying drawing 1 is the face shaping of interdigitated configuration among the present invention.
Accompanying drawing 2 is the cutaway view of single interdigitated configuration among the present invention.
Accompanying drawing 3 is the array arrangement of interdigitated configuration among the present invention.
Accompanying drawing 4 is the structure chart of preparation n trap among the present invention.
Accompanying drawing 5 is for preparing P on the p substrate among the present invention
+The structure chart of anode.
Accompanying drawing 6 is for preparing N on the n trap among the present invention
+The structure chart of negative electrode.
Accompanying drawing 7 is for preparing P on the n trap among the present invention
+The structure chart of anode.
Embodiment
Referring to Fig. 1, Fig. 1 is single interdigitated configuration P in the photosensitive area of the present invention
+Anode construction figure, the photosensitive area among Fig. 1 is by the P of mutual cross arrangement
+Doped region 101,102,103,104,105 and n trap 106 constitute interdigitated configuration P among this figure
+The interdigital number that anode comprised can comprise more or less interdigital number.
Referring to Fig. 2, inside doping situation and the CONCENTRATION DISTRIBUTION of Fig. 2 for realizing that interdigital structure photosensitive area ultraviolet strengthens and selects.It is characterized in that in P substrate 201, injecting n trap 106 and inject two P
+Doped region 202,203, wherein n trap 106 is corresponding with n trap 106 among Fig. 1; In n trap 106, inject two N
+ Doped region 204 and 205 and five P
+Doped region 101,102,103,104,105, wherein P
+P in doped region 101 corresponding diagram 1
+ Doped region 101, P
+P in doped region 102 corresponding diagram 1
+ Doped region 102, P
+P in doped region 103 corresponding diagram 1
+ Doped region 103, P
+P in doped region 104 corresponding diagram 1
+ Doped region 104, P
+P in doped region 105 corresponding diagram 1
+ Doped region 105 forms five strip pn knots; P
+Doped region 101,102 injects P trap 206 around 103,104,105, the superficial growth of structure layer of oxide layer 207.Interdigitated configuration 208 is by 101,102,103,104,105 5 P
+Doped region constitutes, and photocarrier produces the back at P
+District 101,102,103,104,105 separates the N in the n well region 106 with the pn knot place that n well region 106 contact-making surfaces form
+Electronics, P collect in district 204 and 205
+The hole is collected in district 101,102,103,104,105, and P is passed through in the hole
+Electrode in the district 101,102,103,104,105 is read, and electronics passes through N
+Electrode in the district 204,205 is read, and the pn knot that forms between n trap 106 and the p substrate 201 has promoted the recombinant of the photo-generated carrier beyond the ultraviolet wavelength, and the voltage on the p substrate passes through P
+Electrode in the district 202,203 adds.
The frame of broken lines inner structure is Fig. 1 interdigitated P among Fig. 2
+P in the cutaway view of anode, frame of broken lines
+The number of anode is by interdigitated P among Fig. 1
+The quantity decision of anode.The cutaway view of entire device and the difference of Fig. 2 only are P in the frame of broken lines
+The difference of anode quantity, entire device are interdigitated P
+The array distribution of anode construction as Fig. 2 during as the cutaway view of entire device, only need change the P in the frame of broken lines according to the quantity that interdigitated configuration repeats
+The quantity of anode number gets final product, as, when entire device is 6*6 interdigitated P
+During the array of anode, then only need be with the P in the frame of broken lines
+The anode number changes over 30 and gets final product.
Referring to Fig. 3, Fig. 3 is the array arrangement of a plurality of interdigitated configuration, interdigitated P
+The number of anode construction array is not as the criterion with the quantity in scheming, can be more or less.
The photodiode making step that comprises single interdigitated configuration among the present invention is as follows:
1. substrate is chosen.The silicon substrate of choosing among the present invention mixes for the P type, and concentration is 1e14/cm
3, thickness is 2um.
The damage that the P substrate is injected by ion.Make the window 209 at n trap place by lithography, as shown in Figure 4.Carry out phosphonium ion and inject, annealing activates phosphonium ion, forms the n trap, and thickness is 1um, and concentration is 1e16/cm
3
3.P P on the substrate
+The preparation of anode.Make P by lithography
+Carry out the boron ion behind the place window 210 and inject, form thick 0.14 ~ 1um, concentration is 1e19/cm
3P
+ Doped region 202 and 203.As shown in Figure 5.
4.n N on the trap
+The preparation of negative electrode.Make N by lithography
+Carry out phosphonium ion behind the place window 211 and inject, form thick 0.14um, concentration is 1e19/cm
3N
+ Doped region 204 and 205.As shown in Figure 6.
5.n the preparation of interdigitated anode on the trap.As lithography mask version, make interdigitated P with the interdigitated mask by lithography
+Anode 101,102,103,104,105 place windows 212 carry out the boron ion and inject, and form thick 0.14um, and concentration is 1e19/cm
3P
+Doped region 101,102,103,104,105, the P in the corresponding diagram 1 respectively
+Anode 101,102,103,104 and 105.As shown in Figure 7.The interdigitated mask can be seen Fig. 1, and 101,102,103,104 and 105 is the logical light part of mask, and 106 is the shading light part of mask.
6. electrode preparation.Method by evaporation plating Al film generates the thin aluminium lamination of one deck at device surface, makes the aluminium electrode by lithography by photoetching again.
When needs are made the photodiode of the array arrangement that contains a plurality of interdigitated configuration, adopt polylith interdigitated mask when a light requirement is carved, and adopt identical technology to make the interdigitated anode array.
Claims (4)
1. a high speed enhancement mode ultraviolet silicon selectivity avalanche photodide comprises P type substrate, and P type substrate is provided with the n trap, it is characterized in that: the photosensitive window on the n trap is an interdigitated configuration, and the doping type of interdigitated configuration is that the n type is alternate with the p type.
2. according to right 1 described high speed enhancement mode ultraviolet silicon selectivity avalanche photodide, it is characterized in that: described photosensitive window is the array arrangement of a plurality of interdigitated configuration.
3. the manufacture method of a high speed enhancement mode ultraviolet silicon selectivity avalanche photodide may further comprise the steps:
1) on P type silicon substrate, injects one deck n trap;
2) inject two P on the P type silicon substrate
+Doped region;
3) P on the close P type substrate in the n trap
+Doped region injects two N
+Doped region;
4) on the n trap, use the interdigitated mask as lithography mask version, make the interdigitated window by lithography, carry out the boron ion and inject, annealing, the activated boron ion forms interdigitated P
+Anode;
5) at interdigitated P
+Inject the boron ion around the anode, form the p trap;
6) in the upper surface of device growth layer of oxide layer;
7) use the interdigitated mask as lithography mask version, P is fallen in photoetching
+Oxide layer on the anode;
8) method by the evaporation plating aluminium film generates one deck aluminium lamination at device surface;
9) use the interdigitated mask as lithography mask version, P is fallen in photoetching
+Aluminium lamination on the anode obtains the aluminium electrode.
4. according to the manufacture method of claim 3 or 4 described high speed enhancement mode ultraviolet silicon selectivity avalanche photodides, make the array arrangement of a plurality of interdigitated configuration in the described step 4) of the interdigitated mask, and form interdigitated P
+The array arrangement of anode.
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Cited By (7)
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|---|---|---|---|---|
| CN103208555A (en) * | 2012-12-24 | 2013-07-17 | 西南技术物理研究所 | Ultraviolet selective silicon avalanche photoelectric detection chip |
| CN103606587A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Photosensitive diode |
| CN103890961A (en) * | 2011-09-02 | 2014-06-25 | 荷兰能源研究中心基金会 | Interdigitated back contact photovoltaic cell with floating front surface emitter regions |
| CN104157721A (en) * | 2014-08-08 | 2014-11-19 | 浙江大学 | Graphene/silicon/graphene-based avalanche photodetector and manufacturing method thereof |
| CN104157722A (en) * | 2014-08-18 | 2014-11-19 | 浙江大学 | Silicon-graphene avalanche photodetector |
| CN104465686A (en) * | 2014-11-20 | 2015-03-25 | 西安电子科技大学 | Infrared detector array and manufacturing method thereof |
| CN105144404A (en) * | 2013-03-15 | 2015-12-09 | Mtpv动力公司 | Method and structure for multi-cell devices without physical isolation |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103890961A (en) * | 2011-09-02 | 2014-06-25 | 荷兰能源研究中心基金会 | Interdigitated back contact photovoltaic cell with floating front surface emitter regions |
| CN103890961B (en) * | 2011-09-02 | 2016-02-10 | 荷兰能源研究中心基金会 | There is the interdigitated back contact photovoltaic cell of floating front side emitter polar region |
| CN103208555A (en) * | 2012-12-24 | 2013-07-17 | 西南技术物理研究所 | Ultraviolet selective silicon avalanche photoelectric detection chip |
| CN105144404A (en) * | 2013-03-15 | 2015-12-09 | Mtpv动力公司 | Method and structure for multi-cell devices without physical isolation |
| CN105144404B (en) * | 2013-03-15 | 2019-03-29 | Mtpv动力公司 | For being not necessarily to the method and structure of physically-isolated more battery unit devices |
| CN103606587A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | Photosensitive diode |
| CN103606587B (en) * | 2013-10-23 | 2016-06-08 | 上海华力微电子有限公司 | Photodiode |
| CN104157721A (en) * | 2014-08-08 | 2014-11-19 | 浙江大学 | Graphene/silicon/graphene-based avalanche photodetector and manufacturing method thereof |
| CN104157722A (en) * | 2014-08-18 | 2014-11-19 | 浙江大学 | Silicon-graphene avalanche photodetector |
| CN104465686A (en) * | 2014-11-20 | 2015-03-25 | 西安电子科技大学 | Infrared detector array and manufacturing method thereof |
| CN104465686B (en) * | 2014-11-20 | 2016-11-02 | 西安电子科技大学 | Infrared detector array and preparation method thereof |
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Application publication date: 20110817 |