CN102157554A - Fin type transistor structure and manufacturing method thereof - Google Patents
Fin type transistor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102157554A CN102157554A CN2010101125218A CN201010112521A CN102157554A CN 102157554 A CN102157554 A CN 102157554A CN 2010101125218 A CN2010101125218 A CN 2010101125218A CN 201010112521 A CN201010112521 A CN 201010112521A CN 102157554 A CN102157554 A CN 102157554A
- Authority
- CN
- China
- Prior art keywords
- fin
- protective layer
- semiconductor substrate
- hard mask
- etching protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 85
- 239000010410 layer Substances 0.000 claims description 74
- 239000011241 protective layer Substances 0.000 claims description 60
- 238000002360 preparation method Methods 0.000 claims description 40
- 239000000203 mixture Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 18
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000011049 filling Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 2
- 238000001020 plasma etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application discloses a fin type transistor structure and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate comprised of a bulk semiconductor material; patterning a semiconductor substrate to form a fin integral with the semiconductor substrate; patterning the fin so that a gap is formed between the other part of the fin except for the part serving as the channel region of the transistor structure and the surface of the semiconductor substrate; filling an insulator material in the gap; and manufacturing a transistor structure on the basis of the semiconductor substrate with the formed fin. According to the fin type transistor structure manufactured by the invention, the advantages of a body contact structure can be maintained, and the leakage current can be reduced.
Description
Technical field
The application's relate generally to field of semiconductor devices more specifically, relates to a kind of fin transistor structure and preparation method thereof.
Background technology
Fin transistor structure such as FinFET receive much attention owing to its good cutoff performance, extensibility and with the compatibility of conventional manufacturing process.At present, Chang Gui FinFET has two classes usually: the FinFET that forms on silicon-on-insulator (SOI) substrate, and the FinFET that forms on body Si material substrate (body FinFET).Compare with the FinFET that forms on the SOI substrate, body FinFET has numerous advantages, transmits as low-cost, low bulk effect, low reverse bias effect, high heat.
List of references 1 (Tai-su Park et al., " Body-tied triple-gate NMOSFETfabrication using bulk Si wafer ", Solid-state Electronics 49 (2005), disclose a kind of body of body Si wafer fabrication that utilizes in 377-383) to contact three grid NMOSFET.The perspective view of this FET has been shown among Fig. 1 of this article, and in Fig. 2 detailed icon make the method for this FET.Shown in wherein Fig. 1 and 2 (f), the gate electrode of polysilicon forms across fin (Fin), and Fin constitutes the raceway groove of this semiconductor device.But shown in clear among Fig. 2 (f), the raceway groove bottom is by SiN and SiO
2Institute centers on, thereby gate electrode can't effectively be controlled this part.Thereby, even under cut-off state, also can between source/leakage, form current path by the raceway groove bottom, thereby cause leakage current.
List of references 2 (K.Okano et al., " Process Integration Technology andDevice Characteristics of CMOS FinFET on Bulk Silicon Substrate withsub-10nm Fin Width and 20nm Gate Length ", IEDM 2005) in more detailed argumentation this problem.Particularly, with reference to Fig. 4 wherein, the wherein clear leakage current density that shows in the Fin different parts.Can see that in the raceway groove bottom, leakage current density is the one-tenth hundred of channel region and even thousands of times.
In order to solve this leakage problem, described in list of references 2, can introduce break-through in the raceway groove bottom and stop (PTS) structure, so that suppress leakage current.In order to form the PTS structure in the raceway groove bottom, need carry out energetic ion usually and inject.Yet this alloy that will cause injecting is injected into bigger scope, and the impurity concentration of channel region higher (referring to Fig. 5 of list of references 2).Thereby this structure will have big junction leakage and big junction capacitance.
Therefore, need a kind of structure and method of novelty to form fin transistor, it can effectively reduce the leakage current of raceway groove bottom, and can not cause high junction leakage and high junction capacitance when keeping body contact FinFET advantage.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of fin transistor structure and preparation method thereof, this fin transistor structure can also reduce leakage current in the advantage that keeps body contact structure simultaneously.
According to an aspect of the present invention, provide a kind of method of making the fin transistor structure, having comprised: the Semiconductor substrate that is made of semiconductor material body is provided; To the Semiconductor substrate composition, with the fin of formation with this Semiconductor substrate one; Described fin is carried out composition, make to be formed with the space between the surface of other positions outside the position of the channel region that is used as described transistor arrangement in the described fin and Semiconductor substrate; In described space, fill insulating material; And, make transistor arrangement based on the above-mentioned Semiconductor substrate that is formed with fin.
Preferably, described semiconductor material body can comprise Si, and described insulating material can comprise SiO
2Or SiN.
Preferably, the step that described fin is carried out composition comprises: the top surface at semiconductor substrate surface and fin forms the etching protective layer; Both sides at fin form hard mask layer; Sidewall at fin forms another etching protective layer; Described hard mask layer is carried out composition, to limit described space; Carry out etching, thereby form described space; And remove described etching protective layer, another etching protective layer and hard mask layer.
Preferably, the step that forms the etching protective layer at the top surface of semiconductor substrate surface and fin comprises: deposition one preparation etching protective layer, and this preparation etching protective layer is thicker and thinner along the sidewall direction of fin along the surface direction of Semiconductor substrate; And this preparation etching protective layer carried out etching, remove the part on the sidewall that preparation etching protective layer is positioned at fin, to form described etching protective layer.
Preferably, the step that forms hard mask layer in the both sides of fin comprises: deposition one preparation hard mask layer, and this preparation hard mask layer is thicker and thinner along the sidewall direction of fin along the surface direction of Semiconductor substrate; And this preparation hard mask layer carried out etching, the part of removing on the sidewall that the preparation hard mask layer is positioned at fin is removed, to form described hard mask layer.
Preferably, the step that forms another etching protective layer at the sidewall of fin comprises: deposit another conformal preparation etching protective layer; And this another preparation etching protective layer carried out etching, keep this another preparation etching protective layer and be positioned at part on the fin sidewall, to form described another etching protective layer.
Preferably; the step of described hard mask layer being carried out composition comprises: described hard mask layer is carried out selective etch; make this hard mask layer and the corresponding position of the gate regions of the transistor arrangement that will form keep; and remove at all the other positions; thereby expose fin and the corresponding position, described space that will form, and all the other positions of fin and semiconductor substrate surface are by described etching protective layer, another etching protective layer and hard mask layer protection.
Preferably, described etching protective layer and described another etching protective layer can comprise SiO
2, and described hard mask layer can comprise SiN.
Preferably, serve as that the step that the basis makes transistor arrangement comprises with the Semiconductor substrate that is formed with fin: form resilient coating being formed with on the substrate of fin; On resilient coating, form the barrier layer; On the barrier layer, form separator, and this separator is carried out planarization, until exposing the barrier layer; Remove the barrier layer at fin top, and remove a part of separator and make separator recessed; Etching is carried out on the barrier layer of fin both sides and a part of separator of both sides, barrier layer; The resilient coating that exposes is positioned at the corresponding position of gate regions that will form carries out etching, to expose the fin main body; On the fin main body of exposing, form gate insulator; And forming gate electrode with the corresponding position of the gate regions that will form.
According to a further aspect in the invention, provide a kind of fin transistor structure, having comprised: the Semiconductor substrate that constitutes by semiconductor material body; With the fin of Semiconductor substrate one, be used as in the described fin between the surface of other positions outside the position of channel region of described transistor arrangement and Semiconductor substrate and be formed with the space, filled insulating material in the described space.Preferably, described position as channel region is positioned under the gate regions of this fin transistor structure.
In fin transistor structure according to the present invention, channel region and Semiconductor substrate are one, thus the organizator contact structures.This has guaranteed that fin transistor structure of the present invention can keep the advantage of body contact FinFET.In addition, other positions of fin contact with substrate by insulator, thereby form the structure that is similar to SOI, and this has effectively reduced leakage current.Owing to do not use the means (needing to use highly doped) that are similar to PST in the present invention, thereby need not to worry because highly doped high junction leakage that causes and high junction capacitance.
Description of drawings
With reference to the description of accompanying drawing to the embodiment of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be more clear by following, in the accompanying drawings:
Fig. 1～7 show according to the middle junction composition in the manufacture method flow process of the embodiment of the invention, and wherein (a) is perspective view among each figure, (b) are sectional view;
Fig. 8～9 show according to the middle junction composition in the manufacture method flow process of the embodiment of the invention, and wherein (a) is perspective view among each figure, (b) are the sectional view along A-A ' line, (c) are the sectional view along B-B ' line;
Figure 10 shows the fin structure figure according to the embodiment of the invention, and wherein Figure 10 (a) is a perspective view, and Figure 10 (b) is the sectional view along A-A ' line, and Figure 10 (c) is the sectional view of B-B ' line; And
It serves as the structure chart that the basis makes each stage in the flow process of fin transistor structure according to the embodiment of the invention with above-mentioned fin structure that Figure 11～18 show, wherein (a) is perspective view among each figure, (b) be sectional view along A-A ' line, (c) be sectional view along B-B ' line, Figure 18 (d) is the sectional view along C-C ' line.
Embodiment
Below, by the specific embodiment shown in the accompanying drawing the present invention is described.But should be appreciated that these descriptions are exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, omitted description, to avoid unnecessarily obscuring notion of the present invention to known configurations and technology.
The various structure charts and the sectional view of the semiconductor device according to the embodiment of the invention shown in the drawings.These figure draw in proportion, wherein for purpose clearly, have amplified some details, and may omit some details.The shape of the various zones shown in the figure, layer and the relative size between them, position relation only are exemplary, may be because manufacturing tolerance or technical limitations and deviation to some extent in the reality, and those skilled in the art according to reality required can design in addition have difformity, the regions/layers of size, relative position.
According to embodiments of the invention, provide fin (Fin) structure of a kind of novelty and forming method thereof.This fin makes this fin and Semiconductor substrate become one by the Semiconductor substrate composition is formed, and wherein is formed with the space between the surface of all the other positions outside the channel region and Semiconductor substrate, and fills insulating material in the space.As a result, for channel region, it is positioned on the body material, thereby has the advantage as consubstantiality FinFET; And for all the other positions, then be positioned on the insulator, as the FinFET that is formed on the SOI substrate, can reduce leakage current greatly.
Fig. 1～7 show according to the middle junction composition in the manufacture method flow process of the embodiment of the invention, and wherein (a) is perspective view among each figure, (b) are sectional view.
As shown in Figure 1, at first provide the Semiconductor substrate of making by semiconductor material body 1001.For example, Semiconductor substrate 1001 can comprise body Si.Certainly, those skilled in the art also can expect for example body Ge etc. of other different materials.
Then, as shown in Figure 2, Semiconductor substrate 1001 is carried out composition, for example, on Semiconductor substrate 1001, form the Fin of one with it by technological means such as mask exposure, etchings.
In order to realize that all the other positions outside the channel region among this Fin contact with insulator between the Semiconductor substrate, need carry out composition to Fin as shown in Figure 2, between described all the other positions and Semiconductor substrate, to form the space, contact thereby can form insulator by filling insulating material in this space.
For this reason; shown in Fig. 3 and 4; at first form the etching protective layer on the surface of Semiconductor substrate 1001 and the top surface of formed Fin, so that subsequently when forming the space by etching, the surface of protection Semiconductor substrate 1001 and the top of Fin are unaffected.Particularly, as shown in Figure 3, deposition one is prepared etching protective layer 1002 on the surface of Semiconductor substrate 1001 earlier.For example, this preparation etching protective layer 1002 comprises SiO
2Can comprise in this said " deposition " and the mode of various deposition materials for example to include but not limited to CVD (chemical vapour deposition (CVD)), molecular beam epitaxy (MBE), evaporation etc.The depositional mode of this layer makes preparation etching protective layer 1002, and sidewall direction Fin is thin along the surface direction of Semiconductor substrate 1001 is thick.Subsequently, as shown in Figure 4, for example by preparation etching protective layer 1002 is carried out etching, as reactive ion etching (RIE), the reduced thickness of feasible preparation etching protective layer 1002.Because preparation etching protective layer 1002 is thin and thick along the surface direction of Semiconductor substrate along the sidewall direction of Fin; therefore through after the certain hour; preparation etching protective layer 1002 is only stayed the surface of Semiconductor substrate 1001 and the top of Fin; and be not present on the sidewall of Fin, thereby finally form etching protective layer 1002 shown in Figure 4 '.
Then, form a hard mask layer, so that limit space to be formed subsequently in the both sides of Fin.Particularly, as shown in Figure 5, at first deposition one is prepared hard mask layer 1003 on structure shown in Figure 4.For example, this preparation hard mask layer 1003 for example comprises SiN.In addition, the depositional mode of depositional mode of this layer and above-mentioned preparation etching protective layer 1002 is similar, makes preparation hard mask layer 1003 thin and thick along the surface direction of Semiconductor substrate along the sidewall direction of Fin.Subsequently, as shown in Figure 6, for example by preparation hard mask layer 1003 being carried out etching such as RIE, the reduced thickness of feasible preparation hard mask layer 1003.Because preparation hard mask layer 1003 is thin and thick along the surface direction of Semiconductor substrate along the sidewall of Fin, therefore through after the certain hour, preparation hard mask layer 1003 is only stayed the both sides of Fin on the semiconductor substrate surface, and be not present on the sidewall of Fin, thereby finally obtain hard mask layer shown in Figure 6 1003 '.The hard mask layer 1003 that the Fin both sides stay ' thickness roughly corresponding to the height in the space that will form.Although it is pointed out that here the top that some hard mask layers 1003 remains in Fin has been shown among Fig. 6, this residual fraction does not have materially affect for processing subsequently, if technology allows, it can be removed.
Then, as shown in Figure 7, the side-walls that exposes at Fin further forms another etching protective layer 1004, and is unaffected in the interstitial process of etching subsequently with the sidewall of protection Fin.For example, this etching protective layer 1004 can comprise SiO
2Particularly, for example at first on structure shown in Figure 6, deposit another preparation etching protective layer (SiO of conformal (conformal)
2), by this another preparation etching protective layer is carried out etching such as RIE, make its sidewall of only staying Fin then, form etching protective layer 1004 as shown in Figure 6.
Then, need carry out composition, so that limit space to be formed to hard mask layer.
Fig. 8～9 show according to the middle junction composition in the manufacture method flow process of the embodiment of the invention, wherein (a) is perspective view among each figure, (b) be sectional view along A-A ' line, (c) be (for the sake of clarity along the sectional view of B-B ' line, A-A ' line, B-B ' line are not shown among Fig. 9, they are same as shown in Figure 8, below each figure all similar).
As shown in Figure 8; for example; can be by modes such as photoetching; to hard mask layer 1003 ' carry out composition; make its corresponding position of gate regions of only staying and will forming (as among the figure 1003 " shown in); thus expose among the Fin and corresponding position, space to be formed (referring to Fig. 8 (a), 8 (c)), and the remainder of Fin and semiconductor substrate surface be etched protective layer 1002 ', 1004 and hard mask layer 1003 " cover (referring to Fig. 8 (a), 8 (b)).Particularly, for example, deposition one deck photoresist exposes by mask then and develops, and makes photoresist only stay the position corresponding with the gate regions that will form.Then, utilize hard mask layer 1003 ' (as SiN) and etching protective layer (as SiO
2) have the etching agent of selective etch effect, carry out etching.Like this, just removed the hard mask layer 1003 ' (SiN) at all the other positions outside the gate regions, and etching protective layer (SiO
2) unaffected.Subsequently, remove photoresist, thereby finally obtain the hard mask layer 1003 behind as shown in Figure 8 the composition ".
Then, as shown in Figure 9, the structure shown in Fig. 8 is carried out selective etch, makes the position of coming out among the Fin be removed, thereby form described space (referring to Fig. 9 (c)), the height in this space for example about 50 to
Scope in.Particularly, for example utilize that " (as SiN), etching protective layer are (as SiO with hard mask layer 1003 to backing material (as Si)
2) material has the etching agent of selective etch effect, carries out etching.Like this, being exposed to outer Fin position (Si) is removed.And because etching protective layer 1002 ', 1004 and hard mask layer 1003 " existence, Semiconductor substrate that they are protected and Fin can not be subjected to the influence (referring to Fig. 9 (b)) of etching.
In fact, more than with reference to described these operations of Fig. 3～Fig. 9, its purpose is Fin is patterned into the shape (referring to Figure 10) of similar T, forms the space thereby serve as in Fin between other positions outside the position of channel region and the substrate surface.Those of ordinary skills it is contemplated that various mode is provided with etching protective layer, mask layer, etching mode etc., the Fin of this to form " T " shape.
Subsequently, for example, by selective etch, remove etching protective layer 1002 ', 1004 and hard mask layer 1003 ", and in the space, fill insulating material 1005.For example, insulating material 1005 can comprise SiO
2Or SiN.Fill and for example can finish in the following way: deposit insulating material earlier, utilize RIE to eat-back then.
Figure 10 shows the fin structure figure that finally obtains according to the embodiment of the invention, and wherein Figure 10 (a) is a perspective view, and Figure 10 (b) is the sectional view along A-A ' line, and Figure 10 (c) is the sectional view of B-B ' line.
As shown in figure 10, in this Fin structure, in fact Fin is one with Semiconductor substrate 1001.Particularly, among this Fin with the corresponding position of channel region and the Semiconductor substrate 1001 that will form be connected as a single entity (referring to Figure 10 (b)).That is, formed the body contact at channel region.In addition,, inserted insulating material 1005 (referring to Figure 10 (c)) between Fin and the Semiconductor substrate 1001, thereby formed the structure of similar SOI at other positions.
Described above is an embodiment who forms according to Fin of the present invention.Those of ordinary skills can design additive method and form this Fin.
After on substrate, having formed Fin as mentioned above, can there be multiple mode then to form various fin transistor structures.Below, only with wherein a kind of be that example describes so that those skilled in the art can understand the present invention better.
It serves as the structure chart that the basis makes each stage in the flow process of fin transistor structure according to the embodiment of the invention with above-mentioned fin structure that Figure 11～18 show, wherein (a) is perspective view among each figure, (b) be sectional view, (c) be the sectional view of B-B ' line along A-A ' line.
As shown in figure 11, on the substrate that is formed with Fin shown in Figure 10, form (for example, deposition) resilient coating 1006.This resilient coating 1006 for example can be by SiO
2Material forms.Afterwards, as shown in figure 12, on resilient coating 1006, continue to form (for example, deposition) barrier layer 1007.This barrier layer 1007 for example can be formed by the SiN material.Then, as shown in figure 13, layer deposited isolating 1008 on resulting structure.This separator 1008 for example can be by SiO
2Form.Preferably, the separator 1008 that deposits is carried out planarization such as CMP (chemico-mechanical polishing), until exposing barrier layer 1007.
Subsequently, as shown in figure 14, selective etch is carried out on the barrier layer 1007 that is positioned at the Fin top, remove this a part of barrier layer 1007.In addition, removing a part of separator 1008 makes separator 1008 recessed.Then, as shown in figure 15, the barrier layer 1007 and the part separator 1008 of further etching Fin both sides are to expose Fin more.Subsequently, as shown in figure 16, with the corresponding position of the gate regions that will form, etch away resilient coating 1006, to expose Fin main body (corresponding to channel region).
Then, as shown in figure 17, on the Fin main body of exposing, form gate insulator 1009.This gate insulator 1009 for example can be by SiO
2, SiON or high k material form.Then, as shown in figure 18, form gate electrode 1010.This gate electrode 1010 intersects by gate insulator 1009 and Fin main body across Fin.Gate electrode 1010 can be polygate electrodes, perhaps can be metal gate electrode such as TiN, TiAlN, TaN etc.
After forming gate electrode, can be by ion injection etc. to mixing source/drain region, thus the final transistor arrangement that forms according to the embodiment of the invention.It is too big related that this provenance/drain region and purport of the present invention there is no, and do not repeat them here.
The transistor arrangement that finally the obtains sectional view along C-C ' line has been shown among Figure 18 (d).Can be clear that the position (corresponding to channel region) that Fin is positioned under the gate electrode 1010 is one (that is organizator contact) with Semiconductor substrate 1001.It is surrounded by insulator 1005 on every side, thereby can cut off the path of leakage current, and has therefore reduced the leakage current of channel region bottom greatly.
Although be that example describes with the transistor arrangement shown in Figure 18 among the above embodiment, but those skilled in the art will be appreciated that, based on fin structure according to the present invention, can produce multiple fin transistor structure, as double grid FinFET, three gate FinFETs etc., and be not limited only to the structure shown in Figure 18.
In above description, do not make detailed explanation for ins and outs such as the composition of each layer, etchings.Can be but it will be appreciated by those skilled in the art that by various means of the prior art, form layer, zone of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of method described above.
Abovely the present invention has been given explanation with reference to embodiments of the invention.But these embodiment only are for illustrative purposes, and are not in order to limit the scope of the invention.Scope of the present invention is limited by claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (12)
1. method of making the fin transistor structure comprises:
The Semiconductor substrate that is made of semiconductor material body is provided;
To the Semiconductor substrate composition, with the fin of formation with this Semiconductor substrate one;
Described fin is carried out composition, make to be formed with the space between the surface of other positions outside the position of the channel region that is used as described transistor arrangement in the described fin and Semiconductor substrate;
In described space, fill insulating material; And
Based on the above-mentioned Semiconductor substrate that is formed with fin, make transistor arrangement.
2. the method for claim 1, wherein described semiconductor material body comprises Si.
3. the method for claim 1, wherein described insulating material comprises SiO
2Or SiN.
4. the step of the method for claim 1, wherein described fin being carried out composition comprises:
Top surface at semiconductor substrate surface and fin forms the etching protective layer;
Both sides at fin form hard mask layer;
Sidewall at fin forms another etching protective layer;
Described hard mask layer is carried out composition, to limit described space;
Carry out etching, thereby form described space; And
Remove described etching protective layer, another etching protective layer and hard mask layer.
5. method as claimed in claim 4, wherein, the step that forms the etching protective layer at the top surface of semiconductor substrate surface and fin comprises:
Deposition one preparation etching protective layer, this preparation etching protective layer is thicker and thinner along the sidewall direction of fin along the surface direction of Semiconductor substrate; And
This preparation etching protective layer is carried out etching, remove the part on the sidewall that preparation etching protective layer is positioned at fin, to form described etching protective layer.
6. method as claimed in claim 4, wherein, the step that forms hard mask layer in the both sides of fin comprises:
Deposition one preparation hard mask layer, this preparation hard mask layer is thicker and thinner along the sidewall direction of fin along the surface direction of Semiconductor substrate; And
This preparation hard mask layer is carried out etching, and the part of removing on the sidewall that the preparation hard mask layer is positioned at fin is removed, to form described hard mask layer.
7. method as claimed in claim 4, wherein, the step that forms another etching protective layer at the sidewall of fin comprises:
Deposit another conformal preparation etching protective layer; And
This another preparation etching protective layer is carried out etching, keep this another preparation etching protective layer and be positioned at part on the fin sidewall, to form described another etching protective layer.
8. method as claimed in claim 4, wherein, the step of described hard mask layer being carried out composition comprises:
Described hard mask layer is carried out selective etch; make this hard mask layer and the corresponding position of the gate regions of the transistor arrangement that will form keep; and remove at all the other positions; thereby expose fin and the corresponding position, described space that will form, and all the other positions of fin and semiconductor substrate surface are by described etching protective layer, another etching protective layer and hard mask layer protection.
9. method as claimed in claim 4, wherein, described etching protective layer and described another etching protective layer comprise SiO
2
10. method as claimed in claim 9, wherein, described hard mask layer comprises SiN.
11. method as claimed in claim 9 wherein, serves as that basic step of making transistor arrangement comprises with the Semiconductor substrate that is formed with fin:
Form resilient coating being formed with on the substrate of fin;
On resilient coating, form the barrier layer;
On the barrier layer, form separator, and this separator is carried out planarization, until exposing the barrier layer;
Remove the barrier layer at fin top, and remove a part of separator and make separator recessed;
Etching is carried out on the barrier layer of fin both sides and a part of separator of both sides, barrier layer;
The resilient coating that exposes is positioned at the corresponding position of gate regions that will form carries out etching, to expose the fin main body;
On the fin main body of exposing, form gate insulator; And
Forming gate electrode with the corresponding position of the gate regions that will form.
12. a fin transistor structure comprises:
The Semiconductor substrate that constitutes by semiconductor material body;
With the fin of Semiconductor substrate one, be used as in the described fin between the surface of other positions outside the position of channel region of described transistor arrangement and Semiconductor substrate and be formed with the space, filled insulating material in the described space.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101125218A CN102157554A (en) | 2010-02-12 | 2010-02-12 | Fin type transistor structure and manufacturing method thereof |
| PCT/CN2010/001447 WO2011097782A1 (en) | 2010-02-12 | 2010-09-20 | Fin-type transistor structure and manufacturing method thereof |
| US13/077,858 US8441050B2 (en) | 2010-02-12 | 2011-03-31 | Fin transistor structure and method of fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101125218A CN102157554A (en) | 2010-02-12 | 2010-02-12 | Fin type transistor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102157554A true CN102157554A (en) | 2011-08-17 |
Family
ID=44367135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101125218A Pending CN102157554A (en) | 2010-02-12 | 2010-02-12 | Fin type transistor structure and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8441050B2 (en) |
| CN (1) | CN102157554A (en) |
| WO (1) | WO2011097782A1 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021854A (en) * | 2011-09-28 | 2013-04-03 | 中国科学院微电子研究所 | Method for manufacturing fin field effect transistor and semiconductor structure formed by method |
| CN103594513A (en) * | 2012-08-16 | 2014-02-19 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| WO2014071659A1 (en) * | 2012-11-09 | 2014-05-15 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| CN103855093A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| WO2014110853A1 (en) * | 2013-01-15 | 2014-07-24 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US9478660B2 (en) | 2015-01-12 | 2016-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Protection layer on fin of fin field effect transistor (FinFET) device structure |
| TWI601211B (en) * | 2015-10-30 | 2017-10-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and manufacturing method thereof |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8624326B2 (en) * | 2011-10-20 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
| US8809178B2 (en) | 2012-02-29 | 2014-08-19 | Globalfoundries Inc. | Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents |
| US8785284B1 (en) | 2013-02-20 | 2014-07-22 | International Business Machines Corporation | FinFETs and fin isolation structures |
| US9620642B2 (en) * | 2013-12-11 | 2017-04-11 | Globalfoundries Singapore Pte. Ltd. | FinFET with isolation |
| US9093478B1 (en) | 2014-04-11 | 2015-07-28 | International Business Machines Corporation | Integrated circuit structure with bulk silicon FinFET and methods of forming |
| US9548358B2 (en) | 2014-05-19 | 2017-01-17 | International Business Machines Corporation | Dual fill silicon-on-nothing field effect transistor |
| CN105336614B (en) * | 2014-07-02 | 2019-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
| US9515180B2 (en) * | 2014-12-31 | 2016-12-06 | Stmicroelectronics, Inc. | Vertical slit transistor with optimized AC performance |
| US9847388B2 (en) | 2015-09-01 | 2017-12-19 | International Business Machines Corporation | High thermal budget compatible punch through stop integration using doped glass |
| US10177143B2 (en) * | 2015-10-28 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company Limited | FinFET device and method for fabricating the same |
| CN105552126A (en) * | 2015-12-15 | 2016-05-04 | 上海集成电路研发中心有限公司 | Finned-type field effect transistor and fabrication method thereof |
| US9786505B2 (en) * | 2015-12-30 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device using dummy fins for smooth profiling |
| CN108695382B (en) * | 2017-04-07 | 2021-07-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
| US10147787B1 (en) * | 2017-05-31 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
| US10699912B2 (en) | 2018-10-12 | 2020-06-30 | International Business Machines Corporation | Damage free hardmask strip |
| CN112635560B (en) * | 2019-10-08 | 2023-12-05 | 联华电子股份有限公司 | Fin-shaped transistor structure and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100626372B1 (en) * | 2004-04-09 | 2006-09-20 | 삼성전자주식회사 | Semiconductor devices having a field effect transistor and methods of fabricating the same |
| US7018876B2 (en) * | 2004-06-18 | 2006-03-28 | Freescale Semiconductor, Inc. | Transistor with vertical dielectric structure |
| KR100663366B1 (en) * | 2005-10-26 | 2007-01-02 | 삼성전자주식회사 | Method of fabricating flash memory devices having self-aligned floating gate and related device |
| US7422960B2 (en) * | 2006-05-17 | 2008-09-09 | Micron Technology, Inc. | Method of forming gate arrays on a partial SOI substrate |
| US7646071B2 (en) * | 2006-05-31 | 2010-01-12 | Intel Corporation | Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory |
| US7521775B2 (en) * | 2006-06-13 | 2009-04-21 | Intel Corporation | Protection of three dimensional transistor structures during gate stack etch |
| US7517764B2 (en) * | 2006-06-29 | 2009-04-14 | International Business Machines Corporation | Bulk FinFET device |
| US7939889B2 (en) * | 2007-10-16 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistance in source and drain regions of FinFETs |
-
2010
- 2010-02-12 CN CN2010101125218A patent/CN102157554A/en active Pending
- 2010-09-20 WO PCT/CN2010/001447 patent/WO2011097782A1/en active Application Filing
-
2011
- 2011-03-31 US US13/077,858 patent/US8441050B2/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
Non-Patent Citations (1)
| Title |
|---|
| TAI-SU PARK ET AL.: "Body-tied triple-gate NMOSFET fabrication using bulk Si wafer", 《SOLID-STATE ELECTRONICS》 * |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021854A (en) * | 2011-09-28 | 2013-04-03 | 中国科学院微电子研究所 | Method for manufacturing fin field effect transistor and semiconductor structure formed by method |
| WO2013044430A1 (en) * | 2011-09-28 | 2013-04-04 | 中国科学院微电子研究所 | Method for manufacturing a fin field effect transistor and the semiconductor structure formed thereby |
| CN103021854B (en) * | 2011-09-28 | 2015-09-16 | 中国科学院微电子研究所 | Method for manufacturing fin field effect transistor and semiconductor structure formed by method |
| CN103594513A (en) * | 2012-08-16 | 2014-02-19 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| WO2014071659A1 (en) * | 2012-11-09 | 2014-05-15 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| CN103811345A (en) * | 2012-11-09 | 2014-05-21 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| US9564434B2 (en) | 2012-11-09 | 2017-02-07 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device with body spacer at the bottom of the fin and method for manufacturing the same |
| CN103811345B (en) * | 2012-11-09 | 2016-08-03 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103855093B (en) * | 2012-11-30 | 2016-07-06 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103855093A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| WO2014110853A1 (en) * | 2013-01-15 | 2014-07-24 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103928333B (en) * | 2013-01-15 | 2019-03-12 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| US9478660B2 (en) | 2015-01-12 | 2016-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Protection layer on fin of fin field effect transistor (FinFET) device structure |
| US9985133B2 (en) | 2015-01-12 | 2018-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Protection layer on fin of fin field effect transistor (FinFET) device structure |
| TWI601211B (en) * | 2015-10-30 | 2017-10-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and manufacturing method thereof |
| US10153280B2 (en) | 2015-10-30 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for FinFET |
| US10418363B2 (en) | 2015-10-30 | 2019-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for FinFET |
| US10854605B2 (en) | 2015-10-30 | 2020-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for FinFET |
| US11569236B2 (en) | 2015-10-30 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for FinFET |
Also Published As
| Publication number | Publication date |
|---|---|
| US20110198676A1 (en) | 2011-08-18 |
| US8441050B2 (en) | 2013-05-14 |
| WO2011097782A1 (en) | 2011-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102157554A (en) | Fin type transistor structure and manufacturing method thereof | |
| CN102104069B (en) | Fin type transistor structure and manufacturing method thereof | |
| CN102117829B (en) | Fin type transistor structure and manufacturing method thereof | |
| US11699701B2 (en) | Semiconductor device | |
| CN103855215B (en) | FINFET device with isolated channel | |
| US9093376B2 (en) | Replacement metal gate FinFET | |
| US9773871B2 (en) | Fin field effect transistor and method for fabricating the same | |
| US9627382B2 (en) | CMOS NFET and PFET comparable spacer width | |
| US20170077222A1 (en) | Semiconductor device and manufacturing method thereof | |
| US9954081B2 (en) | Fin field effect transistor, semiconductor device and fabricating method thereof | |
| US9202894B1 (en) | Methods for forming semiconductor fin support structures | |
| KR20100105779A (en) | Planar substrate devices integrated with finfets and method of manufacture | |
| KR20140057626A (en) | Non-planar transistors and methods of fabrication thereof | |
| CN107424934A (en) | Fin formula field effect transistor（FINFET）In source/drain regions and forming method thereof | |
| US20180301381A1 (en) | Method and structure for forming vertical transistors with shared gates and separate gates | |
| US9722024B1 (en) | Formation of semiconductor structures employing selective removal of fins | |
| US10269944B2 (en) | Fin semiconductor device and method of manufacture with source/drain regions having opposite conductivities | |
| US10937685B2 (en) | Diffusion break structures in semiconductor devices | |
| US10262998B2 (en) | Semiconductor device and method of manufacturing the same | |
| US9711567B2 (en) | Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location | |
| CN108074974B (en) | Method for forming semiconductor device | |
| US20240120338A1 (en) | Semiconductor device structure and method for forming the same | |
| JP5715037B2 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110817 |