CN102156668A - Real-time data memory method adopting built-in FLASH program memory of singlechip - Google Patents
Real-time data memory method adopting built-in FLASH program memory of singlechip Download PDFInfo
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- CN102156668A CN102156668A CN2011100936319A CN201110093631A CN102156668A CN 102156668 A CN102156668 A CN 102156668A CN 2011100936319 A CN2011100936319 A CN 2011100936319A CN 201110093631 A CN201110093631 A CN 201110093631A CN 102156668 A CN102156668 A CN 102156668A
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Abstract
The invention discloses a real-time data memory method adopting a built-in FLASH program memory of a singlechip. A device for the method comprises an FLASH type singlechip, a power supply and input/output equipment, wherein the built-in FLASH program memory of the FLASH type singlechip performs data write operations in segments. In the invention, data is directly written in the built-in FLASH program memory of the singlechip; the data memory method is performed in real time; the data corresponding to memory requests sent by the input/output equipment can be immediately memorized in the FLASH program memory of the singlechip; and the write operations are performed in segments, thus, the write times of the memory is greatly prolonged.
Description
[technical field]
The present invention relates to a kind of data accumulating method, relate in particular to and utilize single-chip microcomputer built-in FLASH program memory to carry out the method for real time data memory.
[background technology]
Generally used memory function in the current household appliances, promptly the operation related data also can be stored among the ROM after the power down.The memory function of using in the existing goods mostly connects external dedicated memory IC (EEPROM etc.) by single-chip data I/O mouth and realizes.The shortcoming of this method is: taken single-chip processor i/o mouth resource on the one hand, increased the cost of memory external IC on the other hand.
At above-mentioned deficiency, publication number is the date storage method that the Chinese patent application file of CN101645014A has proposed to utilize single-chip microcomputer built-in FLASH program memory simulation EEPROM, but this method still need be remembered IC (eeprom etc.) by external dedicated when realizing memory function; Single-chip microcomputer built-in FLASH program memory is stored and is not real-time, just can carry out during power down; Single-chip microcomputer built-in FLASH program memory stores that to write indegree limited; Single-chip microcomputer built-in FLASH program memory is stored in write time length, the memory can't carry out other operations.
[summary of the invention]
Purpose of the present invention solves the problems of the prior art exactly, a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory is proposed, can prolong the indegree of writing of storer, still can be in the data accumulating process by Interrupt Process and other irrelevant operations of memory, and the memory request can be remembered single-chip microcomputer FLASH storage area at once.
For achieving the above object, the present invention proposes a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory, be made of FLASH type single-chip microcomputer, power supply, input-output device, data write operation is carried out in the built-in FLASH program memory segmentation of described FLASH type single-chip microcomputer.
As preferably, every segment data that segmentation writes the built-in FLASH program memory all comprises header and tail information, and header is represented the number of data segment, the legitimacy of tail information representation data.
As preferably, described FLASH type single-chip microcomputer just carries out addressing and the transmission before data write when start, thereby has realized the significantly shortening of writing time, has adapted to the commodity that real-time is had relatively high expectations.
As preferably, data write in the process of built-in FLASH program memory, can overcome the shortcoming that can't carry out other operations in the prior art memory by Interrupt Process and the irrelevant operation of memory.
As preferably, data write operation is disposable to be finished.
As preferably, data write operation is divided and is finished for several times, adopts the polling mode segmentation to carry out, and under the situation that whole ablation process does not finish, if there is new memory request to produce, new memory request will be delayed processing after also will being sorted automatically, and can not omitted.
Beneficial effect of the present invention: the present invention is with the write direct built-in FLASH program memory of single-chip microcomputer of data, this data accumulating method is real-time, ask pairing data by the memory that input-output device sends, can be remembered the FLASH memory under program of single-chip microcomputer at once, and write operation is that segmentation is carried out, thereby has prolonged the indegree of writing of storer greatly.
Feature of the present invention and advantage will be elaborated in conjunction with the accompanying drawings by embodiment.
[description of drawings]
Fig. 1 is the related hardware configuration synoptic diagram of the inventive method.
Fig. 2 is the control block diagram of fragmented storage.
Fig. 3 is a control flow chart of the present invention.
Fig. 4 is the control block diagram that data are read.
Fig. 5 is the control block diagram that data write.
Fig. 6 is the control block diagram that data transmit.
Fig. 7 is the control flow chart that data write.
[embodiment]
Utilize single-chip microcomputer built-in FLASH program memory to carry out the method for real time data memory, as shown in Figure 1, hardware components is made of FLASH type single-chip microcomputer 1, power supply 2, input-output device 3, and data write operation is carried out in the built-in FLASH program memory segmentation of described FLASH type single-chip microcomputer 1.Every segment data that segmentation writes the built-in FLASH program memory all comprises header and tail information, and header is represented the number of data segment, the legitimacy of tail information representation data.Described FLASH type single-chip microcomputer 1 just carries out addressing and the transmission before data write when start, thereby has realized the significantly shortening of writing time, has adapted to the commodity that real-time is had relatively high expectations.Data write in the process of built-in FLASH program memory, can overcome the shortcoming that can't carry out other operations in the prior art memory by Interrupt Process and the irrelevant operation of memory.Data write operation can disposablely be finished or divide and be finished for several times, adopt the polling mode segmentation to carry out, under the situation that whole ablation process does not finish, if there is new memory request to produce, new memory request will be delayed processing after also will being sorted automatically, and can not omitted.
The erasable number of times of external dedicated memory IC (eeprom) is generally 100,000 times.And the general erasable number of times of single-chip microcomputer built-in FLASH program memory is 1000 times, and the present invention adopts that segmentation writes, the method for bulk erase, makes general the writing indegree and can reach more than 100,000 times of single-chip microcomputer built-in FLASH program memory.Example: write-once 11byte is as a unit, and the storage space of 8Kb can write 73.4 ten thousand times.The present invention is divided into 1 to a plurality of zones according to the big young pathbreaker's single-chip microcomputer of single-chip microcomputer built-in FLASH program memory capacity built-in FLASH program memory, and each zone is called a sector (as Fig. 2).Identify in the first address of sector store status by software, be called the head of sector current sector.Head is divided in the use, writes full, blank and other incorrect these four kinds of situations of head.Write fashionable data and be divided in together and write simultaneously, be called a Packet (as Fig. 2) several byte.The leading address of Packet is used to identify the number of current data group, and the tail address is used to identify the store status of current data group.If cut off the power supply in writing, in the tail address, will can not do and normally write the sign that finishes.Therefore these group data will can not be used.Thereby guaranteed the correctness of data.
The present invention has realized the shortening of write time by the optimal design to ablation process.Ablation process is achieved in that at first will write code is sent to RAM by the ROM of single-chip microcomputer, is called code and transmits.Search out then and write address (content is empty address), be called addressing.Carry out writing from RAM again to ROM.The present invention handles when transport process and addressing process are placed on start.Can directly write data in the program run in the address that searches out.Thereby realized that the write time is less than 1/300 of outside EEPROM writing time.It is 1/30 of the common single-chip microcomputer built-in FLASH program memory write time.
Ablation process involved in the present invention can disposablely be finished, and also can adopt the polling mode segmentation to finish.As shown in Figure 7, when adopting the polling mode segmentation to finish, under the situation that whole ablation process does not finish, if there is new memory request to produce, new memory request is delayed processing after also will being sorted automatically, and can not omitted.
Accumulating method involved in the present invention can be remembered other programs in addition by Interrupt Process in memory, thereby has guaranteed the normal execution of other programs in the memory.
Control flow chart of the present invention is as shown in Figure 3: when single-chip microcomputer powers on, at first will carry out erasable program code and copy to RAM (SC3-00) from the ROM of single-chip microcomputer.Next in RAM, carry out the setting (SC3-01) of interrupt vector table.Next be addressing process (SC3-02), comprise and read addressing and write addressing.
The flow process that data are read addressing is as shown in Figure 4:
1. shown in the A among Fig. 4, the head of each sector detects, and finds the sector in the use.
2. the up-to-date data that write of sector (data of the address maximum of identical packet head) are read in using.B place among Fig. 4 is the zone (packet head:0xff) that does not write, and does not read.C place among Fig. 4 does not write the occasion (packet foot:0xff) that finishes, and does not read.D place among Fig. 4 is that the data number is not wanted the data number (packet head:0x01) of reading, and does not read.E place among Fig. 4 is a correct data, reads.F place among Fig. 4 is not the up-to-date data that write, and does not read.
The flow process of data write addressing is as shown in Figure 5:
1. shown in A among Fig. 5, the head of each sector detects, and sector specifies in the use.
2. shown in B among Fig. 5, the next address of sector latest data is read in the use.Content is empty in the previous address, does not read.Be regular address shown in the C among Fig. 5, read.
Addressing is data readout (SC3-03) after finishing.If addressing failure or read failure, program will be composed default parameter value to each variable.
The processing (SC3-04) that the laggard product of doing business of starting shooting are common.If detect the request of writing this moment, writing request flag will set.In (SC3-06), judge whether in single-chip microcomputer built-in FLASH storage space, to write (example: the memory interval is write not allow to write, do not have when full when the request flag of writing is set and do not write).
Write processing procedure as shown in Figure 7, at first will write the request assignment under the originate mode and give write command (SC7-00) writing, write request zero clearing (SC7-01) then,, also can not omitted if in ensuing ablation process, produce the new request that writes like this.Next forward [writing middle pattern] to (SC7-02).Carry out write (SC7-03) of single packet [writing middle pattern].Writing of single packet is to carry out the process that ROM is rewritten from RAM, if interrupt in this process, program can be carried out the response to interrupting in RAM.If write success then current packet write command zero clearing (SC7-04), if all zero clearings then the pattern that writes resets to [writing originate mode] of packet write command.If write,, otherwise forward the processing that [writing Failure Mode] writes failure to if write full then forward [transfer mode] to as unsuccessful then to judge whether current sector writes full.
[transfer mode] (SC7-06) is meant in the ablation process that memory interval (sector) writes when full, writes will remember latest data before full sector wipes and be sent on the new sector by old sector.This process is also handled in (SC3-06).
The flow process that data transmit is as shown in Figure 6:
1. shown in the A among Fig. 6, the head of each sector detects, and sector finds out in the use.
2. shown in the B among Fig. 6, sector does not have the space to write again in the use.
3. shown in the C among Fig. 6, each packet latest data is sent on the empty sector.
4. shown in the D among Fig. 6, after total data transmitted and finishes, sector head in the use (0xAA, 0xFF) made.Shown in the E among Fig. 6, old sector head becomes (0xAA, 0xAA).
5. shown in the F among Fig. 6, carry out writing of NO.2 data on the new sector.At last, shown in the G among Fig. 6, old sector wipes (all becoming 0xFF).
The foregoing description is to explanation of the present invention, is not limitation of the invention, any scheme after the simple transformation of the present invention is all belonged to protection scope of the present invention.
Claims (6)
1. one kind is utilized single-chip microcomputer built-in FLASH program memory to carry out the method that real time data is remembered, it is characterized in that: be made of FLASH type single-chip microcomputer, power supply, input-output device, data write operation is carried out in the built-in FLASH program memory segmentation of described FLASH type single-chip microcomputer.
2. a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory as claimed in claim 1, it is characterized in that: every segment data that segmentation writes the built-in FLASH program memory all comprises header and tail information, header is represented the number of data segment, the legitimacy of tail information representation data.
3. a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory as claimed in claim 1 is characterized in that: described FLASH type single-chip microcomputer just carries out addressing and the transmission before data write when start.
4. a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory as claimed in claim 1, it is characterized in that: data write in the process of built-in FLASH program memory, can be by Interrupt Process and the irrelevant operation of memory.
5. a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory as claimed in claim 1, it is characterized in that: data write operation is disposable to be finished.
6. a kind of method of utilizing single-chip microcomputer built-in FLASH program memory to carry out the real time data memory as claimed in claim 1, it is characterized in that: data write operation divides several to finish, adopt the polling mode segmentation to carry out, under the situation that whole ablation process does not finish, if there is new memory request to produce, new memory request will be delayed processing after also will being sorted automatically, and can not omitted.
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| CN201110093631.9A CN102156668B (en) | 2011-04-14 | 2011-04-14 | Real-time data memory method adopting built-in FLASH program memory of singlechip |
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| CN201110093631.9A CN102156668B (en) | 2011-04-14 | 2011-04-14 | Real-time data memory method adopting built-in FLASH program memory of singlechip |
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Cited By (1)
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| CN102629234A (en) * | 2012-01-18 | 2012-08-08 | 物联微电子(常熟)有限公司 | Fast retrieval method for data of built-in Flash of single chip microcomputer |
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| CN1632773A (en) * | 2004-12-31 | 2005-06-29 | 北京中星微电子有限公司 | Interrupt processing apparatus and method in chip |
| CN101645014A (en) * | 2008-08-09 | 2010-02-10 | 海信（北京）电器有限公司 | Method for simulating data storage of EEPROM by using built-in FLASH program storing device of single-chip |
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- 2011-04-14 CN CN201110093631.9A patent/CN102156668B/en active Active
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| CN1632773A (en) * | 2004-12-31 | 2005-06-29 | 北京中星微电子有限公司 | Interrupt processing apparatus and method in chip |
| CN101645014A (en) * | 2008-08-09 | 2010-02-10 | 海信（北京）电器有限公司 | Method for simulating data storage of EEPROM by using built-in FLASH program storing device of single-chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102629234A (en) * | 2012-01-18 | 2012-08-08 | 物联微电子(常熟)有限公司 | Fast retrieval method for data of built-in Flash of single chip microcomputer |
| CN102629234B (en) * | 2012-01-18 | 2015-01-21 | 物联微电子(常熟)有限公司 | Fast retrieval method for data of built-in Flash of single chip microcomputer |
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Effective date of registration: 20210204 Address after: 310018 No.2, Songqiao street, Hangzhou Economic and Technological Development Zone, Hangzhou City, Zhejiang Province Patentee after: PANASONIC HOME APPLIANCES (CHINA) Co.,Ltd. Patentee after: Hangzhou Matsushita Household Appliances Co.,Ltd. Address before: 310018 3-A, No. 6 Songqiao Street, Hangzhou Economic and Technological Development Zone, Zhejiang Province Patentee before: PANASONIC HOME APPLIANCES R&D CENTER (HANGZHOU) Co.,Ltd. Patentee before: Hangzhou Matsushita Household Appliances Co.,Ltd. |