CN102148018B - Circuit for extracting field synchronizing signal from LVDS (Low Voltage Differential Signaling) signal and processing field synchronizing signal - Google Patents
Circuit for extracting field synchronizing signal from LVDS (Low Voltage Differential Signaling) signal and processing field synchronizing signal Download PDFInfo
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- CN102148018B CN102148018B CN 201010112334 CN201010112334A CN102148018B CN 102148018 B CN102148018 B CN 102148018B CN 201010112334 CN201010112334 CN 201010112334 CN 201010112334 A CN201010112334 A CN 201010112334A CN 102148018 B CN102148018 B CN 102148018B
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Abstract
The invention relates to a circuit for extracting a field synchronizing signal from LVDS (Low Voltage Differential Signaling) signals and processing the field synchronizing signal. The circuit comprises a chip of an LVDS signal/digital RGB (Red, Green and Blue) signal, and the signal input end of the chip of the LVDS signal/digital RGB signal is connected with the LVDS signal output end of an image card through a resistor. The invention realizes that the field synchronizing signal is extracted from the signals with diverse input signals and processed into a required reference field synchronizing signal applied to a phase-lock frequency multiplier circuit.
Description
Technical field
The present invention relates to the display circuit technical field, more particularly, relate to a kind of circuit, level conversion and the pulse shaping circuit of field sync signal, ON-OFF control circuit of phase locking frequency multiplying signal output from the multifarious signal of LCD input, extracted, this invention will be extracted field synchronization from the diversity signal of LCD input method is converted to from the LVDS signal to be extracted, thus make extract field sync signal become may and practical.
Background technology
If the input signal of display is single VGA signal, can directly from this signal, takes out field sync signal, and get final product with this reference signal as phase lock circuitry.But in most cases, the input signal of display is multifarious, and therefore how taking out required field sync signal from these multifarious input signals becomes the key of using phase-locked frequency doubling technology.It is to extract field sync signal and the circuit of level translation and shaping pulse in addition the multifarious signal that prior art does not provide from input signal, does not also have the ON-OFF control circuit of phase locking frequency multiplying signal output.
Summary of the invention
The technical problem to be solved in the present invention is, for existing can not be to extract field sync signal and the defective of necessary treatment circuit in addition the multifarious signal from input signal, a kind of circuit that extracts and process field sync signal from the LVDS signal is provided.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of circuit that from the LVDS signal, extracts and process field sync signal, it comprises: comprising: the chip of LVDS signal/digital rgb signal, the signal input part of the chip of described LVDS signal/digital rgb signal links to each other with the LVDS signal output part of image card by resistance.
Wherein, preferably, the described circuit that from the LVDS signal, extracts and process field sync signal, also comprise Sheffer stroke gate device (74LS00), described reception connects from the signal output part of the chip of described LVDS signal/digital rgb signal, receive the field sync signal that the chip of described LVDS signal/digital rgb signal sends over, and will described field sync signal output to phase-locking frequency multiplication circuit after through level conversion and shaping.Simultaneously, also as the on-off circuit of phase locking frequency multiplying signal (300Hz) output, its control signal comes from the phase-locked identification signal of phase lock circuitry to 74LS00.
Wherein, preferred, the 9th pin of the chip of described LVDS signal/digital rgb signal links by resistance R 16 and the 10th pin; The 11st pin links by resistance R 17 and the 12nd pin; The 15th pin links by resistance R 18 and the 16th pin; The 17th pin links by resistance R 19 and the 18th pin; The 19th pin links by resistance R 20 and the 20th pin, and inputs 5 pairs of corresponding signals among the LVDS in respective pins.
Wherein, preferred, the signal output part (the 5th pin) of the chip of the signal input part of described Sheffer stroke gate device (the 5th pin) access described LVDS signal/digital rgb signal; The 60Hz field sync signal of the signal output part of described Sheffer stroke gate device (the 8th pin) output after level conversion and shaping.
Implement technical scheme of the present invention, has following beneficial effect: provide a kind of circuit that from the LVDS signal, extracts field sync signal, can realize from input signal being to extract field sync signal the multifarious signal, and be treated as and be applied to the required reference field synchronizing signal of phase-locking frequency multiplication circuit.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is according to circuit theory diagrams provided by the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the invention provides a kind of circuit that extracts field sync signal from LVDS (low voltage differential signaling, Low Voltage Differential Signal) signal.The chip of LVDS signal/digital rgb signal, the signal input part of the chip of described LVDS signal/digital rgb signal links to each other with the LVDS signal by resistance.In LCD, the diversity picture signal of input becomes unique LVDS digital signal that can be received by liquid crystal panel after the conversion of image card.Utilize the chip of described LVDS signal/digital rgb signal, can from the LVDS signal, extract field sync signal, realized from the diversity input signal, extracting field sync signal.
(model is the chip of LVDS signal/digital rgb signal: the device that DS90CF386MTD) can finish conversion and abstraction function.Its effect is to convert the LVDS signal that image card is exported to digital R, G, B signal, simultaneously exportable, line synchronizing signal.In the example of the present invention, mainly solved following 3 actual application problem:
(1), how the LVDS signal accesses the chip of this LVDS signal/digital rgb signal
(2), the field sync signal of the chip of this LVDS signal/digital rgb signal being exported is treated as the required reference field synchronizing signal of phase-locking frequency multiplication circuit
(3), the signal of phase locking frequency multiplying passes through the control of phase lock circuitry identification signal, joins pwm pulse generation circuit.
In the present embodiment, the LVDS signal of exporting from image card will be divided into two-way (a tunnel directly enters the T_CON plate of liquid crystal display, and another road then will enter the signal input part of the chip of LVDS signal/digital rgb signal).Although can finish well allocating task and don't cause the distortion of LVDS signal with the method for divider, the cost that this method realizes is very high, should not adopt.In example circuit of the present invention, from the drive characteristic of analyzing the LVDS transmitter and the input characteristics of LVDS receiver, adopted the distribution that realizes the LVDS signal with the method for the cascade of build-out resistor.Show by the test to LVDS, this method equally can be in the situation that do not affect original LVDS signal, the harmless distribution of realization signal.
Side circuit as shown in Figure 1, this circuit comprises: by the circuit of build-out resistor with the chip of the LVDS signal of image card access LVDS signal/digital rgb signal, the circuit of the chip of LVDS signal/digital rgb signal and by four Sheffer stroke gate devices (model is: the two-stage Sheffer stroke gate pulse processing circuit that 74LS00) consists of.
In the present embodiment, specifically comprise:
The two ends of the signal input part of the chip of described LVDS signal/digital rgb signal by resistance R 16, R17, R18,5 build-out resistors such as R19, R20 (resistance is 120 ohm) are connected with corresponding signal in the LVDS signal respectively.The 4th, 8,14,21,22,24,28,36,44,52 pin ground connection of the chip (DS90CF386MTD) of described LVDS signal/digital rgb signal.Behind the circuit working, just can obtain our required field sync signal at the 5th pin of the chip of LVDS signal/digital rgb signal.But because the supply voltage of the chip of this LVDS signal/digital rgb signal is 3.3V, and the factors such as the synchronizing signal of exporting in signal conversion process may be interfered, therefore this signal should be carried out necessary processing, required to satisfy follow-up phase-locking frequency multiplication circuit normal operation.
Further among the embodiment, the circuit that extracts field sync signal from the LVDS signal also comprises the 74LS00 four Sheffer stroke gate devices that are used as level conversion and shaping pulse purposes.Extract the 5th pin that field sync signal is imported into described four Sheffer stroke gate devices from the 5th pin of the chip of LVDS signal/digital rgb signal, and after the level conversion of two Sheffer stroke gates that described four Sheffer stroke gate devices the 4th, 5,6 pins and the 8th, 9,10 pins consist of and shaping, be exportablely to satisfy phase lock circuitry to the reference field synchronizing signal of field sync signal amplitude and polar requirement from the 8th pin of described four Sheffer stroke gate devices.
In the circuit, the Sheffer stroke gate that is consisted of by 74LS00 the 1st, 2,3, it is the on-off circuit as the output of phase locking frequency multiplying signal, the signal that adds at the 1st pin of the chip of this LVDS signal/digital rgb signal is the output signal (signal frequency is 300Hz) of phase-locking frequency multiplication circuit, and what add on the 2nd pin is the phase-locked identification signal of phase locking frequency multiplying device output.When phase-locking frequency multiplication circuit was working properly, this output signal was high level, thereby allowed correct phase locking frequency multiplying signal to be formed circuit (otherwise just turn-offing) by the signal of phase-locked and frequency multiplication to pwm pulse from the 3rd pin by resistance R 22 outputs.The power input of described Sheffer stroke gate device (the 4th, 9 pin) access+5V voltage;
The earth terminal of described Sheffer stroke gate device (the 14th pin) is by capacitor C 9 ground connection, the earth terminal of described Sheffer stroke gate device (the 7th pin) ground connection.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. circuit that from the LVDS signal, extracts and process field sync signal, it is characterized in that, comprise: the chip of LVDS signal/digital rgb signal, the model of the chip of described LVDS signal/digital rgb signal is DS90CF386MTD, and the signal input part of the chip of described LVDS signal/digital rgb signal links to each other with the LVDS signal output part of image card by resistance;
Described circuit also comprises Sheffer stroke gate device 74LS00, described Sheffer stroke gate device 74LS00 is connected with the signal output part of the chip of described LVDS signal/digital rgb signal, the field sync signal that reception sends over from the chip of described LVDS signal/digital rgb signal, and will described field sync signal output to phase-locking frequency multiplication circuit after through level conversion and shaping;
Signal input part the 5th pin of described Sheffer stroke gate device 74LS00 accesses field sync signal output terminal the 5th pin of the chip of described LVDS signal/digital rgb signal; The 60Hz field sync signal of signal output part the 8th pin output after level conversion and shaping of described Sheffer stroke gate device 74LS00; The power input the 4th of described Sheffer stroke gate device 74LS00,9 pin access+5V power supplys; Earth terminal the 14th pin of described Sheffer stroke gate device 74LS00 is by capacitor C 9 ground connection; Earth terminal the 7th pin ground connection of described Sheffer stroke gate device 74LS00.
2. circuit as claimed in claim 1 is characterized in that, the 9th pin of the chip of described LVDS signal/digital rgb signal links by resistance R 16 and the 10th pin; The 11st pin links by resistance R 17 and the 12nd pin; The 15th pin links by resistance R 18 and the 16th pin; The 17th pin links by resistance R 19 and the 18th pin; The 19th pin links by resistance R 20 and the 20th pin, and inputs corresponding 5 pairs of signals among the LVDS in respective pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010112334 CN102148018B (en) | 2010-02-09 | 2010-02-09 | Circuit for extracting field synchronizing signal from LVDS (Low Voltage Differential Signaling) signal and processing field synchronizing signal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010112334 CN102148018B (en) | 2010-02-09 | 2010-02-09 | Circuit for extracting field synchronizing signal from LVDS (Low Voltage Differential Signaling) signal and processing field synchronizing signal |
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| CN102148018A CN102148018A (en) | 2011-08-10 |
| CN102148018B true CN102148018B (en) | 2013-02-13 |
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| CN 201010112334 Expired - Fee Related CN102148018B (en) | 2010-02-09 | 2010-02-09 | Circuit for extracting field synchronizing signal from LVDS (Low Voltage Differential Signaling) signal and processing field synchronizing signal |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101193217A (en) * | 2006-11-21 | 2008-06-04 | 青岛海信电器股份有限公司 | LCD TV set with dual-channel LVDS output circuit |
| CN101540146A (en) * | 2008-03-20 | 2009-09-23 | 奇信电子股份有限公司 | Liquid crystal display driving device with interface conversion function |
-
2010
- 2010-02-09 CN CN 201010112334 patent/CN102148018B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101193217A (en) * | 2006-11-21 | 2008-06-04 | 青岛海信电器股份有限公司 | LCD TV set with dual-channel LVDS output circuit |
| CN101540146A (en) * | 2008-03-20 | 2009-09-23 | 奇信电子股份有限公司 | Liquid crystal display driving device with interface conversion function |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2006-166188A 2006.06.22 |
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