CN102142458A - MOS (Metal Oxide Semiconductor) field effect transistor - Google Patents
MOS (Metal Oxide Semiconductor) field effect transistor Download PDFInfo
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- CN102142458A CN102142458A CN2010101026960A CN201010102696A CN102142458A CN 102142458 A CN102142458 A CN 102142458A CN 2010101026960 A CN2010101026960 A CN 2010101026960A CN 201010102696 A CN201010102696 A CN 201010102696A CN 102142458 A CN102142458 A CN 102142458A
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Abstract
The invention provides an MOS (Metal Oxide Semiconductor) field effect transistor comprising a substrate, a source electrode, a drain electrode and a grid stack, wherein the source electrode and the drain electrode are formed in the substrate; the grid stack is formed above the substrate and positioned between the source electrode and the drain electrode; and a grid dielectric layer is made of a dielectric material with an adjustable K value. In the embodiment of the invention, the dielectric material with the adjustable K value is applied to the grid dielectric layer of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device; the grid capacitance is increased by dynamically obtaining the high K value; and the capability of the CMOS device on controlling the short channel effect and the switching rate are improved.
Description
Technical field
The present invention relates to the semiconductor design field, particularly the structure of MOS field-effect transistor (MOSFET).
Background technology
Continuous development along with semiconductor technology, the characteristic size of cmos device is constantly dwindled, thereby cause problems such as short-channel effect, adopt high-k (K value) material (as HfSiON, HfAlON etc.) to replace SiO2 and make gate dielectric layer, can increase the electric current of device, the driving force of enhance device improves control short-channel effect ability, device is further dwindled be able to possibility.The existing integrated circuits device all adopts fixedly K value dielectric material to do the gate insulation medium, yet on interchange (AC) performance of device, the All Ranges that is not the gate insulation medium all is high more good more.For example when cmos device during at the state of opening, because Miller capacitance (Miller capacitor) effect, should be relatively low near the gate medium in drain region to improve the speed of device.Because above consideration, the research and development of a lot of device optimization are arranged and patent takes asymmetric device structures (asymmetric device structure) but symmetrical device requires extra photo etched mask (lithography mask) usually, make cost increase, and technology itself also is subjected to various restrictions (as the angle that ion injects, the height and distance of grid etc.).
Summary of the invention
Purpose of the present invention is intended to one of solve the problems of the technologies described above at least, particularly variable K value dielectric material is applied in the gate dielectric layer.By this method, need not to change on the basis of conventional process flow, can improve the short-channel effect of device simultaneously and the AC characteristic when opening.
For achieving the above object, the present invention proposes a kind of MOSFET structure, comprising: substrate; Be formed on source electrode and drain electrode in the described substrate; And be formed on the described substrate and the grid between described source electrode and described drain electrode pile up, wherein, gate dielectric layer adopts variable K value dielectric material.
In an embodiment of the present invention, described gate dielectric layer comprises the described variable K value dielectric material of one deck at least.
In an embodiment of the present invention, described variable K value dielectric material is meant that its relative dielectric constant has the nonlinear effect that changes with extra electric field.
In an embodiment of the present invention, described variable K value dielectric material be meant possess the high-k rate of change, the ferroelectric material of the perovskite structure of high polarization speed, high breakdown voltage resistant characteristic.
In an embodiment of the present invention, utilize the described nonlinear effect of described variable K value dielectric material,, change the electric capacity between grid and described drain electrode or the source electrode by producing the voltage that changes extra electric field.
In an embodiment of the present invention, the electric capacity between described grid and described drain electrode or the source electrode is proportional to the voltage that puts between described grid and described drain electrode or the source electrode respectively.
The novel MOSFET structure that the present invention proposes, variable K value dielectric material is applied to the gate dielectric layer of MOSFET, dynamically obtain high K value by changing extra electric field, on the one hand: the voltage between grid and source electrode and drain electrode raises gradually, grid source and gate leakage capacitance increase gradually, make grid strengthen, thereby improved control short-channel effect ability the control of raceway groove; On the other hand, when device is opened driving (gate source voltage is higher than threshold voltage), gate voltage will increase to applied voltage Vdd, Vdd is identical with the drain voltage initial value, thereby the voltage in grid leak district is lower, (Miller capacitor) is also less for the formed Miller capacitance of grid leak, thereby the AC characteristic of device (speed) is better.Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1 is the structural representation of the MOSFET of the embodiment of the invention;
Fig. 2 is the equivalent circuit diagram of the MOSFET of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
The present invention proposes a kind of novel MOSFET structure, in embodiments of the present invention, this structure comprise grid and be formed on grid and substrate between gate dielectric layer, wherein, gate dielectric layer adopts variable K value dielectric material, dynamically obtain high K value by changing the voltage that produces external electric field, thereby improve the interchange performance of control short-channel effect ability and device.
As shown in Figure 1, be the structural representation of embodiment of the invention MOSFET.This structure comprises substrate 100; Be formed on source electrode 101 and drain electrode 102 in the substrate; Be formed on the substrate 100 and pile up at source electrode 101 and the grid that drain between 102, wherein, grid pile up comprise grid 103 and be formed on grid 103 and substrate 100 between gate dielectric layer 104, at least comprise the variable K value of one deck layer of dielectric material in the gate dielectric layer 104, can certainly comprise that other materials constitutes gate dielectric layer 104 jointly.In an embodiment of the present invention, gate dielectric layer 104 adopts the ferroelectric material of perovskite structures, for example specifically can be but is not limited to barium strontium titanate (BST) film, strontium lead titanate (PST) film, CaCu 3 Ti 4 O CaCuTi4O12 (CCTO) dielectric ceramic or the like.The common feature of such material be possess the high-k rate of change, fast, the anti-breakdown electric field of polarization speed is big, wherein, the high-k rate of change is embodied in, and relative dielectric constant has the nonlinear characteristic that changes with extra electric field, promptly ferroelectric nonlinear effect.
As shown in Figure 2, be the equivalent circuit diagram of embodiment of the invention MOSFET.According to described ferroelectric nonlinear effect, to adopting described variable K value dielectric material to carry out the analysis of gate leakage capacitance and external electric field relation as the MOSFET device of gate dielectric layer, obtain: gate leakage capacitance Cgd and grid source capacitor C gs are directly proportional with drain-to-gate voltage Vgd and gate source voltage Vgs respectively, Cgd and Cgs all increase when grid potential raises, thereby control short-channel effect better.When this device was opened and drive, gate voltage rose to Vdd, because the drain voltage initial value also is Vdd, drain-to-gate voltage Vgd is near zero, thereby gate leakage capacitance Cgd (Miller electric capacity) is less, and switching speed accelerates.
The novel MOSFET structure that the present invention proposes applies to the gate dielectric layer of MOSFET with variable K value dielectric material, dynamically changes the K value by the change extra electric field, makes device that better short channel control ability and AC characteristic be arranged.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (6)
1. a MOS field effect transistor M OSFET is characterized in that, comprising:
Substrate;
Be formed on source electrode and drain electrode in the described substrate; With
Be formed on the described substrate and the grid between described source electrode and described drain electrode pile up, wherein, the gate dielectric layer during described grid pile up adopts variable K value dielectric material.
2. MOSFET structure as claimed in claim 1 is characterized in that, described gate dielectric layer comprises the described variable K value dielectric material of one deck at least.
3. MOSFET structure as claimed in claim 1 is characterized in that, described variable K value dielectric material is the dielectric material that relative dielectric constant has the nonlinear effect that changes with extra electric field.
4. MOSFET structure as claimed in claim 3 is characterized in that, described variable K value dielectric material is the ferroelectric material that possesses the perovskite structure of high-k rate of change, high polarization speed, high breakdown voltage resistant characteristic.
5. MOSFET structure as claimed in claim 3 is characterized in that, utilizes the described nonlinear effect of described variable K value dielectric material, by changing the voltage that produces extra electric field, changes the electric capacity between grid and described drain electrode or the source electrode.
6. MOSFET structure as claimed in claim 5 is characterized in that, described electric capacity is proportional to the voltage that puts between described grid and described drain electrode or the source electrode respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010102696.0A CN102142458B (en) | 2010-01-28 | 2010-01-28 | MOS (Metal Oxide Semiconductor) field effect transistor |
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| CN201010102696.0A CN102142458B (en) | 2010-01-28 | 2010-01-28 | MOS (Metal Oxide Semiconductor) field effect transistor |
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| CN102142458A true CN102142458A (en) | 2011-08-03 |
| CN102142458B CN102142458B (en) | 2014-03-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094326A (en) * | 2011-11-05 | 2013-05-08 | 中国科学院微电子研究所 | Semiconductor device |
| CN109755242A (en) * | 2019-02-03 | 2019-05-14 | 中国科学院微电子研究所 | Semiconductor device and its manufacturing method and electronic equipment including the device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1290962C (en) * | 2004-12-22 | 2006-12-20 | 中国科学院上海微系统与信息技术研究所 | Nano polishing liquid for high dielectric material strontium barium titanate chemical-mechanical polish |
| CN100580953C (en) * | 2006-09-29 | 2010-01-13 | 华东师范大学 | Strontium bismuth tantalate-strontium barium titanate heterogeneous dielectric material and synthesizing method and application thereof |
| CN100527371C (en) * | 2007-09-14 | 2009-08-12 | 北京大学 | Portion exhausted SOI MOS transistor preparation method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094326A (en) * | 2011-11-05 | 2013-05-08 | 中国科学院微电子研究所 | Semiconductor device |
| CN103094326B (en) * | 2011-11-05 | 2016-08-03 | 中国科学院微电子研究所 | Semiconductor device |
| CN109755242A (en) * | 2019-02-03 | 2019-05-14 | 中国科学院微电子研究所 | Semiconductor device and its manufacturing method and electronic equipment including the device |
| CN109755242B (en) * | 2019-02-03 | 2021-01-29 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
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| CN102142458B (en) | 2014-03-05 |
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