CN102142412B - Input/output pad circuit having electrostatic discharge tolerance and comprising encircling well - Google Patents
Input/output pad circuit having electrostatic discharge tolerance and comprising encircling well Download PDFInfo
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- CN102142412B CN102142412B CN 201010111331 CN201010111331A CN102142412B CN 102142412 B CN102142412 B CN 102142412B CN 201010111331 CN201010111331 CN 201010111331 CN 201010111331 A CN201010111331 A CN 201010111331A CN 102142412 B CN102142412 B CN 102142412B
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Abstract
The invention relates to an input/output pad circuit having electrostatic discharge tolerance and comprising an encircling well, which comprises a semiconductor main body and an encircling well, wherein the semiconductor main body is provided with a first conduction type and a contact pad, and the encircling well is provided with a second conduction type and is laid out to be a circle of area as an electrostatic discharge circuit encircling in the semiconductor main body. The encircling well is relatively deep, and the encircling well also provides a first end point of a diode formed in the semiconductor main body besides the defined area as the electrostatic discharge circuit. In the area encircled by the encircling well, a diode is coupled with the contact pad, a transistor is coupled with a reference voltage device, and the diode and the transistor are connected in series and form a parasitic device in the semiconductor main body.
Description
Technical field
The present invention relates to the ESD protection circuit in a kind of integrated circuit, particularly relate to a kind of I/O pad circuit with static discharge tolerance that comprises around well.
Background technology
Usually include an ESD protection circuit in integrated circuit and I/o pad couples.A representational ESD protection circuit can be consulted the people's such as Salling U.S. Patent number 6858902, and title is " EFFICIENT ESD PROTECTION WITH APPLICATION FOR LOW CAPACITANCEI/O PADS ".
As shown in US Patent specification Fig. 4 of the people such as Salling; a kind of ESD protection circuit of prior art comprises a diode between this contact pad and supply current potential VDD, and it can leak electricity to limit high-tension operation when having high positive voltage to the electrostatic discharge event of VDD.This ESD protection circuit also comprises a field-effect transistor between this contact pad and ground, has parasitic bipolar transistor or thyristor (SCR) structure.This field-effect transistor and parasitic bipolar transistor/thyristor (SCR) structure has a trigger voltage, and it can be opened and discharge when electrostatic event.
Wish that preferably ESD protection circuit has consistent trigger voltage, it can respond electrostatic discharge event rapidly, and operation that can handle high voltages, also can be used in the I/o pad of integrated circuit.
This shows, the circuit structure that above-mentioned existing ESD protection circuit and I/o pad couple obviously still has inconvenience and defective, and demands urgently further being improved in the use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, completed by development but have no for a long time applicable design always, and common product does not have appropriate structure to address the above problem, this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of I/O pad circuit with static discharge tolerance around well of comprising of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to; overcome the defective that circuit structure that existing ESD protection circuit and I/o pad couple exists; and a kind of I/O pad circuit with static discharge tolerance around well of comprising of new structure is provided; technical problem to be solved is to make it by the Current Limits in the discharge event is fixed in a region of discharge; and has consistent trigger voltage; can respond rapidly electrostatic discharge event, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of I/O pad circuit with static discharge tolerance that comprises around well that the present invention proposes, it comprises: the semiconductor main body has one first conduction type; One contact pad is on this semiconductor body; One around well in this semiconductor body, couple with this contact pad and have one second conduction type, should be surrounded on a zone in this semiconductor body around well; And in an electrostatic discharge circuit this zone in this semiconductor body, comprise that a diode and this contact pad couple, and a transistor is applicable to couple with a reference voltage, so that a discharge current path between this contact pad and this reference voltage to be provided in a region of discharge of this semiconductor body.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well comprises: in an interior well this zone in this semiconductor body, and have this second conduction type; One first end points of this diode comprises a doped region in this interior well, has this first conduction type, and this first end points and this contact pad couple; One second end points of this diode comprises a doped region in this interior well, has this second conduction type; This transistorized one source pole and a drain electrode have this second conduction type in this zone of this main body; One main body end points has this first conduction type in this zone in this main body, this main body end points is applicable to couple with this reference voltage and this transistorized this source electrode; One bias voltage end points in this main body, have this second conduction type in this zone between this interior well and this drain electrode, this bias voltage end points and a voltage source couple; And be connected in one in this main body and this second end points of this diode is coupled with this transistorized this drain electrode.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said main body end points, this source electrode and this drain electrode have the degree of depth, and should have one around well depth around well, it far surpasses drain at least one the degree of depth of this main body end points, this source electrode and this.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said main body end points, this source electrode and this drain electrode have the degree of depth, and should have one around well depth around well, it is drain at least one two times to ten times of the degree of depth of this main body end points, this source electrode and this.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, comprise one around well trench insulation body in this main body between this is around well and this zone, and have one around trench depth, should have a degree of depth in this main body around well is around trench depth greater than this.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, comprise an internal trenches insulator in this main body between this interior well and this drain electrode, and have an internal trenches degree of depth, this drain electrode has a degree of depth in this main body be less than this internal trenches degree of depth.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said zone comprises a first and a second portion, and comprises: an internal trenches insulator in this main body between this first and this second portion in this zone; One around well trench insulation body in this main body between this is around well and this zone, and have one around trench depth, should have a degree of depth in this main body around well is around trench depth greater than this; In this first in this zone of one interior well in this main body, and have this second conduction type, this interior well has a degree of depth in this main body be around trench depth greater than this; One first end points of this diode comprises a doped region in this interior well, has this first conduction type, and this first end points and this contact pad couple; One second end points of this diode comprises a doped region in this interior well, has this second conduction type; This transistorized one source pole and a drain electrode have this second conduction type in this second portion in this zone of this main body; One main body end points has this first conduction type in this second portion in this zone in this main body, this main body end points is applicable to couple with this reference voltage and this transistorized this source electrode; One bias voltage end points in this main body, have this second conduction type in this zone between this first and this second portion, this bias voltage end points is applicable to couple with a voltage source; And this second end points of this diode couples with this transistorized this drain electrode.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said drain electrode are that this second end points by one second field-effect transistor and this diode couples.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said transistor has a grid and is applicable to couple with this reference voltage.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said transistor comprises a field transistor.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of I/O pad circuit with static discharge tolerance that comprises around well that the present invention proposes, it comprises: the semiconductor main body has one first conduction type; One contact pad is on this semiconductor body; One around well in this semiconductor body, couple with this contact pad and have one second conduction type, should be surrounded on a zone in this semiconductor body around well; One locking prevents the bias voltage end points in this main body, has this second conduction type, and to cut apart this zone be a first and a second portion, and this locking prevents that the bias voltage end points is applicable to couple with a voltage source; In this first in this zone of one interior well in this main body, and has this second conduction type; One doped region has this first conduction type in this interior well, be as one first end points of a diode and couple with this contact pad; One second end points of this diode comprises a doped region in this interior well, has this second conduction type; One transistorized one source pole and a drain electrode have this second conduction type in this second portion in this zone of this main body; And one the main body end points in this main body, have this first conduction type in this second portion in this zone, this main body end points is applicable to couple with a reference voltage and this transistorized this source electrode.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, comprise: a plurality of trench insulation bodies between this is around well and this zone, between this first end points and this second end points of this diode, prevent between the bias voltage end points, prevent between bias voltage end points and this source electrode and this drain electrode between this locking between this interior well and this locking, and between this source electrode and should drain electrode and this main body end points between.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said main body end points, this source electrode and this drain electrode have the degree of depth, and should have one around well depth around well, it far surpasses drain at least one the degree of depth of this main body end points, this source electrode and this.
Aforesaid a kind of I/O pad circuit with static discharge tolerance that comprises around well, wherein said main body end points, this source electrode and this drain electrode have the degree of depth, and should have one around well depth around well, it is drain at least one two times to ten times of the degree of depth of this main body end points, this source electrode and this.
The present invention compared with prior art has obvious advantage and beneficial effect.By above technical scheme as can be known, main technical content of the present invention is as follows:
For achieving the above object, the invention provides a kind of I/O pad circuit with static discharge tolerance that comprises around well, comprise the semiconductor main body, have one first conduction type, normally p-type, be coupled to a reference voltage, normally the ground of p-type substrate.One contact pad is formed on this semiconductor body, and it can be used as and is applied in this device and an end points of extraneous phase connection circuit.One well is called around well herein, has one second conduction type (as being N-shaped for the p-type substrate), and layout is one to be surrounded on the zone as electrostatic discharge circuit in this semiconductor body.This is relatively dark around well, and except defining a zone as electrostatic discharge circuit, also provides one first end points of a diode to be formed in semiconductor body.This around well around a zone in, one diode and this contact pad couple, and a transistor AND gate reference voltage couples, these both be series connection and form a dominant parasitic device in this semiconductor body and provide a discharge current path in being confined to semiconductor body deeply around in the formed region of discharge of well.
In a dark interior well this zone in this semiconductor body, and have this second conduction type, be positioned at around well around a zone.One first end points of the diode of this electrostatic discharge circuit, itself and contact pad couple, and comprise a doped region in this interior well, have this first conduction type.One second end points of the diode of this electrostatic discharge circuit comprises a doped region in this interior well, has this second conduction type.This transistorized one source pole and one the drain electrode in this main body, around well around the zone in, have this second conduction type.One main body end points has this first conduction type in this zone in this main body, and has within a collecting region contact is formed at this zone, and couples with this reference voltage and this transistorized this source electrode.One locking prevents that bias voltage end points and the voltage source from coupling, and also is provided at the zone between this interior well and transistor in main body.Be connected in one in this main body and couple with the second end points and the transistorized drain electrode of diode.
This around well therewith contact pad couple, so, this can reach roughly the same with contact pad high voltage around well in a high positive voltage discharge event.Also because it is enough dark, so tendency is limited to the current flowing in the discharge event in one volume of this semiconductor body.Therefore, the carrier that injects in this semiconductor body assists to open this dominant parasitic device in an efficient and consistent mode.In addition, when this contact pad pad and when very high around the voltage of well, be reversely biased between the diode around well and semiconductor body because form, so positive charge can not flow to dark interior well.So limited positive charge within the region of discharge around well.
In addition, structure described herein also can be fit to high-tension application because from contact pad to forward diode path not between supply-voltage source VDD.So still can valid function during higher than VDD at the voltage of contact pad.
The trench insulation body uses herein in described device, comprise around well trench insulation body between this around the main body between well and its circle zone in.In addition, in the main body of an internal trenches insulator between this interior well and transistor drain.It is the degree of depth greater than this transistor drain that this internal trenches insulator has a degree of depth.By the Current Limits in the discharge event is fixed in this region of discharge, this parasitic bipolar transistor can be opened more evenly.
By technique scheme; a kind of I/O pad circuit with static discharge tolerance that comprises around well of the present invention has following advantages and beneficial effect at least: ESD protection circuit of the present invention can evenly be opened parasitic bipolar transistor; can bear higher static discharge current, and operation that can handle high voltages.
In sum, the invention relates to a kind of I/O pad circuit with static discharge tolerance that comprises around well, comprise the semiconductor main body, have one first conduction type, and a contact pad.One has one second conduction type around well, and layout is one to be surrounded on the zone as electrostatic discharge circuit in this semiconductor body.This is relatively dark around well, and except defining a zone as electrostatic discharge circuit, also provides one first end points of a diode to be formed in semiconductor body.This around well around a zone in, a diode and this contact pad couple, and transistor AND gate one reference voltage couples, both are series connection and form a dominant parasitic device in this semiconductor bodies for this.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and the cooperation accompanying drawing, be described in detail as follows.
Description of drawings
Fig. 1 is according to the schematic diagram that the present invention includes around the electrostatic discharge circuit of well.
Fig. 2 be show comprise one around well the generalized section of the electrostatic discharge circuit in the semiconductor main body.
Fig. 3 shows that one comprises a schematic layout pattern around the electrostatic discharge circuit of well.
Fig. 4 shows that comprise one substitutes the block diagram of electrostatic discharge circuit around first of well.
Fig. 5 shows that comprise one substitutes the block diagram of electrostatic discharge circuit around second of well.
10,400,500: I/o pad 11,401,501: around well
12,402,502: diode 13,403,503: ground
14,404,504: interior well 15,405,505: the second diodes
16: field-effect transistor 17,407,507:n type end points
18,408,508: voltage source 19,509a, 509b: grid
20,410,510: collecting region end points 21,411,511: substrate resistance
50: around well 51: dark interior well
52:p+ type end points 53,54,55:n+ type end points
56: drain terminal 57: the source electrode end points
58,59: light Doped n-type zone 60: collecting region end points
61,62,64: connector 63: grid
70,71,72,73,74,75: trench insulation body 80:PNP parasitic bipolar transistor
81:NPN parasitic bipolar transistor 100: semiconductor body
200: around well 201:n type well
202-1 is to 202-7:p+ type end points 203,204:n+ type end points
205: active area 206: collecting region
210: trench insulation body 211-1 is to 211-8: grid
406: field-effect transistor 506a, 506b: transistor
Embodiment
Reach for further setting forth the present invention technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, a kind of its embodiment of I/O pad circuit, structure, feature and effect thereof with static discharge tolerance that comprises around well to foundation the present invention proposes is described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known to present in the following detailed description that coordinates with reference to graphic preferred embodiment.By the explanation of embodiment, when can be to reach technological means and the effect that predetermined purpose takes to obtain one more deeply and concrete understanding to the present invention, yet appended graphic only be to provide with reference to the use of explanation, the present invention is limited.
The following description of the embodiment of the present invention please coordinate consults Fig. 1 to shown in Figure 5.
Fig. 1 is according to the present invention includes schematic diagram around the electrostatic discharge circuit of well, this electrostatic discharge circuit comprise a N-shaped around well 11 in a p-type semiconductor body.This N-shaped can be consulted Fig. 2 around the more detailed construction of well 11.This N-shaped provides a negative electrode of a diode 12 around well 11, and an anode of diode 12 is semiconductor bodies.This semiconductor body is coupled by substrate resistance 21 and ground 13.This N-shaped defines a zone around well 11, and one second diode 15 is to connect to be arranged between I/o pad 10 and ground 13 with the source-drain electrode of a field-effect transistor 16 therein.Within this diode 15 is formed at a dark N-shaped interior well 14.One locking prevents that N-shaped end points 17 and the voltage source 18 from coupling, and is for example supply current potential VDD so that a voltage to be provided, and is to be formed between interior well 14 and transistor 16.P+ type collecting region end points 20 is formed at transistor 16 and around between well 11, and couples with ground 13.The grid 19 of transistor 16 couples with ground in this embodiment.And in other embodiment, it can be suspension joint or couple with other reference voltages.
Fig. 2 Fig. 2 be show comprise one around well the generalized section of the electrostatic discharge circuit in the semiconductor main body, it has shown the generalized section of circuit shown in application drawing 1, in the integrated circuit that comprises semiconductor body 100.This semiconductor body can be the bulk wafer, and a main body is formed on insulator, or other structures.In section, in semiconductor body 100 is that a deep-well couples with the I/o pad with N-shaped doping around well 50, and having a part is left side and the right side that is shown in this cross-section illustration.The trench insulation body is for example that shallow slot isolation structure 70 and 71 is in the both sides around well 50.This trench insulation body 71 (around insulator) is between the interior zone around well and formation diode/transistor discharge circuit.This has a degree of depth greater than the degree of depth of trench insulation body 71 around well 50.End points 50a, the 50b of n+ kenel is provided in the surface around well 50, so that the ohmic contact with contact pad to be provided.
The one dark interior well 51 with N-shaped doping is formed at this regional right side.A p+ type end points 52 is formed in this dark interior well 51 and couples with I/o pad.A n+ type end points 53 is formed in this dark interior well 51, and as the anode that is formed at diode in this interior well 51.One channel isolating structure 72 is separated the structure on right side in interior well 51 and figure.N+ type end points 54 and 55 is separated by trench insulation body 73 in semiconductor body 100, is to prevent end points as locking.One trench insulation body 74 is separated drain terminal 56 and the source electrode end points 57 that locking prevents end points 55 and field-effect transistor.This drain terminal 56 is that a n+ type in semiconductor body 100 is regional.Similarly, this source electrode end points 57 is to be formed in semiconductor body 100 and to comprise n+ type zone to be separated by a passage with drain terminal 56.In this embodiment, light Doped n-type zone 58,59 is formed at respectively between drain terminal 56 and source electrode end points 57 and transistorized passage.Transistorized grid 63 and is separated itself and passage by a gate insulator on passage.The other tilting zone of grid is the side wall member of transistor gate.The source electrode end points 57 that one trench insulation body 75 is separated field-effect transistors be formed at this layout right side near trench insulation body 71 with around the p+ type collecting region end points 60 in the semiconductor body 100 of well 50.This around well 50 have a degree of depth be much larger than, be for example 2 times to 10 times dark, the degree of depth in n+ type and p+ type zone comprises end points 52,53,54,55,56,57 and 60, and consists of this discharge circuit, and therefore as a Current Limits fixed structure.Be to be considered to far be deeper than as the bias voltage locking prevent end points 54 and 55 and one of drain terminal 56 and source electrode end points 57 around well 50, it has the flow of charge restriction in this dominant parasitic device with impact of enough degree of depth.
As shown in FIG., end points 53 is as the anode of diode and be connected with transistorized drain terminal 56 by a connector that is positioned on semiconductor body.In addition, transistorized source electrode end points 57 couples with ground, and is coupled by the line 64 and the p+ type collecting region end points 60 that are positioned on semiconductor body, and its center line 64 is a connector on semiconductor body 100.Locking prevent end points 54 and 55 by one be positioned on semiconductor body connector 62 and with one be for example that the voltage source of supply current potential VDD couples.
As shown in Figure 2, parasitic bipolar transistor 80 and 81 (also forming a thyristor (SCR)) forms according to the result of this layout.This bipolar transistor 80 is PNP devices, and p+ type end points 52 is to be as base stage and the p-type semiconductor body is as collector as emitter-base bandgap grading, the dark interior well 51 of N-shaped therein.This bipolar transistor 81 is NPN devices, and drain terminal 56 is to be as base stage and source electrode end points 57 is as collector as emitter-base bandgap grading, semiconductor body 100 therein.In operation, when a positive electrostatic discharge event, the diode that electric current is formed by end points 52 and 53 is to the transistor that comprises drain electrode 56 and source electrode 57 to ground.In addition, electric current flows at the parasitic bipolar transistor that end points 52, the dark interior well 51 of N-shaped and semiconductor body 100 form, and the injection positive charge enters the base stage of bipolar transistor 81 and the p+ type collecting region end points 60 that arrives.In addition, flow of charge enter the passage of field-effect transistor and promote substrate bias and assist to open field effect transistor and bipolar electrostatic induction transistor 81 both.This is limited to the p+ type collecting region end points 60 to ground connection from PNP parasitic bipolar transistor 80 around well 50 tendencies with current flowing in this zone, improved the current density of field-effect transistor and npn parasitic bipolar transistor 81 base stages, caused this device more evenly to reach fast and open.In addition because this around well 50 and dark interior well 51 therewith contact pad couple, it can reach roughly the same with contact pad high voltage in a high positive voltage discharge event.So cause forming between being reversely biased around the diode of well 50 with semiconductor body 100, reaching to form between the diode of dark interior well 51 with semiconductor body and be reversely biased.So limited around the positive charge within well 50.
This is relatively dark wells around well 50 and dark interior well 51, and has a well depth, for example, and in 1 to 1.5 micron number magnitude.Has a well depth in 0.13 to 0.18 micron number magnitude in system separately around other n+ type end points in well institute circle zone thus.Therefore, be far to be deeper than collecting region end points and one of drain electrode and source electrode end points around well.Other p+ type end points in this zone have a well depth in 0.17 to 0.23 micron number magnitude.The trench insulation body is to arrange also deeplyer than n+ type end points and p+ type end points, is for example in 0.28 to 0.35 micron number magnitude.
This doping content around well 50 and interior well 51 can be 10E13/cm
2The order of magnitude.Similarly, end points 52,53,54,55,56,57 and 60 doping content can be 10E15/cm
2The order of magnitude.
In the case, dark is limited to the current flowing in the discharge event in one volume of this semiconductor body around well and interior well tendency, and can provide consistent and discharge fast, and can prevent from being dispersed into outside main current path at the interdischarge interval electric charge.
Fig. 3 shows that one comprises a schematic layout pattern around the electrostatic discharge circuit of well, and it has shown that a layout that is similar to electrostatic discharge circuit shown in Fig. 2 shows.As what described before, trench insulation body 210 is separated many different elements.This layout shows that N-shaped has a rectangular shape around well 200.Darker N-shaped well 201 be positioned at by around 200, well around the zone within.Within a n+ type end points 201a is formed at this darker N-shaped well 201 and have a trapezoidal pattern.P+ type end points 202-1 is between the horizontal line of trapezoidal pattern n+ type end points 201a to 202-7.In this layout, the edge of the N-shaped well 201 that this is darker is to aim at the edge of n+ type end points 201a.The collecting region end points (in figure is for indicate " x " and blockage) aim at the surface of n+ type end points 201a.Similarly, the collecting region end points is aimed to the surface of 202-7 with p+ type end points 202-1.
Locking prevent n+ type end points 203 and 204 be vertical extend through by around 200, well around the zone.
Transistorized n+ type active area 205 comprises that 5 source region S and 4 drain region D are placed on dark N-shaped well 201 opposite sides, and makes locking prevent that n+ type end points 203 and 204 is mediate.Grid structure 211-1 is to be formed on active area 205 by doped polycrystalline silicon or metal wire to 211-8.(only indicating 211-1 and 211-8 in diagram too crowded to prevent).
P+ type collecting region 206 forms between active area 205 and the right side around well 200, and stretch by by around the defined zone of well 200 on the edge.Although do not indicate in diagram, on many different end points, wherein these end points can be used for being connected with the connector of the reference voltage of being discussed before, voltage source or top collecting region end points (being shown as little " x " square).
These are positioned at size and the number of gates of the digitized diode structure of N-shaped well 201, and these size and number of gates of being positioned at the digitized transistor arrangement of active area 205 tops can change according to the demand of application-specific.Similarly, locking prevents that the number of end points 203 and 204 from also can change according to the demand of application-specific.Similarly, dark N-shaped well 201 and the distance of active area 205 also can optionally be adjusted the performance that prevents locking and improve this electrostatic discharge circuit.
In a representative system, have 14 areas and be the 1.5 p+ type end points of taking advantage of 24 square microns in dark N-shaped well, rather than 7 end points 202-1 as shown in Fig. 3 layout are to 202-7.In addition, in a representative system, the transistor in active area 205 in layout has 6 source electrode end points and 5 drain terminal and 10 grids, and the size of these grids is about 0.6 and takes advantage of 30 square microns.
Fig. 4 shows that comprise one substitutes the block diagram of electrostatic discharge circuit around first of well, Fig. 5 shows that comprise one substitutes the block diagram of electrostatic discharge circuit around second of well, and it can use described herein around the well collocation alternative n channel mos field-effect transistor 16 different from Fig. 1.Also can use other alternate embodiment, use as the npn parasitic bipolar transistor 81 in Fig. 2.
In Fig. 4, the transistor 16 in Fig. 1 is replaced by a field-effect transistor 406, and it has thicker oxide layer on passage.Therefore, the circuit in Fig. 4 comprises I/o pad 400 and couples with electrostatic discharge circuit, its comprise N-shaped around well 401 in a p-type semiconductor body.This N-shaped provides a negative electrode of a diode 402 around well 401, and an anode of diode 402 is semiconductor bodies.This semiconductor body is coupled by substrate resistance 411 and ground 403.This N-shaped defines a zone around well 401, and one second diode 405 is to connect to be arranged between I/o pad 400 and ground 403 with the source-drain electrode of a field-effect transistor 406 therein.One locking prevents that n+ type end points 407 and the voltage source 408 from coupling, and is for example supply current potential VDD so that a voltage to be provided, and is to be formed between interior well 404 and field-effect transistor 406.P+ type collecting region end points 410 is formed at field-effect transistor 406 and around between well 401, and couples with ground 403.
In Fig. 5, the transistor 16 in Fig. 1 by the series winding transistor 506a and 506b replaced, its at least one be biased into when this integrated circuit normal running and close.Therefore, the circuit in Fig. 5 comprises I/o pad 500 and couples with electrostatic discharge circuit, its comprise N-shaped around well 501 in a p-type semiconductor body.This N-shaped provides a negative electrode of a diode 502 around well 501, and an anode of diode 502 is semiconductor bodies.This semiconductor body is coupled by substrate resistance 511 and ground 503.This N-shaped defines a zone around well 501, and one second diode 505 is to connect to be arranged between I/o pad 500 and ground 503 with the source-drain electrode of transistor 506a and 506b therein.One locking prevents that n+ type end points 507 and the voltage source 508 from coupling, and is for example supply current potential VDD so that a voltage to be provided, and is to be formed between interior well 504 and transistor 506a and 506b.When the one or both of grid 509a and 509b can couple to guarantee normal running with ground, current path is pent.P+ type collecting region end points 510 is formed at transistor 506b and around between well 501, and couples with ground 503.
the above, it is only preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet be not to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (12)
1. I/O pad circuit with static discharge tolerance that comprises around well is characterized in that it comprises:
The semiconductor main body has one first conduction type;
One contact pad is on this semiconductor body;
One around well in this semiconductor body, couple with this contact pad and have one second conduction type, should be surrounded on a zone in this semiconductor body around well; And
In one electrostatic discharge circuit this zone in this semiconductor body, comprise that a diode and this contact pad couple, and a transistor is applicable to couple with a reference voltage, so that a discharge current path between this contact pad and this reference voltage to be provided in a region of discharge of this semiconductor body.
2. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 1 is characterized in that comprising:
In one interior well this zone in this semiconductor body, and has this second conduction type;
One first end points of this diode comprises a doped region in this interior well, has this first conduction type, and this first end points and this contact pad couple;
One second end points of this diode comprises a doped region in this interior well, has this second conduction type;
This transistorized one source pole and a drain electrode have this second conduction type in this zone of this main body;
One main body end points has this first conduction type in this main body, in this zone, this main body end points is applicable to couple with this reference voltage and this transistorized this source electrode;
One bias voltage end points has this second conduction type in this main body, between this interior well and this drain electrode, this bias voltage end points and a voltage source couple in this zone; And
Be connected in one in this main body and this second end points of this diode is coupled with this transistorized this drain electrode.
3. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 2, it is characterized in that wherein said main body end points, this source electrode and this drain electrode have the degree of depth, and should have one around well depth around well, it is drain at least one two times to ten times of the degree of depth of this main body end points, this source electrode and this.
4. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 1, it is characterized in that comprising one around well trench insulation body in this main body between this is around well and this zone, and have one around trench depth, should have a degree of depth in this main body around well is around trench depth greater than this.
5. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 2, it is characterized in that comprising an internal trenches insulator in this main body between this interior well and this drain electrode, and have an internal trenches degree of depth, this drain electrode has a degree of depth in this main body be less than this internal trenches degree of depth.
6. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 1 is characterized in that wherein said zone comprises a first and a second portion, and comprises:
One internal trenches insulator in this main body between this first and this second portion in this zone;
One around well trench insulation body in this main body between this is around well and this zone, and have one around trench depth, should have a degree of depth in this main body around well is around trench depth greater than this;
In this first in this zone of one interior well in this main body, and have this second conduction type, this interior well has a degree of depth in this main body be around trench depth greater than this;
One first end points of this diode comprises a doped region in this interior well, has this first conduction type, and this first end points and this contact pad couple;
One second end points of this diode comprises a doped region in this interior well, has this second conduction type;
This transistorized one source pole and a drain electrode have this second conduction type in this second portion in this zone of this main body;
One main body end points has this first conduction type in this main body, in this second portion in this zone, this main body end points is applicable to couple with this reference voltage and this transistorized this source electrode;
One bias voltage end points has this second conduction type in this main body, between this first and this second portion, this bias voltage end points is applicable to couple with a voltage source in this zone; And
This of this diode the second end points couples with this transistorized this drain electrode.
7. put according to claim 6 comprising around the I/O pad circuit with static discharge tolerance of well, it is characterized in that wherein said drain electrode is that this second end points by one second field-effect transistor and this diode couples.
8. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 1, is characterized in that wherein said transistor has a grid and this reference voltage couples.
9. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 1, is characterized in that wherein said transistor comprises a field transistor.
10. I/O pad circuit with static discharge tolerance that comprises around well is characterized in that it comprises:
The semiconductor main body has one first conduction type;
One contact pad is on this semiconductor body;
One around well in this semiconductor body, couple with this contact pad and have one second conduction type, should be surrounded on a zone in this semiconductor body around well;
One locking prevents the bias voltage end points in this main body, has this second conduction type, and to cut apart this zone be a first and a second portion, and this locking prevents that the bias voltage end points is applicable to couple with a voltage source;
In this first in this zone of one interior well in this main body, and has this second conduction type;
One doped region has this first conduction type in this interior well, be as one first end points of a diode and couple with this contact pad;
One second end points of this diode comprises a doped region in this interior well, has this second conduction type;
One transistorized one source pole and a drain electrode have this second conduction type in this second portion in this zone of this main body; And
One main body end points has this first conduction type in this main body, in this second portion in this zone, this main body end points is applicable to couple with a reference voltage and this transistorized this source electrode.
11. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 10 is characterized in that comprising:
A plurality of trench insulation bodies between this is around well and this zone, between this first end points and this second end points of this diode, prevent between the bias voltage end points, prevent between bias voltage end points and this source electrode and this drain electrode between this locking between this interior well and this locking, and between this source electrode and should drain electrode and this main body end points between.
12. the I/O pad circuit with static discharge tolerance that comprises around well according to claim 10, it is characterized in that wherein said main body end points, this source electrode and this drain electrode have the degree of depth, and should have one around well depth around well, it is drain at least one two times to ten times of the degree of depth of this main body end points, this source electrode and this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010111331 CN102142412B (en) | 2010-02-02 | 2010-02-02 | Input/output pad circuit having electrostatic discharge tolerance and comprising encircling well |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010111331 CN102142412B (en) | 2010-02-02 | 2010-02-02 | Input/output pad circuit having electrostatic discharge tolerance and comprising encircling well |
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| Publication Number | Publication Date |
|---|---|
| CN102142412A CN102142412A (en) | 2011-08-03 |
| CN102142412B true CN102142412B (en) | 2013-06-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010111331 Active CN102142412B (en) | 2010-02-02 | 2010-02-02 | Input/output pad circuit having electrostatic discharge tolerance and comprising encircling well |
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| CN (1) | CN102142412B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157573A (en) * | 1989-05-12 | 1992-10-20 | Western Digital Corporation | ESD protection circuit with segmented buffer transistor |
| US5237395A (en) * | 1991-05-28 | 1993-08-17 | Western Digital Corporation | Power rail ESD protection circuit |
| US5389811A (en) * | 1994-04-14 | 1995-02-14 | Analog Devices, Incorporated | Fault-protected overvoltage switch employing isolated transistor tubs |
| US5945713A (en) * | 1994-09-26 | 1999-08-31 | International Business Machines Corporation | Electrostatic discharge protection circuits for mixed voltage interface and multi-rail disconnected power grid applications |
-
2010
- 2010-02-02 CN CN 201010111331 patent/CN102142412B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157573A (en) * | 1989-05-12 | 1992-10-20 | Western Digital Corporation | ESD protection circuit with segmented buffer transistor |
| US5237395A (en) * | 1991-05-28 | 1993-08-17 | Western Digital Corporation | Power rail ESD protection circuit |
| US5389811A (en) * | 1994-04-14 | 1995-02-14 | Analog Devices, Incorporated | Fault-protected overvoltage switch employing isolated transistor tubs |
| US5945713A (en) * | 1994-09-26 | 1999-08-31 | International Business Machines Corporation | Electrostatic discharge protection circuits for mixed voltage interface and multi-rail disconnected power grid applications |
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| Publication number | Publication date |
|---|---|
| CN102142412A (en) | 2011-08-03 |
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