CN102142283B - Method for testing nonvolatile memory - Google Patents
Method for testing nonvolatile memory Download PDFInfo
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- CN102142283B CN102142283B CN 201010102373 CN201010102373A CN102142283B CN 102142283 B CN102142283 B CN 102142283B CN 201010102373 CN201010102373 CN 201010102373 CN 201010102373 A CN201010102373 A CN 201010102373A CN 102142283 B CN102142283 B CN 102142283B
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Abstract
The invention discloses a method for testing a nonvolatile memory. The method comprises the following steps of: a, selecting a group of nonvolatile memory units on one random word line or bit line; b, writing data into the odd nonvolatile memory units in the nonvolatile memory unit group, and measuring a first leakage current value; c, writing data into the even nonvolatile memory units in the nonvolatile memory unit group, and measuring a second leakage current value; d, after the data are written into the nonvolatile memory unit group, measuring a third leakage current value; and e, judging whether the difference between the third leakage current value and the sum of the first leakage current value and the second leakage current value is in a permissible range, wherein if the difference is not in the permissible range, the nonvolatile memory has flaws and is not suitable for continuous reliability test, and the sequence of the b, c and d can be interchanged.
Description
Technical field
The present invention relates to the silicon semiconductor device field tests, particularly a kind of method of testing of nonvolatile memory is used for judging whether this nonvolatile memory is fit to proceed reliability testing.
Background technology
Nonvolatile memory (NVM, Non-Volatile Memory) adopts the floating grid structure to store data usually.Floating grid be designed to can stored charge structure, and utilize oxide skin(coating) to carry out insulation processing, once for a long time (more than 10 years) maintenance of the electric charge of accumulation.Fig. 1 has shown a kind of structural representation of non-volatile memory cells.Among Fig. 1, the channel region that in Semiconductor substrate 10, is formed with source region 11, drain region 12 and between source region 11 and drain region 12, extends.Provide tunnel oxide 17 at channel region, and form floating grid 15 in tunnel oxide 17.Control gate 13 is separated by dielectric layer between grid 16 and floating grid 15.The writing of data (Program) is that injection by electric charge in the floating grid 15 is carried out with discharging with wiping (Erase) in the non-volatile memory cells.Electric charge in the floating grid 15 can be offset the voltage that offers control gate 13.That is to say that if data writing is arranged in the storage unit, accumulated electric charge in the floating grid 15, then threshold voltage increases.Situation (not having data writing in the storage unit) when not having electric charge in the floating grid 15 is compared, if high voltage is provided for control gate 13, and 12 states that can not be in conducting in source region 11 and drain region then.Therefore, judge whether write data in this non-volatile memory cells by whether having accumulated electric charge in the floating grid 15.Particularly, concerning flash memory (flash), data writing is data writing " 0 " in the storage unit.And concerning EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM), it is data writing " 1 " that data writing is arranged in the storage unit.
Nonvolatile memory usually is expert at a plurality of memory cell arrangements and is listed to consist of the memory cell array of matrix type.Each storage unit is configured in the intersection point place of many word lines and multiple bit lines, and one in the control gate of the storage unit of each row and the many word lines is connected, and one in drain electrode and the multiple bit lines is connected.
The reliability testing of nonvolatile memory is the Efficient Evaluation method in its serviceable life.Yet reliability testing is the accumulation results of a kind of time, and test period is usually very long, needs one to two months even the longer time.This mainly is because aging (the burn in the reliability testing process, BI) test needs long time, and present BI board can not Real-Time Monitoring product to be measured characteristic, the final test behind burn-in test (final test, FT) is the unique channel of judging product.In a single day occur unsuccessfully in the process of whole reliability testing, whole work just need to restart, and wastes time and energy.
Summary of the invention
The object of the present invention is to provide a kind of method of testing of nonvolatile memory, can judge whether this nonvolatile memory is fit to proceed reliability testing.
The invention provides a kind of method of testing of nonvolatile memory, be used for judging whether described nonvolatile memory is fit to proceed reliability testing, and described nonvolatile memory comprises: many word lines; With described many multiple bit lines that the word line is arranged in a crossed manner; And a plurality of non-volatile memory cells, it is configured in each intersection point place of described many word lines and described multiple bit lines, each non-volatile memory cells has floating grid and control gate, wherein, described method of testing comprises: a, one group of non-volatile memory cells on selected any word line or the bit line; B behind odd bits non-volatile memory cells data writing in described one group of selected non-volatile memory cells, measures the first leakage current value; C behind even bit non-volatile memory cells data writing in described one group of selected non-volatile memory cells, measures the second leakage current value; D behind described one group of selected equal data writing of non-volatile memory cells, measures the 3rd leakage current value; E, judge that the difference of described the first leakage current value and described the second leakage current value sum and described the 3rd leakage current value is whether in permissible range, if not in permissible range, then there is flaw in described nonvolatile memory, be not suitable for proceeding reliability testing, wherein, the order of step b, c, d can be exchanged.
Further, if among the step e, judged result is within permissible range, and circulation step a～e then is until test all word lines or all bit lines of described nonvolatile memory.
Further, described nonvolatile memory is flash memory.
Further, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo).
Further, described permissible range is for being not more than 1 microampere.
Further, adopt to measure described the first leakage current value of unit measuring, the second leakage current value and the 3rd leakage current value, the measuring accuracy of described measurement unit is for receiving the peace level, and working temperature is normal temperature.
Compared with prior art, the method of testing of nonvolatile memory provided by the invention, one group of non-volatile memory cells on selected any word line or the bit line, respectively to the odd bits storage unit, even bit storage unit and whole storage unit data writing obtain the first corresponding leakage current value with measurement, the second leakage current value and the 3rd leakage current value, whether recently judge mutually with the 3rd leakage current value whether this nonvolatile memory exists flaw by comparing the first leakage current value with the second leakage current value sum, just can select thus the good storer of performance and carry out reliability testing, that guarantees to test carries out smoothly, and then assesses out exactly the use life-span.
Description of drawings
Fig. 1 is a kind of structural representation of non-volatile memory cells;
Fig. 2 is the process flow diagram of the method for testing of nonvolatile memory of the present invention.
Embodiment
For purpose of the present invention, feature are become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is further described.
Please refer to Fig. 2, Fig. 2 is the process flow diagram of the method for testing of nonvolatile memory of the present invention.This nonvolatile memory comprise many word lines (wordline, WL), with these many word lines multiple bit lines (bitline, BL) and a plurality of non-volatile memory cells arranged in a crossed manner.These non-volatile memory cells are configured in each intersection point place of many word lines and multiple bit lines, and each non-volatile memory cells has floating grid and control gate.Method of testing of the present invention comprises following flow process:
S1: one group of non-volatile memory cells on selected any word line or the bit line.
S2: in this group non-volatile memory cells behind the odd bits non-volatile memory cells data writing, measure the first leakage current value I1, wherein the data that write of adjacent non-volatile memory cells are opposite.For example, concerning flash, first storage unit data writing (data " 0 "), second storage unit be data writing (data " 1 ") not, and by that analogy, the data of this group non-volatile memory cells are " 0101...0101 ".Concerning EEPROM, first storage unit data writing (data " 1 "), second storage unit be data writing (data " 0 ") not, and by that analogy, the data of this group non-volatile memory cells are " 1010...1010 ".After finishing writing data, can the consumption measurement unit measure total leakage current of this group storage unit, obtain the first leakage current value I1.Wherein, the measuring accuracy of this measurement unit reaches to receive pacifies level, and working temperature is 25 ℃ of normal temperature (usually, humidity elects 40% as).
S3: behind even bit non-volatile memory cells data writing in this group non-volatile memory cells, measure the second leakage current value I2.Similarly, concerning flash, first storage unit is data writing (data " 1 ") not, second storage unit data writing (data " 0 "), and by that analogy, the data of this group non-volatile memory cells are " 1010...1010 ".Concerning EEPROM, first storage unit is data writing (data " 0 ") not, second storage unit data writing (data " 1 "), and by that analogy, the data of this group non-volatile memory cells are " 0101...0101 ".After finishing writing data, same consumption measurement unit measures total leakage current of this group storage unit, obtains the second leakage current value I2.
S4: behind the equal data writing of this group non-volatile memory cells, measure the 3rd leakage current value I3.Concerning flash, whole equal data writings of storage unit (data " 0 "), the data of this group non-volatile memory cells are " 0000...0000 ".Concerning EEPROM, whole equal data writings of storage unit (data " 1 "), the data of this group non-volatile memory cells are " 1111...1111 ".After finishing writing data, same consumption measurement unit measures total leakage current of this group storage unit, obtains the 3rd leakage current value I3.
S5: whether the difference of judging the first leakage current value I1 and the second leakage current value I2 sum and the 3rd leakage current value I3 in permissible range, if not in permissible range, shows that then there is flaw in this nonvolatile memory, is not suitable for proceeding reliability testing.Particularly, this permissible range is for being not more than 1 microampere.If within permissible range, show that this group non-volatile memory cells does not all have flaw, circulation step S1～S5 then is until test all word lines or all bit lines of this nonvolatile memory.
When in the non-volatile memory cells data writing being arranged, accumulated electric charge in the floating grid, this storage unit is in cut-off state, and leakage current is larger, is generally microampere order.When not having data writing in the non-volatile memory cells, there is not electric charge in the floating grid, this storage unit is in conducting state, and leakage current is smaller, is generally to receive to pacify level.Thus, utilize above method, to record the first leakage current value I1 and the second leakage current value I2 among step S2 and the step S3 to this group non-volatile memory cells interval data writing, and be to record the 3rd leakage current value I3 among the step S3 to whole storage unit data writings, if there is flaw (being that nonvolatile memory exists flaw) in this group non-volatile memory cells, then when measuring the 3rd leakage current value I3 since all storage unit all end, the situations such as mutually electric leakage may appear between the storage unit, thereby cause the 3rd leakage current value I3 to become large or diminish, the first leakage current value I1 and the second leakage current value I2 sum can become and differ greatly with the 3rd leakage current value I3.If this group non-volatile memory cells does not all have flaw, then the first leakage current value I1 and the second leakage current value I2 sum should be close with the 3rd leakage current value I3, differ between the two and generally are not more than 1 microampere.
In addition, the sequencing of above step S2, S3 and S4 can exchange, and does not affect the enforcement of this method.Should be noted that, if what select is word-line direction, then with this method all word lines are circulated one time (owing to traveled through all storage unit, need not select in addition bit line direction to test), if the test result of every word line all be show do not have defective, then whole performance of non-volatile memory is good, does not have flaw.If what select is bit line direction, then with this method all bit lines are circulated one time (owing to traveled through all storage unit, need not select in addition word-line direction to test), if the test result of every bit lines all be show do not have defective, then whole performance of non-volatile memory is good, does not have flaw.
Thus, the method of testing of nonvolatile memory provided by the invention, one group of non-volatile memory cells on selected any word line or the bit line, respectively to the odd bits storage unit, even bit storage unit and whole storage unit data writing obtain the first corresponding leakage current value with measurement, the second leakage current value and the 3rd leakage current value, whether recently judge mutually with the 3rd leakage current value whether this nonvolatile memory exists flaw by comparing the first leakage current value with the second leakage current value sum, just can select thus the good storer of performance and carry out reliability testing, that guarantees to test carries out smoothly, and then assesses out exactly the use life-span.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (5)
1. the method for testing of a nonvolatile memory is used for judging whether described nonvolatile memory is fit to proceed reliability testing, and described nonvolatile memory comprises:
Many word lines;
With described many multiple bit lines that the word line is arranged in a crossed manner; And
A plurality of non-volatile memory cells, it is configured in each intersection point place of described many word lines and described multiple bit lines, and each non-volatile memory cells has floating grid and control gate,
It is characterized in that described method of testing comprises:
A, one group of non-volatile memory cells on selected any word line or the bit line;
B behind odd bits non-volatile memory cells data writing in described one group of selected non-volatile memory cells, measures the first leakage current value;
C behind even bit non-volatile memory cells data writing in described one group of selected non-volatile memory cells, measures the second leakage current value;
D behind described one group of selected equal data writing of non-volatile memory cells, measures the 3rd leakage current value;
E, in permissible range, if not in permissible range, then there is flaw in described nonvolatile memory to the difference of judging described the first leakage current value and described the second leakage current value sum and described the 3rd leakage current value, is not suitable for proceeding reliability testing,
Wherein, the order of step b, c, d can be exchanged, and described permissible range is for being not more than 1 microampere.
2. the method for testing of nonvolatile memory as claimed in claim 1 is characterized in that, if among the step e, judged result is within permissible range, and circulation step a～e then is until test all word lines or all bit lines of described nonvolatile memory.
3. the method for testing of nonvolatile memory as claimed in claim 1 is characterized in that, described nonvolatile memory is flash memory.
4. the method for testing of nonvolatile memory as claimed in claim 1 is characterized in that, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo).
5. the method for testing of nonvolatile memory as claimed in claim 1, it is characterized in that, adopt to measure described the first leakage current value of unit measuring, the second leakage current value and the 3rd leakage current value, the measuring accuracy of described measurement unit is for receiving the peace level, and working temperature is normal temperature.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1184330A (en) * | 1996-12-05 | 1998-06-10 | 三菱电机株式会社 | Semi-conductor memory device |
| US6331954B1 (en) * | 2001-06-28 | 2001-12-18 | Advanced Micro Devices, Inc. | Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells |
| CN101226778A (en) * | 2007-01-16 | 2008-07-23 | 松下电器产业株式会社 | Semiconductor memory having function to determine semiconductor low current |
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| JP2004227710A (en) * | 2003-01-24 | 2004-08-12 | Renesas Technology Corp | Semiconductor storage device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1184330A (en) * | 1996-12-05 | 1998-06-10 | 三菱电机株式会社 | Semi-conductor memory device |
| US6331954B1 (en) * | 2001-06-28 | 2001-12-18 | Advanced Micro Devices, Inc. | Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells |
| CN101226778A (en) * | 2007-01-16 | 2008-07-23 | 松下电器产业株式会社 | Semiconductor memory having function to determine semiconductor low current |
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