CN102136481B - Manufacture method of EEPROM (Electronically Erasable Programmable Read-Only Memory) device - Google Patents
Manufacture method of EEPROM (Electronically Erasable Programmable Read-Only Memory) device Download PDFInfo
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- CN102136481B CN102136481B CN 201010100501 CN201010100501A CN102136481B CN 102136481 B CN102136481 B CN 102136481B CN 201010100501 CN201010100501 CN 201010100501 CN 201010100501 A CN201010100501 A CN 201010100501A CN 102136481 B CN102136481 B CN 102136481B
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Abstract
The invention discloses a manufacture method of an EEPROM (Electronically Erasable Programmable Read-Only Memory) device. The method comprises the following steps of: firstly, growing a sacrificial oxidation layer injected by a high-pressure well and forming high-pressure well injection; then, removing the sacrificial oxidation layer, growing a high-pressure grid oxidation layer and forming a tunnelling window; then, depositing a floating grid, etching off the floating grid in a logic area, depositing an ONO (Oxide-Nitride-Oxide) (Silicon Oxide/Silicon Nitride/Silicon Oxide) dielectric layer, etching off the upper layer oxidation layer and the nitrification layer of the ONO in the logic area, using the remained bottom layer oxidation layer as a retaining layer injected by a low-pressure well to form low-pressure well injection, manufacturing a low-pressure device and etching out the ONO in the logic area; and finally growing a 5-V grid oxidation layer. Through the method, the invention prevents the trench injection of a low-pressure device from being exhausted due to the influence of the oxygen growth of the high-pressure grid so as to enhance the adjustability of the threshold voltage of the low-pressure device and simplify the process steps by directly adopting the oxidation layer of the ONO dielectric layer as the sacrificial oxidation layer of low-pressure well injection.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor memory, especially a kind of manufacture method of EEPROM device.
Background technology
In built-in EEPROM technique, need multiple device to realize various functions: in 0.18um technique, 1.8V is as logical device, and 5V is as the input/output port device, and 18V is as the high tension apparatus of realizing the EEPROM operation.The device of integrated different voltages and eeprom memory spare are the significant challenge of in-line memory technique.
Traditional built-in EEPROM technique, the height kill-job is injected and is utilized same sacrificial oxide layer.Sacrificial oxide layer injects at well and finishes rear the removal, and the high-pressure gate oxide of then growing respectively forms tunneling window, floating boom and ONO (silicon oxide/silicon nitride/silicon oxide) dielectric layer, forms at last the gate oxide of logic low voltage device.This mode can make the Channeling implantation of low-voltage device be subject to the high-pressure gate oxide affects on the growth and exhaust, and causes the threshold voltage of low-voltage device to be difficult to regulate, and is final so that component failure.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method of EEPROM device, can adopt simple and convenient step, avoids the manufacture craft mesohigh well of EEPROM device to inject and low pressure well injection impact each other, improves device reliability.
For solving the problems of the technologies described above, the technical scheme of the manufacture method of EEPROM device of the present invention is wherein to include successively following steps:
At first, the sacrificial oxide layer that growth one deck high-pressure well injects forms the high-pressure well that is arranged in P type substrate and injects;
Then, remove this sacrificial oxide layer, the growth high voltage grid oxidation layer, the high voltage grid oxidation layer above high-pressure well injects forms tunneling window;
Afterwards, the deposit floating boom etches away floating boom at the logic area that is positioned at the high-pressure well injection zone outside, deposit ono dielectric layer again, the silicon oxide layer on logic area etches away being positioned at of ono dielectric layer and middle silicon nitride layer, the silicon oxide layer of the bottom that stays;
At last, the sacrificial oxide layer that the silicon oxide layer that is positioned at bottom in the ono dielectric layer that logic area is not etched away injects as the logic area low pressure well forms low pressure well and injects, and makes low-voltage device.
The present invention passes through said method, just kill-job is carried out after injecting and being placed on the high-pressure gate oxide growth, avoided the Channeling implantation of low-voltage device to be subject to the high-pressure gate oxide affects on the growth and exhausted, thereby strengthened the threshold voltage controllability of low-voltage device, and directly adopt the silicon oxide layer of ono dielectric layer as the sacrificial oxide layer that low pressure well injects, simplified processing step.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the schematic diagram of the sacrificial oxide layer that the growth high-pressure well injects among the present invention;
Fig. 2 be grow among the present invention high voltage grid oxidation layer, form the schematic diagram of tunneling window;
Fig. 3 is the schematic diagram after the deposit ono dielectric layer among the present invention;
Fig. 4 carries out etching schematic diagram afterwards to the ono dielectric layer among the present invention;
Fig. 5 is the schematic diagram of growth 5V gate oxide among the present invention.
Embodiment
The invention provides a kind of manufacture method of EEPROM device, such as Fig. 1～shown in Figure 5, wherein include successively following steps:
At first, the sacrificial oxide layer that growth one deck high-pressure well injects forms the high-pressure well that is arranged in P type substrate and injects;
Then, remove this sacrificial oxide layer, the growth high voltage grid oxidation layer, the high voltage grid oxidation layer above high-pressure well injects forms tunneling window;
Afterwards, the deposit floating boom etches away floating boom at the logic area that is positioned at the high-pressure well injection zone outside, deposit ono dielectric layer again, the silicon oxide layer on logic area etches away being positioned at of ono dielectric layer and middle silicon nitride layer, the silicon oxide layer of the bottom that stays;
At last, the sacrificial oxide layer that the silicon oxide layer that is positioned at bottom in the ono dielectric layer that logic area is not etched away injects as the logic area low pressure well forms low pressure well and injects, and makes low-voltage device.
The thickness of the sacrificial oxide layer that described high-pressure well injects is
The thickness of described high voltage grid oxidation layer is
The thickness of described floating boom is
The present invention passes through said method, just kill-job is carried out after injecting and being placed on the high-pressure gate oxide growth, avoided the Channeling implantation of low-voltage device to be subject to the high-pressure gate oxide affects on the growth and exhausted, thereby strengthened the threshold voltage controllability of low-voltage device, and directly adopt the silicon oxide layer of ono dielectric layer as the sacrificial oxide layer that low pressure well injects, simplified processing step.
Claims (4)
1. the manufacture method of an EEPROM device is characterized in that, wherein includes successively following steps:
At first, the sacrificial oxide layer that growth one deck high-pressure well injects forms the high-pressure well that is arranged in P type substrate and injects;
Then, remove this sacrificial oxide layer, the growth high voltage grid oxidation layer, the high voltage grid oxidation layer above high-pressure well injects forms tunneling window;
Afterwards, the deposit floating boom etches away floating boom at the logic area that is positioned at the high-pressure well injection zone outside, and deposit ono dielectric layer etches away the silicon oxide layer that is positioned at the upper strata of ono dielectric layer and the silicon nitride layer of centre, the silicon oxide layer of the bottom that stays at logic area again;
At last, the sacrificial oxide layer that the silicon oxide layer that is positioned at bottom in the ono dielectric layer that logic area is not etched away injects as the logic area low pressure well forms low pressure well and injects, and makes low-voltage device.
2. the manufacture method of EEPROM device according to claim 1 is characterized in that, the thickness of the sacrificial oxide layer that described high-pressure well injects is
3. the manufacture method of EEPROM device according to claim 1 is characterized in that, the thickness of described high voltage grid oxidation layer is
4. the manufacture method of EEPROM device according to claim 1 is characterized in that, the thickness of described floating boom is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010100501 CN102136481B (en) | 2010-01-25 | 2010-01-25 | Manufacture method of EEPROM (Electronically Erasable Programmable Read-Only Memory) device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010100501 CN102136481B (en) | 2010-01-25 | 2010-01-25 | Manufacture method of EEPROM (Electronically Erasable Programmable Read-Only Memory) device |
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| CN102136481A CN102136481A (en) | 2011-07-27 |
| CN102136481B true CN102136481B (en) | 2013-03-13 |
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| CN1787206A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. flash memory |
| CN100490123C (en) * | 2006-10-23 | 2009-05-20 | 上海华虹Nec电子有限公司 | Making technology method for flash memory |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |