CN102136458A - Improved structure aimed at BOAC framework - Google Patents
Improved structure aimed at BOAC framework Download PDFInfo
- Publication number
- CN102136458A CN102136458A CN2011100450230A CN201110045023A CN102136458A CN 102136458 A CN102136458 A CN 102136458A CN 2011100450230 A CN2011100450230 A CN 2011100450230A CN 201110045023 A CN201110045023 A CN 201110045023A CN 102136458 A CN102136458 A CN 102136458A
- Authority
- CN
- China
- Prior art keywords
- bond pad
- dielectric layer
- metal gasket
- boac
- framework
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides an improved structure aimed at a BOAC framework, which comprises an active circuit and a bond pad structure arranged above the active circuit. The bond pad structure comprises a bond pad, a passivation layer, and a first metal gasket. The bond pad is arranged on a first dielectric layer; the passivation layer is covered on the periphery of the bond pad so as to form an opening area on above the bond pad; and the first metal gasket is arranged in a second dielectric layer and is arranged on the periphery of a corresponding right under the opening area. As an original metal gasket in an area right under the opening area of a bond pad of the prior art is changed into a dielectric medium material with larger mechanical strength by the improved structure, then mechanical pressure formed in the opening area during subsequent packaging process can be absorbed and born by the dielectric medium material; in this way, collapse of the bond pad and the metal gasket caused by external mechanical pressure can be effectively prevented so as to avoid the active circuit below from damaging; therefore, redundant electric property connection formed by the active circuit can be prevented; therefore, the failure rate of the active circuit is reduced, and the product yield is improved.
Description
Technical field
The present invention relates to a kind of integrated circuit technology manufacturing technology, relate in particular to a kind of improvement structure at the BOAC framework, this improvement structure can be born bond pad structure than great machinery pressure what efficient circuit (Active Circuit) go up to form.
Background technology
Along with the fast development of integrated circuit technology manufacturing industry, the current densities and the complexity of integrated circuit improve significantly, and the package dimension of following also significantly reduces.Development of technology is come together is that quick operation, cost to semiconductor device reduces and the increase of higher reliability requirement.Going up the more individual semiconductor die of formation at wafer (Wafer), is crucial to above-mentioned Technical Development Requirement.
For reducing the size of chip (Chip), expectation is directly put on effective circuit and is formed bond pad (Bonding Pad).BOAC (Bonding over active circuit) framework is that bond pad structure is set directly on the multilayer efficient circuit; for example be positioned at I/O (I/O circuit) or static discharge (ElectroStatic Discharge; ESD) on the protective circuit; in order to save chip area, reduce cost of manufacture.
Fig. 1 is the brief configuration schematic diagram of a kind of BOAC framework in the prior art, as shown in Figure 1, form described efficient circuit 10 on Semiconductor substrate, and directly form bond pad structure above described efficient circuit 10, bond pad structure is electrical connected by being communicated with lead 13 with efficient circuit.Described bond pad structure comprises: first dielectric layer 23 and second dielectric layer 24 that is positioned at first dielectric layer, 23 belows; Bond pad 21 is formed on first dielectric layer 23; Passivation layer 22 is formed at first dielectric layer, 23 tops and covers the periphery of described bond pad 21, exposes opening 30 above bond pad 21; Metal gasket 25, be arranged in second dielectric layer 24, electrically communicate by conductive through hole 26 with bond pad, described metal gasket 25 be positioned at comprise under the bond pad 21 opening part over against the zone all have metal gasket 25, metal gasket 25 is used for the electrical communication efficient circuit and bears the mechanical pressure that opening part is received in encapsulation process.Yet, there is following defective in said structure in encapsulation process: the opening part 30 that presses bond pad 21 at CP test process middle probe, the mechanical pressure of wayward size easily causes weighing wounded the metal gasket of bond pad 30 and below thereof, causes metal gasket to subside; Equally in encapsulation (Package) process, during for example at the encapsulation of copper cash, wire-bonded or spun gold are spherical to need bigger bonding force in conjunction with in the engaging processes such as (Gold Ball), inevitably need be by external force, cause its following metal gasket breakage to be subsided equally easily, damage efficient circuit 10, even metal gasket 25 that subsides and the unnecessary electric connection of efficient circuit 10 generations cause chip failure, cause the yield of product test and encapsulation to reduce, influence the volume production requirement.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of improvement structure at the BOAC framework, to prevent in encapsulation process the damage that mechanical pressure causes efficient circuit.
For addressing the above problem, the invention provides a kind of improvement structure at the BOAC framework, comprise efficient circuit and the bond pad structure that is arranged at the efficient circuit top, described bond pad structure comprises:
First dielectric layer and be positioned at second dielectric layer under it;
Bond pad is arranged on described first dielectric layer;
Passivation layer is arranged on described first dielectric layer and is covered in described bond pad periphery, to form open region above described bond pad;
First metal gasket, be arranged in described second dielectric layer, and be positioned at the periphery of corresponding region under the described open region, described first metal gasket and described bond pad are electrical connected by first conductive through hole, and wherein said first conductive through hole is formed in described first dielectric layer.
Further, be positioned at that the material of corresponding region is silica, silicon nitride, boron-phosphorosilicate glass, fluorine silex glass, phosphorosilicate glass or its combination under the described open region in described second dielectric layer.
Further, described first conductive through hole and described bond pad are formed in one.
Further, the material of described bond pad is tungsten, aluminium, copper or its combination.
Further, the material of described first metal gasket is nickel, cobalt, aluminium, copper or its combination.
Further, described bond pad structure also comprises the 3rd dielectric layer and second metal gasket, described second metal gasket is arranged in described the 3rd dielectric layer, and be positioned at the periphery of corresponding region under the described open region, described second metal gasket and described first metal gasket are electrical connected by second conductive through hole, and wherein said second conductive through hole is formed in described second dielectric layer.
Further, be positioned at that the material of corresponding region is silica, silicon nitride, boron-phosphorosilicate glass, fluorine silex glass, phosphorosilicate glass or its combination under the described open region in described the 3rd dielectric layer.
Further, described second conductive through hole and described first metal gasket are formed in one.
Further, the material of described second metal gasket is nickel, cobalt, aluminium, copper or its combination.
In sum, the present invention replaces with the bigger dielectric substance of mechanical strength with the original metal gasket in the zone under the bond pad openings district in the prior art, then the mechanical pressure that forms in follow-up encapsulation process split shed district can and be born by the dielectric substance absorption, prevent that effectively extraneous mechanical pressure from causing bond pad and metal gasket to cave in, the efficient circuit of damage below, and then prevent that efficient circuit from forming unnecessary electrical connection, and reduce the efficient circuit failure rate, improve the product yield.
Description of drawings
Fig. 1 is the brief configuration schematic diagram of a kind of BOAC framework in the prior art.
Fig. 2 is the schematic diagram of the improvement structure of BOAC framework in one embodiment of the invention.
Fig. 3 is the schematic diagram of the improvement structure of BOAC framework in another embodiment of the present invention.
Embodiment
For making content of the present invention clear more understandable,, content of the present invention is described further below in conjunction with Figure of description.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Explain embodiments of the invention according to accompanying drawing, in specification of the present invention and accompanying drawing, illustrated which floor of the top layer of metal level and below thereof among the figure, metal level can be multilayer, for example between 2 to 8, other metal levels omit in the drawings, but are not restricted to the accompanying drawing statement.
In embodiments of the present invention; Fig. 2 is the schematic diagram of the improvement structure of BOAC framework in one embodiment of the invention; as shown in Figure 2; described improvement structure at the BOAC framework comprises efficient circuit 100 and directly is arranged at the bond pad structure of efficient circuit top; wherein said efficient circuit 100 can comprise I/O (I/O circuit) or static discharge (ElectroStatic Discharge; ESD) protective circuit; wherein each efficient circuit can be made up of a plurality of semiconductor subassemblies; semiconductor subassembly 102 as MOSFETS (Metal-Oxide-SemiconductorField-Effect Transistors, mos field effect transistor) is arranged on the first type surface of Semiconductor substrate (Substrate) 100.
Wherein said bond pad structure comprises: first dielectric layer 203 and be positioned at second dielectric layer 204, bond pad 201, passivation layer 202, first metal gasket 205 and conductive through hole 206 under it.Wherein:
First dielectric layer 203 and be positioned at second dielectric layer 204 under it; Described first dielectric layer 203, second dielectric layer 204 are the dielectric layer of metal interlevel, wherein can also have the dielectric layer of more metal interlevels, omit in the accompanying drawings.Wherein first dielectric layer 203, second dielectric layer 204 can be by low-k (Low-K, K value can less than 4), or ultralow dielectric (Ultra Low-K, K value can less than 2.5) material forms, but is not limited thereto.The material of first dielectric layer 203, second dielectric layer 204 can be the dielectric material as silica, silicon nitride, boron-phosphorosilicate glass, fluorine silex glass or phosphorosilicate glass or its combination etc.
Fig. 3 is the schematic diagram of the improvement structure of BOAC framework in further embodiment of this invention, as shown in Figure 4, described bond pad structure is on the basis of structural representation shown in Figure 2, also comprise the 3rd dielectric layer 207 and second metal gasket 208, described second metal gasket 208 is arranged in described the 3rd dielectric layer 107, and be positioned at the periphery of corresponding region under the described open region 300, the zone that is second dielectric layer 204 of correspondence under the described open region 300 does not have second metal gasket 208, described second metal gasket 208 is electrical connected by second conductive through hole 209 with described first metal gasket 205, wherein said second conductive through hole 206 is formed in described second dielectric layer, can form simultaneously with first metal gasket 205; Second conductive through hole 206 can be square or bar shaped, and second conductive through hole 209 can comprise a plurality of, to improve conductivity, can reduce resistance.The material of described conductive through hole 206 is identical with the material of described bond pad 201.Further, be positioned at that the material of corresponding region is silica, silicon nitride, boron-phosphorosilicate glass, fluorine silex glass, phosphorosilicate glass or its combination under the described open region 300 in described the 3rd dielectric layer 204.The 3rd dielectric layer 204 can further improve the mechanical pressure ability to bear, and protection efficient circuit 100 improves the product yield.
In sum, the present invention replaces with the bigger dielectric substance of mechanical strength with the original metal gasket in the zone under the bond pad openings district in the prior art, then the mechanical pressure that forms in follow-up encapsulation process split shed district can and be born by the dielectric substance absorption, prevent that effectively extraneous mechanical pressure from causing bond pad and metal gasket to cave in, the efficient circuit of damage below, and then prevent that efficient circuit from forming unnecessary electrical connection, and reduce the efficient circuit failure rate, improve the product yield.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (9)
1. the improvement structure at the BOAC framework comprises efficient circuit and the bond pad structure that is arranged at the efficient circuit top, it is characterized in that described bond pad structure comprises:
First dielectric layer and be positioned at second dielectric layer under it;
Bond pad is arranged on described first dielectric layer;
Passivation layer is arranged on described first dielectric layer and is covered in described bond pad periphery, to form open region above described bond pad;
First metal gasket, be arranged in described second dielectric layer, and be positioned at the periphery of corresponding region under the described open region, described first metal gasket and described bond pad are electrical connected by first conductive through hole, and wherein said first conductive through hole is formed in described first dielectric layer.
2. the improvement structure at the BOAC framework as claimed in claim 1, it is characterized in that, be positioned at that the material of corresponding region is silica, silicon nitride, boron-phosphorosilicate glass, fluorine silex glass, phosphorosilicate glass or its combination under the described open region in described second dielectric layer.
3. the improvement structure at the BOAC framework as claimed in claim 1 is characterized in that described first conductive through hole and described bond pad are formed in one.
4. the improvement structure at the BOAC framework as claimed in claim 1 is characterized in that, the material of described bond pad is tungsten, aluminium, copper or its combination.
5. the improvement structure at the BOAC framework as claimed in claim 1 is characterized in that, the material of described first metal gasket is nickel, cobalt, aluminium, copper or its combination.
6. the improvement structure at the BOAC framework as claimed in claim 1, it is characterized in that, described bond pad structure also comprises the 3rd dielectric layer and second metal gasket, described second metal gasket is arranged in described the 3rd dielectric layer, and be positioned at the periphery of corresponding region under the described open region, described second metal gasket and described first metal gasket are electrical connected by second conductive through hole, and wherein said second conductive through hole is formed in described second dielectric layer.
7. the improvement structure at the BOAC framework as claimed in claim 6, it is characterized in that, be positioned at that the material of corresponding region is silica, silicon nitride, boron-phosphorosilicate glass, fluorine silex glass, phosphorosilicate glass or its combination under the described open region in described the 3rd dielectric layer.
8. the improvement structure at the BOAC framework as claimed in claim 6 is characterized in that, described second conductive through hole and described first metal gasket are formed in one.
9. the improvement structure at the BOAC framework as claimed in claim 6 is characterized in that, the material of described second metal gasket is nickel, cobalt, aluminium, copper or its combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100450230A CN102136458A (en) | 2011-02-24 | 2011-02-24 | Improved structure aimed at BOAC framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100450230A CN102136458A (en) | 2011-02-24 | 2011-02-24 | Improved structure aimed at BOAC framework |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102136458A true CN102136458A (en) | 2011-07-27 |
Family
ID=44296192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100450230A Pending CN102136458A (en) | 2011-02-24 | 2011-02-24 | Improved structure aimed at BOAC framework |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102136458A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447837A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307363A (en) * | 2000-01-12 | 2001-08-08 | 三菱电机株式会社 | Semiconductor device and its manufacture, chemical-mechanical grinding device and method |
| CN1652329A (en) * | 2004-02-05 | 2005-08-10 | 松下电器产业株式会社 | Semiconductor device |
| JP2005236277A (en) * | 2004-01-22 | 2005-09-02 | Kawasaki Microelectronics Kk | Semiconductor integrated circuit |
| JP2007214349A (en) * | 2006-02-09 | 2007-08-23 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
-
2011
- 2011-02-24 CN CN2011100450230A patent/CN102136458A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307363A (en) * | 2000-01-12 | 2001-08-08 | 三菱电机株式会社 | Semiconductor device and its manufacture, chemical-mechanical grinding device and method |
| JP2005236277A (en) * | 2004-01-22 | 2005-09-02 | Kawasaki Microelectronics Kk | Semiconductor integrated circuit |
| CN1652329A (en) * | 2004-02-05 | 2005-08-10 | 松下电器产业株式会社 | Semiconductor device |
| JP2007214349A (en) * | 2006-02-09 | 2007-08-23 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447837A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12074121B2 (en) | Metal-free frame design for silicon bridges for semiconductor packages | |
| KR101828063B1 (en) | Semiconductor device and method of forming the same | |
| US11676889B2 (en) | Guard ring design enabling in-line testing of silicon bridges for semiconductor packages | |
| US7696631B2 (en) | Wire bonding personalization and discrete component attachment on wirebond pads | |
| US9997480B2 (en) | Method of forming a semiconductor device including strain reduced structure | |
| US8138616B2 (en) | Bond pad structure | |
| US8772943B2 (en) | Offset of contact opening for copper pillars in flip chip packages | |
| US20230154894A1 (en) | Three-dimensional integrated circuit structure and a method of fabricating the same | |
| US20220336303A1 (en) | Semiconductor structure and method of forming | |
| US20220045000A1 (en) | Semiconductor device and fabrication method for the same | |
| CN111223819A (en) | Semiconductor structure and manufacturing method thereof | |
| CN102136458A (en) | Improved structure aimed at BOAC framework | |
| US20070215993A1 (en) | Chip Package Structure | |
| US8658466B2 (en) | Semiconductor package structure and method for making the same | |
| JP2007258381A (en) | Semiconductor apparatus and manufacturing method thereof | |
| US20150145119A1 (en) | Integrated Circuit And Fabricating Method Thereof | |
| US9691671B2 (en) | Test key array | |
| CN102184904A (en) | Bonding disc structure aiming at BOAC frame and integrated circuit device structure | |
| KR20060130105A (en) | Efficient use of wafer area with device under the pad approach | |
| KR20240090500A (en) | Electronic component package and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110727 |