CN102136417B - Method for manufacturing semiconductor device - Google Patents
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- CN102136417B CN102136417B CN 201010102418 CN201010102418A CN102136417B CN 102136417 B CN102136417 B CN 102136417B CN 201010102418 CN201010102418 CN 201010102418 CN 201010102418 A CN201010102418 A CN 201010102418A CN 102136417 B CN102136417 B CN 102136417B
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Abstract
The invention provides a method for manufacturing a semiconductor device, which comprises the following steps of: providing a substrate, and forming a layer of gate oxide on the substrate; forming a grid on the gate oxide; depositing and etching on the side wall of the gate oxide and the side wall of the grid to form an interval wall insulation layer; depositing and etching on the side wall of the interval wall insulation layer to form an interval wall layer; performing an ion implantation process on the substrate to form a source/drain; forming a titanium nitride layer on the substrate, the grid, the interval wall insulation layer and the interval wall layer; forming a nickel layer on the surface of the titanium nitride layer; performing the ion implantation process on the nickel layer; performing a first annealing process on the substrate, forming a nickel disilicide layer in the substrate below the titanium nitride layer, and removing the residual nickel layer and titanium nitride layer above the titanium nitride layer; and performing a second annealing process on the substrate, so that the nickel disilicide layer is reacted with the substrate to form a nickel silicide layer. According to the method, the phenomenon of 'nickel erosion' can be overcome effectively.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly methods of making semiconductor devices.
Background technology
The technical development of micro-dimension semiconductor device needs the method for improved conduction contact for the manufacture of the semiconductor impurities district.Metal silicide has proved excellent contact material, and it is easy to form with self-aligned manner by silication technique for metal.
Form the metal silicide contact by silication technique for metal and generally include the following step: deposition contains the thin metal layer (for example thickness is less than 15nm) of silicide metals or the metal alloy metal or metal alloy of metal silicide (thereby can form with pasc reaction) equably on the Semiconductor substrate that comprises siliceous device region and dielectric isolation, thereby heat this Semiconductor substrate and on device region, form silicide, and optionally etch away unreacted metal from dielectric isolation then.
In the known metal self-aligned silicide process, often adopt cobalt silicide, be used for the following technology of 250nm.Yet, in the technology of the ultra tiny circuit below 42nm, if use cobalt silicide as ultra tiny polysilicon gate, source electrode and drain electrode, can cause so-called agglomeration, therefore must seek other substitution material.Utilize the formed ultra tiny polysilicon gate of nickle silicide, source electrode and drain electrode in the prior art, owing to have lower resistance, less leakage current, less silicon consumption, and can promote the transistorized drive current of MOS (metal-oxide semiconductor (MOS)), thereby can address the above problem.
Particularly, shown in Figure 1A to 1E, form the method for semiconductor device for the method for traditional employing self-aligned silicide technology.
Shown in Figure 1A, substrate 100 is provided, comprise shallow channel isolation area (STI) 101, a plurality of field oxide region (not shown) and be pre-formed in wherein N trap or P trap (not shown).Substrate 101 surfaces have one deck gate oxide 102, are formed with one deck polysilicon layer 103 on the gate oxide 102.Carry out light dope technology, form LDD district 104A and 104B.
As shown in Figure 1B, deposit and etching formation clearance wall insulating barrier 105A and 105B at the sidewall of gate oxide 102 with polysilicon layer 103, on the sidewall of clearance wall insulating barrier 105A and 105B, deposit respectively then and etching formation gap parietal layer 106A and 106B.Then, carry out ion implantation technology, formation source/drain electrode 107A and 107B.
Shown in Fig. 1 C, at total surface deposition one deck titanium nitride layer 108, then form one deck nickel dam 109 on the surface of titanium nitride layer 108, material can be chosen as pure nickel or nickel alloy.
Shown in Fig. 1 D, first annealing process is carried out in the substrate 101 with nickel dam 109, first annealing process can be chosen as under 300～380 degrees centigrade first temperature and carry out.Nickel dam 109 reacts with the silicon on source/drain electrode 107A and 107B surface, forms silication two nickel dams 110 with less resistive.Utilize the unreacted nickel dam 109 of etching technics selective removal and titanium nitride layer 108, in order to expose gap parietal layer 106A and 106B, polysilicon layer 103 and shallow trench isolation regions 101.
Shown in Fig. 1 E, carry out second annealing process, in the source/surface of drain electrode 107A and 107B forms nickel silicide layer 111.
Finally by later continuous intraconnections process, finish the making of MOS transistor.
But, the defective of " nickel erosion " in the self-aligned silicide technology of traditional employing nickel dam 109, can appear, and namely after annealing process, finding that nickel is diffused into should be not where.Shown in Fig. 2 A, nickel invades 201 zones below the grid 103.Shown in Fig. 2 B, be the defects detection figure of semiconductor device with " nickel erosion " defective, as we can see from the figure, the surface of the semiconductor device that traditional nickel self-aligned silicide process is made has a lot " nickel erosion " defective, shown in 202 zones.
Therefore, need a kind of method, can overcome " nickel erosion " phenomenon effectively, in order to improve the overall performance of semiconductor device, improve yields.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to overcome " nickel erosion " phenomenon effectively, the present invention proposes a kind of methods of making semiconductor devices, comprise step: provide a substrate; Form one deck gate oxide in described substrate; Form grid at described gate oxide; Form the clearance wall insulating barrier at the sidewall of described gate oxide and sidewall deposition and the etching of described grid; Sidewall deposition and etching at described clearance wall insulating barrier form the gap parietal layer; Ion implantation technology is carried out in described substrate, formation source/drain electrode; Form one deck titanium nitride layer at described substrate, described grid, described clearance wall insulating barrier and described gap parietal layer; Surface at described titanium nitride layer forms one deck nickel dam; Described nickel dam is carried out ion implantation technology; First annealing process is carried out in described substrate, form silication two nickel dams in the described substrate under described titanium nitride layer and remove remaining nickel dam and described titanium nitride layer on the described titanium nitride layer; Second annealing process is carried out in described substrate, make described silication two nickel dams and described substrate reaction, form nickel silicide layer.
It is preferably, described that described nickel dam is carried out the ion that ion implantation technology adopts is silicon ion.
It is preferably, described that described nickel dam is carried out the injection energy range that ion implantation technology adopts is 40～50Kev.
It is preferably, described that described nickel dam is carried out the injection energy range that ion implantation technology adopts is 43～48Kev.
It is preferably, described that described nickel dam is carried out the injection energy range that ion implantation technology adopts is 45Kev.
It is preferably, described that described nickel dam is carried out the implantation dosage that ion implantation technology adopts is 7 * 10
14～11 * 10
14Cm
-2
Preferably, described to described nickel dam carry out implantation dosage that ion implantation technology adopts be 9 *
14Cm
-2
According to the present invention, can overcome " nickel erosion " phenomenon effectively, improve the overall performance that semiconductor device is produced, improve yields.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 E is the cross-sectional view that the method for traditional employing self-aligned silicide technology forms semiconductor device;
Fig. 2 A is the TEM figure with semiconductor device of " nickel erosion " defective;
Fig. 2 B is the defects detection figure with semiconductor device of " nickel erosion " defective;
Fig. 3 A to 3F is the cross-sectional view that forms semiconductor device according to the method for employing self-aligned silicide technology of the present invention;
Fig. 4 is the defects detection figure of semiconductor device according to an embodiment of the invention;
Fig. 5 is the leakage current of semiconductor device according to an embodiment of the invention and the comparison diagram of the leakage current of the semiconductor device of making according to traditional handicraft;
Fig. 6 is the semiconductor device technology flow chart of making according to the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that explanation the present invention is problem how to eliminate " nickel erosion " defective.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Make the problem that the MOS device uses " the nickel erosion " of adopting the nickel alloy appearance in the self-aligned silicide technology in order to overcome, the present invention proposes to inject silicon ion after deposited nickel layer.With reference to Fig. 3 A to Fig. 3 G, illustrate according to one embodiment of present invention and after deposited nickel layer, to inject silicon ion with the cutaway view of semiconductor device 300 each steps of manufacture craft of avoiding " nickel erosion " defective.
As shown in Figure 3A, provide substrate 300, can be but be not limited to monocrystalline silicon, polysilicon and silicon-on-insulator etc., comprise shallow channel isolation area (STI) 301, a plurality of field oxide region (not shown) and be pre-formed in wherein N trap or P trap (not shown).Have one deck gate oxide 302 in the substrate 300, can be chosen as and utilize oxidation technology temperature in the oxygen steam ambient to form gate oxide 302 down about 800～1000 degrees centigrade.Be formed with grid 303 on the gate oxide 302, material can be chosen as polysilicon, and the mode that forms grid 303 can adopt the chemical vapor deposition (CVD) method.Carry out light dope technology then, form LDD district 304A and 304B.
Then, shown in Fig. 3 B, at sidewall deposition and etching formation clearance wall insulating barrier 305A and the 305B of gate oxide 302 with grid 303, material can be but be not limited to silicon nitride.Deposit respectively on the sidewall of clearance wall insulating barrier 305A and 305B then and etching formation gap parietal layer 306A and 306B, material can be but be not limited to silicon nitride.Then, carry out ion and inject, inject n type foreign ion or p-type foreign ion, formation source/drain electrode 307A and 307B.Carry out annealing process then, the foreign ion of activation of source/ drain electrode 307A and 307B can carry out the annealing process of source/ drain electrode 307A and 307B by rta technique under 830～1150 degrees centigrade temperature.
Then, shown in Fig. 3 C, clean the surface at the semiconductor-based end 300 of having finished source/ drain electrode 307A and 307B annealing process in order to remove natural oxide layer and the contamination particle that remains on source/drain electrode 307A and the 307B.At total surface deposition one deck titanium nitride layer 308, the effect of titanium nitride layer 308 is to prevent nickel dam 309 oxidations that next will deposit.Then form one deck nickel dam 309 on the surface of titanium nitride layer 308.Material can be chosen as pure nickel or nickel alloy.Particularly, nickel alloy can comprise at least a material of selecting, for example NiPt from the group that Ta, Zr, Ti, Hf, W, Co, Pt, Mo, V and Nb constitute.When the material of nickel dam 309 is nickel alloy, can improve the thermal stability of the nickel alloy silicide layer that in technology subsequently, will form.Can utilize CVD or sputtering method to form nickel dam 309.
Next, shown in Fig. 3 D, nickel dam 309 is carried out ion implantation technology.The ion of selecting for use is silicon ion, and the injection energy range of selecting for use is 40～50Kev, is preferably 43～48Kev, 45Kev more preferably, and the implantation dosage of selecting for use is 7 * 10
14～11 * 10
14Cm
-2, be preferably 9 * 10
14Cm
-2
Then, shown in Fig. 3 E, first annealing process is carried out in the substrate 300 with nickel dam 309, first annealing process can be chosen as under 300～380 degrees centigrade first temperature and carry out.Nickel dam 309 reacts with the silicon on source/ drain electrode 307A and 307B surface, forms silication two nickel dams 310 with less resistive in the substrate 300 under titanium nitride layer 308.Then, utilize wet etching to remove unreacted nickel dam 309 and titanium nitride layer 308, in order to expose gap parietal layer 306A and 306B, grid 303 and shallow trench isolation regions 301.Can utilize the mixed solution of sulfuric acid and hydrogen peroxide to remove unreacted nickel dam 309 and titanium nitride layer 308.
Then, as Fig. 3 F, carry out second annealing process with the substrate 301 of titanium nitride layer 308 having removed unreacted nickel dam 309.Second annealing process preferably carries out under second temperature higher than first temperature, make silication two nickel dams 310 further with substrate 301 in silicon react, in the source/ drain electrode 307A and 307B formed the nickel silicide layer 311 with thermal stability, can utilize sputter equipment or rapidly the thermal annealing device carry out second annealing process.Then through follow-up intraconnections process, finish the making of MOS transistor.
To detecting according to present embodiment manufactured samples sheet,, as shown in Figure 4, be significantly less than quantity according to traditional handicraft manufactured samples sheet defective according to the defects count of present embodiment manufactured samples sheet, phenomenon that this explanation nickel corrodes has obtained remarkable improvement.This is owing to select for use silicon ion to inject, and the silicon that has imperfect key below silicon ion and the grid reacts, and to avoid reacting " nickel erosion " defective that causes owing to nickel in the annealing process and this part silicon, has improved the yields of semiconductor device.After testing, yields has improved about 3%.Another beneficial effect that brings according to embodiments of the invention is that the leakage current of semiconductor device has reduced.As shown in Figure 5, leakage current has approximately reduced two orders of magnitude, for example from 10
-9A/ μ m has been reduced to 10
-11A/ μ m.The energy has been saved in the reduction that reduces to be of value to the semiconductor device power consumption of leakage current.
The flow chart of Fig. 6 shows making injects to eliminate " nickel erosion " defective according to the employing silicon ion of the embodiment of the invention semiconductor device technology flow chart.In step 601, a substrate is provided, have a layer gate oxide in the substrate, be formed with grid on the gate oxide, carry out light dope technology then, form the LDD district.In step 602, at sidewall deposition and the etching formation clearance wall insulating barrier of gate oxide and grid.In step 603, sidewall deposition and etching formation gap parietal layer at the clearance wall insulating barrier then carry out ion implantation technology, and annealing process is carried out, the foreign ion of activation of source/drain electrode then in formation source/drain electrode.In step 604, at total surface deposition one deck titanium nitride layer, form one deck nickel dam on the surface of titanium nitride layer.In step 605, nickel dam is carried out the silicon ion injection technology.In step 606, first annealing process is carried out in the substrate with nickel dam, form silication two nickel dams with less resistive.In step 607, remove unreacted nickel dam and titanium nitride layer, in order to expose gap parietal layer and grid.In step 608, carry out second annealing process in the substrate of having removed unreacted nickel dam and titanium nitride layer, formed the nickel silicide layer with thermal stability in source/drain electrode.Then through follow-up intraconnections process, finish the making of MOS transistor.
The employing silicon injection technology of making according to aforesaid embodiment can be applicable in the multiple integrated circuit (IC) with the semiconductor device of eliminating " nickel erosion " defective.For example be memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (8)
1. methods of making semiconductor devices comprises step:
One substrate is provided;
Form one deck gate oxide in described substrate;
Form grid at described gate oxide;
Form the clearance wall insulating barrier at the sidewall of described gate oxide and sidewall deposition and the etching of described grid;
Sidewall deposition and etching at described clearance wall insulating barrier form the gap parietal layer;
Ion implantation technology is carried out in described substrate, formation source/drain electrode;
Form one deck titanium nitride layer at described substrate, described grid, described clearance wall insulating barrier and described gap parietal layer;
Surface at described titanium nitride layer forms one deck nickel dam;
Described nickel dam is carried out ion implantation technology, and the ion that adopts is silicon ion;
First annealing process is carried out in described substrate, form silication two nickel dams in the described substrate under described titanium nitride layer;
Remove remaining nickel dam and described titanium nitride layer on the described titanium nitride layer;
Second annealing process is carried out in described substrate, make described silication two nickel dams and described substrate reaction, form nickel silicide layer.
2. the method for claim 1 is characterized in that, described described nickel dam is carried out the injection energy range that ion implantation technology adopts is 40～50Kev.
3. the method for claim 1 is characterized in that, described described nickel dam is carried out the injection energy range that ion implantation technology adopts is 43～48Kev.
4. the method for claim 1 is characterized in that, described described nickel dam is carried out the injection energy range that ion implantation technology adopts is 45Kev.
5. the method for claim 1 is characterized in that, described described nickel dam is carried out the implantation dosage that ion implantation technology adopts is 7 * 10
14～11 * 10
14Cm
-2
6. the method for claim 1 is characterized in that, described described nickel dam is carried out the implantation dosage that ion implantation technology adopts is 9 * 10
14Cm
-2
7. integrated circuit that comprises the semiconductor device that the method for claim 1 makes, described integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array and radio-frequency devices.
8. electronic equipment that comprises the semiconductor device that the method for claim 1 makes, wherein said electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| CN 201010102418 CN102136417B (en) | 2010-01-27 | 2010-01-27 | Method for manufacturing semiconductor device |
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| CN103035497B (en) * | 2011-09-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Nickel silicide formation method and Transistor forming method |
| CN104952799B (en) * | 2015-06-29 | 2017-12-08 | 上海华力微电子有限公司 | A kind of optimization method of nickel silicide |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093805A (en) * | 2006-06-22 | 2007-12-26 | 株式会社东芝 | Method of fabricating semiconductor device and semiconductor device |
| CN101136336A (en) * | 2006-08-31 | 2008-03-05 | 中芯国际集成电路制造(上海)有限公司 | Method for improving silicate nickel layer performance and method for forming PMOS transistor |
| CN101154682A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device and method of manufacturing the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093805A (en) * | 2006-06-22 | 2007-12-26 | 株式会社东芝 | Method of fabricating semiconductor device and semiconductor device |
| CN101136336A (en) * | 2006-08-31 | 2008-03-05 | 中芯国际集成电路制造(上海)有限公司 | Method for improving silicate nickel layer performance and method for forming PMOS transistor |
| CN101154682A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device and method of manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2007-294496A 2007.11.08 |
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