CN102130677B - Ultra-low voltage nand gate circuit - Google Patents
Ultra-low voltage nand gate circuit Download PDFInfo
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- CN102130677B CN102130677B CN201110101066A CN201110101066A CN102130677B CN 102130677 B CN102130677 B CN 102130677B CN 201110101066 A CN201110101066 A CN 201110101066A CN 201110101066 A CN201110101066 A CN 201110101066A CN 102130677 B CN102130677 B CN 102130677B
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Abstract
The invention relates to an ultra-low voltage nand gate circuit, which belongs to the field of design of ultra-low voltage circuits implemented by adopting the CMOS (complementary metal oxide semiconductor) process. A single-end input and single-end output structure is constituted by two ultra-low voltage nand gate basic units; and the output ends of the first and the second ultra-low voltage basic units are connected together as the output end of the single-end input and single-end output structure of the ultra-low voltage nand gate circuit. Or a differential input and differential output structure is constituted by four ultra-low voltage nand gate basic units; the input ends of the second and the third ultra-low voltage nand gate basic units are connected as the two differential input ends of the circuit; the input ends of the first and the fourth ultra-low voltage nand gate basic units are connected as the two differential input ends of the circuit; and the output ends of all the basic units are used as the two differential output ends of the circuit respectively. The body biasing technology of a PMOS (positive-channel metal oxide semiconductor) transistor is adopted, thereby being capable of working under ultra-low voltage, being symmetrical and simple in structure, being easy to design, and being good in symmetry of rising edge and falling edge of output signals.
Description
Technical field
The invention belongs to the ultralow pressure circuit engineering field of adopting CMOS technology to realize, particularly the ultralow pressure NAND gate circuit.
Background technology
Power problems is just becoming an important limiting factor of very lagre scale integrated circuit (VLSIC) system.The market demand of portable set constantly increases at present, and more and more as the electronic product of power supply with battery, for extending battery life, the researcher is more and more urgent to the requirement of low consumption circuit.And use for permanent circuit, maximum operating temperature also requires the power consumption of circuit more and more lower, thereby guarantees the job stability of chip and even system.The angle that realizes from circuit, when supply voltage is reduced to ultralow pressure (below 0.5～0.6V), power consumption will sharply reduce.Some circuit engineering adopts special process at present, and for example low threshold value or zero threshold transistor can realize ultralow pressure, but these technologies sometimes can not the dual-purpose general technologies.Therefore press for the compatible general ultralow pressure circuit engineering of exploitation.
The NAND gate (NAND) that adopts CMOS technology to realize is the common circuit unit.Provided NAND gate circuit (Jin-Han Kim " A 120-MHz 1.8-GHz CMOS DLL-Based Clock Generatorfor Dynamic Frequency Scaling " the IEEE JOURNAL OF SOLID-STATE CIRCUITS of a kind of fan-in (fan-in) symmetry among Fig. 1; VOL.41; NO.9; SEPTEMBER 2006), by six transistor M
1, M
2, M
3, M
4, M
5And M
6Form M
1, M
2And M
3Three range upon range of connections of transistor, M
4, M
5And M
6Three range upon range of connections of transistor.Compare with traditional NAND gate logic, the input side a and b of NAND gate shown in Figure 1 all connects the grids of PMOS pipe and two NMOS pipes, the load effect of previous stage is equal to, and fan-in is symmetrical.But the weak point of this NAND gate is: owing to there are three range upon range of connections of transistor, make it in the ultralow pressure Circuits System, should be used for realizing low-power consumption.
Summary of the invention
The objective of the invention is to propose the ultralow pressure NAND gate circuit for overcoming the weak point of prior art.The present invention adopts the inclined to one side technology of the transistorized body of PMOS to realize the ultralow pressure operating state, and symmetrical configuration is simple, is easy to design.
A kind of ultralow pressure NAND gate circuit that the present invention proposes is characterized in that, adopts the single-ended export structure of single-ended input, is made up of the first ultralow pressure NAND gate elementary cell 1 and the second ultralow pressure NAND gate elementary cell 2; The first input end i of the said first ultralow pressure NAND gate elementary cell 1
1Meet input A, the second input i
2Meet input B, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input A, the 7th input i
7Meet input A, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input B, the 12 input i
12Meet input A;
The first input end i of the said second ultralow pressure NAND gate elementary cell 2
1Meet input B, the second input i
2Meet input A, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input B, the 7th input i
7Meet input B, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input A, the 12 input i
12Meet input B;
The output out of the output out of the first ultralow pressure elementary cell 1 and the second ultralow pressure elementary cell 2 links together as the output QN of the single-ended export structure of single-ended input of ultralow pressure NAND gate circuit.
The another kind of ultralow pressure NAND gate circuit that the present invention proposes; It is characterized in that; Adopt the differential-input differential export structure, form by the first ultralow pressure NAND gate elementary cell 1, the second ultralow pressure NAND gate elementary cell 2, the 3rd ultralow pressure NAND gate elementary cell 3 and the 4th ultralow pressure NAND gate elementary cell 4;
The first input end i of the said first ultralow pressure NAND gate elementary cell 1
1Meet input BN, the second input i
2Meet input A, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet input B, the 6th input i
6Meet input AN, the 7th input i
7Meet input AN, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Earthed voltage VSS, the 12 input i
12Meet input BN, output out is QIP;
The first input end i of the said second ultralow pressure NAND gate elementary cell 2
1Meet input A, the second input i
2Meet supply voltage VDD, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input B, the 7th input i
7Meet input B, the 8th input i
8Meet input AN, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input BN, the 12 input i
12Meet input A, output out is QIN;
The first input end i of said the 3rd ultralow pressure NAND gate elementary cell 3
1Meet input B, the second input i
2Meet input AN, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet input BN, the 6th input i
6Meet input A, the 7th input i
7Meet input A, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Earthed voltage VSS, the 12 input i
12Meet input B, output out is QQP;
The first input end i of said the 4th ultralow pressure NAND gate elementary cell 4
1Meet input AN, the second input i
2Meet supply voltage VDD, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input BN, the 7th input i
7Meet input BN, the 8th input i
8Meet input A, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input B, the 12 input i
12Meet input AN, output out is QQN;
The input A of described second ultralow pressure NAND gate elementary cell and the 3rd ultralow pressure NAND gate elementary cell links to each other respectively as two differential input ends of ultralow pressure NAND gate circuit with B; The input AN of the first ultralow pressure NAND gate elementary cell and the 4th ultralow pressure NAND gate elementary cell links to each other respectively as two differential input ends of ultralow pressure NAND gate circuit with BN; The output QIP of each ultralow pressure NAND gate elementary cell and QIN, output QQP and QQN are respectively as two difference output ends of ultralow pressure NAND gate circuit.
Characteristics of the present invention and effect:
The present invention adopts the transistorized body of PMOS technology partially, manages the ultralow pressure NAND gate elementary cell that constitutes by two PMOS pipes and two NMOS and forms, and symmetrical configuration is simple, is easy to design.
The present invention can work under ultralow pressure.Can realize the output of single-ended input of single-ended input and differential-input differential.
The present invention the rising edge and the trailing edge symmetry of output signal good.
Description of drawings
Fig. 1 is the sketch map of existing NAND gate circuit;
Fig. 2 is the ultralow pressure NAND gate circuit sketch map of the single-ended export structure of the single-ended input of employing that proposes of the present invention;
Fig. 3 is the ultralow pressure NAND gate circuit sketch map of the employing differential-input differential export structure that proposes of the present invention;
Fig. 4 is the structural representation of ultralow pressure NAND gate elementary cell;
Fig. 5 be the ultralow pressure NAND gate circuit that proposes among Fig. 2 at the 0.5V supply voltage, the timing waveform during the 500MHz input signal;
Fig. 6 be the ultralow pressure NAND gate circuit that proposes among Fig. 2 at the 0.6V supply voltage, the timing waveform during the 1GHz input signal;
Fig. 7 be the ultralow pressure NAND gate circuit that proposes among Fig. 3 at the 0.6V supply voltage, the timing waveform during the 1GHz input signal;
Embodiment
Ultralow pressure NAND gate circuit of the present invention combines accompanying drawing and embodiment to specify as follows:
A kind of ultralow pressure NAND gate circuit that the present invention proposes, as shown in Figure 2, it is characterized in that, adopt the single-ended export structure of single-ended input, form by the first ultralow pressure NAND gate elementary cell 1 and the second ultralow pressure NAND gate elementary cell 2; The first input end i of the said first ultralow pressure NAND gate elementary cell 1
1Meet input A, the second input i
2Meet input B, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input A, the 7th input i
7Meet input A, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input B, the 12 input i
12Meet input A;
The first input end i of the said second ultralow pressure NAND gate elementary cell 2
1Meet input B, the second input i
2Meet input A, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input B, the 7th input i
7Meet input B, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input A, the 12 input i
12Meet input B;
The output out of the output out of the first ultralow pressure elementary cell 1 and the second ultralow pressure elementary cell 2 links together as the output QN of the single-ended export structure of single-ended input of ultralow pressure NAND gate circuit.
The another kind of ultralow pressure NAND gate circuit that the present invention proposes; As shown in Figure 3; It is characterized in that; Adopt the differential-input differential export structure, form by the first ultralow pressure NAND gate elementary cell 1, the second ultralow pressure NAND gate elementary cell 2, the 3rd ultralow pressure NAND gate elementary cell 3 and the 4th ultralow pressure NAND gate elementary cell 4;
The first input end i of the said first ultralow pressure NAND gate elementary cell 1
1Meet input BN, the second input i
2Meet input A, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet input B, the 6th input i
6Meet input AN, the 7th input i
7Meet input AN, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Earthed voltage VSS, the 12 input i
12Meet input BN, output out is labeled as QIP;
The first input end i of the said second ultralow pressure NAND gate elementary cell 2
1Meet input A, the second input i
2Meet supply voltage VDD, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input B, the 7th input i
7Meet input B, the 8th input i
8Meet input AN, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input BN, the 12 input i
12Meet input A, output out is labeled as QIN;
The first input end i of said the 3rd ultralow pressure NAND gate elementary cell 3
1Meet input B, the second input i
2Meet input AN, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet input BN, the 6th input i
6Meet input A, the 7th input i
7Meet input A, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Earthed voltage VSS, the 12 input i
12Meet input B, output out is labeled as QQP;
The first input end i of said the 4th ultralow pressure NAND gate elementary cell 4
1Meet input AN, the second input i
2Meet supply voltage VDD, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input BN, the 7th input i
7Meet input BN, the 8th input i
8Meet input A, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input B, the 12 input i
12Meet input AN, output out is labeled as QQN;
The input A of above-mentioned described second ultralow pressure NAND gate elementary cell and the 3rd ultralow pressure NAND gate elementary cell links to each other respectively as two differential input ends of ultralow pressure NAND gate circuit with B; The input AN of the first ultralow pressure NAND gate elementary cell and the 4th ultralow pressure NAND gate elementary cell links to each other respectively as two differential input ends of ultralow pressure NAND gate circuit with BN; The output QIP of each ultralow pressure NAND gate elementary cell and QIN, QQP and QQN are respectively as two difference output ends of ultralow pressure NAND gate circuit.
Above-mentioned all ultralow pressure NAND gate basic cell structures are as shown in Figure 4, all can be by PMOS pipe M
1, the 2nd PMOS manages M
2, the 3rd PMOS manages M
3With the 4th PMOS pipe M
4Form; Wherein, PMOS pipe M
1Grid meet first input end i
1, a PMOS manages M
1Source electrode meet the second input i
2, a PMOS manages M
1Substrate meet the 3rd input i
3The 2nd PMOS manages M
2Grid meet the 6th input i
6, the 2nd PMOS manages M
2Source electrode meet the 5th input i
5, the 2nd PMOS manages M
2Substrate meet four-input terminal i
4The 3rd PMOS manages M
3Grid meet the 7th input i
7, the 3rd PMOS manages M
3Source electrode meet the 8th input i
8, the 3rd PMOS manages M
3Substrate meet the 9th input i
9The 4th PMOS manages M
4Grid meet the 12 input i
12, the 4th PMOS manages M
4Source electrode meet the 11 input i
11, the 4th PMOS manages M
4Substrate meet the tenth input i
10The drain electrode M of the one PMOS pipe
1, the 2nd PMOS pipe drain electrode M
2, the 3rd PMOS manages M
3Drain electrode and the 4th PMOS pipe M
4Drain electrode link to each other, be labeled as out.
Ultralow pressure NAND gate circuit of the present invention; Adopt the transistorized body of PMOS technology partially; The single-ended export structure of its single-ended input is made up of two ultralow pressure elementary cells based on four PMOS pipes and four NMOS pipe; And the differential-input differential export structure is made up of four ultralow pressure elementary cells, and symmetrical configuration is simple, is easy to design.Ultralow pressure NAND gate circuit of the present invention can be worked under ultralow pressure.The rising edge and the trailing edge symmetry of the output signal of ultralow pressure NAND gate circuit of the present invention are good, and have the fan-in symmetry characteristic.
Below introduce the result who ultralow pressure NAND gate circuit of the present invention is carried out simulating, verifying:
Ultralow pressure NAND gate circuit of the present invention shown in Figure 2 adopts CMOS 65nm technology to design, to verify correctness of the present invention.(1) when frequency input signal be 500MHz; The delay inequality of input A and input B institute plus signal is 400ps; The circuit simulation result is as shown in Figure 5, and the vertical coordinate axle of this curve chart and horizontal axis represent with volt (V) to be the voltage and corresponding time (ns) of unit respectively.Input A and input B are high level simultaneously, and output QN is a low level; Input A is a high level, and input B is a low level, and output QN is a high level; Input A is a low level, and input B is a high level, and output QN is a high level; Input A is a low level, and input B is a low level, and output QN is a high level; These meet the NAND gate circuit logical relation.(2) when frequency input signal be 1GHz; The delay inequality of input A and input B institute plus signal is 200ps; The circuit simulation result is as shown in Figure 6, and the vertical coordinate axle of this curve chart and horizontal axis represent with volt (V) to be the voltage and corresponding time (ns) of unit respectively.Input A and input B are high level simultaneously, and output QN is a low level; Input A is a high level, and input B is a low level, and output QN is a high level; Input A is a low level, and input B is a high level, and output QN is a high level; Input A is a low level, and input B is a low level, and output QN is a high level; These meet the NAND gate circuit logical relation.Ultralow pressure NAND gate circuit of the present invention shown in Figure 3 adopts CMOS 65nm technology to design, to verify correctness of the present invention.When frequency input signal is 1GHz; The delay inequality of input A and input B institute plus signal is 200ps; Input AN and BN add the signal with input A and B anti-phase respectively; The circuit simulation result is as shown in Figure 7, and the vertical coordinate axle of this curve chart and horizontal axis represent with volt (V) to be the voltage and corresponding time (ns) of unit respectively.QIP and QIN export with difference form, and QQP and QQN export with difference form.The ultralow pressure NAND gate circuit that above-mentioned simulation result checking the present invention proposes.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. a ultralow pressure NAND gate circuit is characterized in that, adopts the single-ended export structure of single-ended input, is made up of the first ultralow pressure NAND gate elementary cell 1 and the second ultralow pressure NAND gate elementary cell 2; The first input end i of the said first ultralow pressure NAND gate elementary cell 1
1Meet input A, the second input i
2Meet input B, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input A, the 7th input i
7Meet input A, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input B, the 12 input i
12Meet input A;
The first input end i of the said second ultralow pressure NAND gate elementary cell 2
1Meet input B, the second input i
2Meet input A, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input B, the 7th input i
7Meet input B, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input A, the 12 input i
12Meet input B;
The output out of the output out of the said first ultralow pressure NAND gate elementary cell 1 and the said second ultralow pressure NAND gate elementary cell 2 links together as the output QN of the single-ended export structure of single-ended input of ultralow pressure NAND gate circuit;
Said ultralow pressure NAND gate elementary cell is by PMOS pipe M
1, the 2nd PMOS manages M
2, the 3rd PMOS manages M
3With the 4th PMOS pipe M
4Form; Wherein, PMOS pipe M
1Grid meet first input end i
1, a PMOS manages M
1Source electrode meet the second input i
2, a PMOS manages M
1Substrate meet the 3rd input i
3The 2nd PMOS manages M
2Grid meet the 6th input i
6, the 2nd PMOS manages M
2Source electrode meet the 5th input i
5, the 2nd PMOS manages M
2Substrate meet four-input terminal i
4The 3rd PMOS manages M
3Grid meet the 7th input i
7, the 3rd PMOS manages M
3Source electrode meet the 8th input i
8, the 3rd PMOS manages M
3Substrate meet the 9th input i
9The 4th PMOS manages M
4Grid meet the 12 input i
12, the 4th PMOS manages M
4Source electrode meet the 11 input i
11, the 4th PMOS manages M
4Substrate meet the tenth input i
10The drain electrode M of the one PMOS pipe
1, the 2nd PMOS pipe drain electrode M
2, the 3rd PMOS manages M
3Drain electrode and the 4th PMOS pipe M
4Drain electrode link to each other as output out.
2. ultralow pressure NAND gate circuit; It is characterized in that; Adopt the differential-input differential export structure, form by the first ultralow pressure NAND gate elementary cell 1, the second ultralow pressure NAND gate elementary cell 2, the 3rd ultralow pressure NAND gate elementary cell 3 and the 4th ultralow pressure NAND gate elementary cell 4;
The first input end i of the said first ultralow pressure NAND gate elementary cell 1
1Meet input BN, the second input i
2Meet input A, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet input B, the 6th input i
6Meet input AN, the 7th input i
7Meet input AN, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Earthed voltage VSS, the 12 input i
12Meet input BN, output out is QIP;
The first input end i of the said second ultralow pressure NAND gate elementary cell 2
1Meet input A, the second input i
2Meet supply voltage VDD, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input B, the 7th input i
7Meet input B, the 8th input i
8Meet input AN, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input BN, the 12 input i
12Meet input A, output out is QIN;
The first input end i of said the 3rd ultralow pressure NAND gate elementary cell 3
1Meet input B, the second input i
2Meet input AN, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet input BN, the 6th input i
6Meet input A, the 7th input i
7Meet input A, the 8th input i
8Earthed voltage VSS, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Earthed voltage VSS, the 12 input i
12Meet input B, output out is QQP;
The first input end i of said the 4th ultralow pressure NAND gate elementary cell 4
1Meet input AN, the second input i
2Meet supply voltage VDD, the 3rd input i
3Earthed voltage VSS, four-input terminal i
4Earthed voltage VSS, the 5th input i
5Meet supply voltage VDD, the 6th input i
6Meet input BN, the 7th input i
7Meet input BN, the 8th input i
8Meet input A, the 9th input i
9Earthed voltage VSS, the tenth input i
10Earthed voltage VSS, the 11 input i
11Meet input B, the 12 input i
12Meet input AN, output out is QQN;
The input A of described second ultralow pressure NAND gate elementary cell 2 and the 3rd ultralow pressure NAND gate elementary cell 3 links to each other respectively as two differential input ends of ultralow pressure NAND gate circuit with B; The input AN of the first ultralow pressure NAND gate elementary cell 1 and the 4th ultralow pressure NAND gate elementary cell 4 links to each other respectively as two differential input ends of ultralow pressure NAND gate circuit with BN; The output QIP of each ultralow pressure NAND gate elementary cell and QIN, output QQP and QQN are respectively as two difference output ends of ultralow pressure NAND gate circuit; Said ultralow pressure NAND gate elementary cell is by PMOS pipe M
1, the 2nd PMOS manages M
2, the 3rd PMOS manages M
3With the 4th PMOS pipe M
4Form; Wherein, PMOS pipe M
1Grid meet first input end i
1, a PMOS manages M
1Source electrode meet the second input i
2, a PMOS manages M
1Substrate meet the 3rd input i
3The 2nd PMOS manages M
2Grid meet the 6th input i
6, the 2nd PMOS manages M
2Source electrode meet the 5th input i
5, the 2nd PMOS manages M
2Substrate meet four-input terminal i
4The 3rd PMOS manages M
3Grid meet the 7th input i
7, the 3rd PMOS manages M
3Source electrode meet the 8th input i
8, the 3rd PMOS manages M
3Substrate meet the 9th input i
9The 4th PMOS manages M
4Grid meet the 12 input i
12, the 4th PMOS manages M
4Source electrode meet the 11 input i
11, the 4th PMOS manages M
4Substrate meet the tenth input i
10The drain electrode M of the one PMOS pipe
1, the 2nd PMOS pipe drain electrode M
2, the 3rd PMOS manages M
3Drain electrode and the 4th PMOS pipe M
4Drain electrode link to each other as output out.
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|---|---|---|---|
| CN201110101066A CN102130677B (en) | 2011-04-21 | 2011-04-21 | Ultra-low voltage nand gate circuit |
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|---|---|---|---|
| CN201110101066A CN102130677B (en) | 2011-04-21 | 2011-04-21 | Ultra-low voltage nand gate circuit |
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| CN102130677A CN102130677A (en) | 2011-07-20 |
| CN102130677B true CN102130677B (en) | 2012-10-10 |
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| CN201110101066A Expired - Fee Related CN102130677B (en) | 2011-04-21 | 2011-04-21 | Ultra-low voltage nand gate circuit |
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| CN108009112A (en) * | 2017-09-27 | 2018-05-08 | 上海玮舟微电子科技有限公司 | A kind of high-frequency clock IQ phase calibration circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1122534A (en) * | 1994-08-29 | 1996-05-15 | 株式会社日立制作所 | Low distortion switch |
| US7439787B2 (en) * | 2006-07-27 | 2008-10-21 | Freescale Semiconductor, Inc. | Methods and apparatus for a digital pulse width modulator using multiple delay locked loops |
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| JP4015937B2 (en) * | 2002-12-06 | 2007-11-28 | 松下電器産業株式会社 | Duty ratio correction circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1122534A (en) * | 1994-08-29 | 1996-05-15 | 株式会社日立制作所 | Low distortion switch |
| US7439787B2 (en) * | 2006-07-27 | 2008-10-21 | Freescale Semiconductor, Inc. | Methods and apparatus for a digital pulse width modulator using multiple delay locked loops |
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