CN102130155B - Manufacturing method of silicon control rectifier structure - Google Patents
Manufacturing method of silicon control rectifier structure Download PDFInfo
- Publication number
- CN102130155B CN102130155B CN 201010027336 CN201010027336A CN102130155B CN 102130155 B CN102130155 B CN 102130155B CN 201010027336 CN201010027336 CN 201010027336 CN 201010027336 A CN201010027336 A CN 201010027336A CN 102130155 B CN102130155 B CN 102130155B
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- type
- germanium silicon
- doped
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 13
- 239000010703 silicon Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 238000009792 diffusion process Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 22
- 238000000034 method Methods 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 10
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Abstract
The invention discloses a silicon control rectifier structure. A P-type lightly-doped diffusion region is arranged above an N well, germanium silicon doped with an N impurity is arranged above the P-type lightly-doped diffusion region, emitter polycrystalline silicon doped with a P impurity is arranged above the germanium silicon doped with the N impurity, the germanium silicon doped with the N impurity is in short connection with the emitter polycrystalline silicon doped with the P impurity by a metal wire, and the P-type lightly-doped diffusion region is in short connection with an N-type lead-out region of the N well by a metal wire; and heterojunction is formed between the germanium silicon doped with the N impurity and the P-type lightly-doped diffusion region. The silicon control rectifier structure manufactured by the method of manufacturing the silicon control rectifier structure can be used for static protection and can be formed in the conventional germanium silicon process.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacturing approach of thyristor structure.
Background technology
Static is masty problem for the injury of electronic product always.Based on different processes, requirement, our searching/optimization different structure is to reach the requirement of electrostatic protection.
The maximum electrostatic preventing structure of current use uses GGNMOS structure (Ground Gate NMOS) more.Yet in using the radio frequency products of germanium silicon material, much do not have integrated CMOS, consider based on cost, just big limitations the use of electrostatic preventing structure.
(Silicon control Rectifier) is as shown in Figure 1 for thyristor, can one group of PN junction structure be linked to each other as hot end, and another group PN junction structure links to each other as cold end, and to use as electrostatic preventing structure, its equivalent electric circuit is as shown in Figure 2.Common thyristor structure is illustrated in figure 3 as transversary; Be on substrate, to form P trap and N trap; In said P trap, form a P doped region and a N doped region; In said N trap, also form a P doped region and a N doped region, P doped region that forms in the said P trap and N doped region link to each other as cold end as one group of PN junction structure, and P doped region that in said N trap, forms and N doped region link to each other as hot end as one group of PN junction structure.
Summary of the invention
The technical problem that the present invention will solve provides a kind of manufacturing approach of thyristor structure, and the thyristor structure of its manufacturing can be used for electrostatic protection, and can in conventional germanium silicon technology, form.
For solving the problems of the technologies described above, thyristor structure of the present invention forms above silicon substrate, by field isolated area and other device isolation, it is characterized in that on every side,
Comprise N trap, P type light dope diffusion region, doped type N impurity germanium silicon, mix the emitter-polysilicon of p type impurity; It on the N trap P type light dope diffusion region; Be the germanium silicon of doped type N impurity on the P type light dope diffusion region; On the germanium silicon of doped type N impurity for mixing the emitter-polysilicon of p type impurity, the germanium silicon of said doped type N impurity, mix p type impurity emitter-polysilicon through metal wire phase short circuit, said P type light dope diffusion region with the N type draw-out area of N trap through metal wire phase short circuit;
The germanium silicon of said doped type N impurity is with forming heterojunction between the said P type light dope diffusion region.
The manufacturing approach of thyristor structure of the present invention comprises following processing step:
One. on silicon substrate, form the N trap, and through an oxygen with the thyristor structure with other device isolation;
Two. definition and formation P type light dope diffusion region on said N trap upper strata;
Three. on said P type light dope diffusion region, generate dielectric layer, on dielectric layer, generate polysilicon, define the contact-making surface of P type light dope diffusion region and N doped germanium silicon then through the figure that defines this dielectric layer and polysilicon simultaneously;
Four. on said P type light dope diffusion region, generate germanium silicon; And make the N type and mix; On said N doped germanium silicon, generate dielectric layer then; On dielectric layer, generate polysilicon, define the contact-making surface of said N doped germanium silicon and P type doping emitter-polysilicon then through the figure that defines this dielectric layer and polysilicon simultaneously;
Five. on said N doped germanium silicon, generate emitter-polysilicon, define the figure of said emitter-polysilicon then, define the figure of said N doped germanium silicon again, form side wall afterwards;
Six. the N type draw-out area of definition N trap, simultaneously the emitter-polysilicon on the said N doped germanium silicon is carried out the P type and mix, form described P type doping emitter-polysilicon;
Seven. the N type draw-out area and the P type light dope diffusion region via through holes of said N trap are connected through metal wire, said N doped germanium silicon, P type doping emitter-polysilicon via through holes are drawn metal wire and be connected.
Thyristor structure of the present invention; It is a kind of novel vertical silicon control reorganizer structure; This structure can be used for electrostatic protection; And, increase conventional germanium silicon technology flow process on a small quantity, so of the present inventionly many a kind of electrostatic preventing structure lower cost solutions are provided for the germanium silicon product that does not have integrated CMOS based on realizing in the conventional germanium silicon technology.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed description.
Fig. 1 is the thyristor structural representation;
Fig. 2 is that thyristor uses equivalent circuit diagram as electrostatic preventing structure;
Fig. 3 is the thyristor structural representation of common transversary;
Fig. 4 is thyristor structure one an execution mode sketch map of the present invention;
Fig. 5 is the manufacturing approach one execution mode process chart of thyristor structure of the present invention.
Embodiment
Thyristor structure one execution mode of the present invention is as shown in Figure 4, above silicon substrate, forms, on every side by field isolated area 1 and other device isolation; Form by the germanium silicon 2 of N trap 10, P type light dope diffusion region 11, doped type N impurity, emitter-polysilicon 3 vertical stacks of mixing p type impurity; It on N trap 10 P type light dope diffusion region 11; Be the germanium silicon 2 of doped type N impurity on the P type light dope diffusion region 11; For mixing the emitter-polysilicon 3 of p type impurity, the germanium silicon 2 of said doped type N impurity, the emitter-polysilicon 3 of mixing p type impurity are drawn metal wire 5 phase short circuits through through hole 4, are used for connecing hot end on the germanium silicon 2 of doped type N impurity; Said P type light dope diffusion region 11 is drawn metal wire 5 phase short circuits with the N type draw-out area 12 of N trap 10 through through hole 4, is used for connecing cold end.
The germanium silicon 2 of said doped type N impurity is with forming heterojunction between the said P type light dope diffusion region 11.The equivalent electric circuit of said thyristor structure is as shown in Figure 2, can be used as electrostatic preventing structure and uses.
Thyristor structure of the present invention is a kind of novel vertical silicon control reorganizer structure, and this structure can be used for electrostatic protection, and can in conventional germanium silicon technology, realize.The roughly step of conventional germanium silicon technology and the processing step such as the table 1 and shown in Figure 5 of thyristor structure of the present invention; In conventional germanium silicon technology, there is multilayer polysilicon/germanium silicon; Thyristor structure of the present invention have N type or P type to mix respectively, so can realize in conventional germanium silicon technology.Of the present inventionly provide many a kind of electrostatic preventing structures low-cost solutions for the germanium silicon product that do not have integrated CMOS.
The manufacturing approach of thyristor structure of the present invention comprises following processing step:
One. on silicon substrate, form N trap 10, and through an oxygen with the thyristor structure with other device isolation;
Two. definition and formation P type light dope diffusion region 11 on said N trap 10 upper stratas;
Three. on said P type light dope diffusion region 11, generate dielectric layer 16, on dielectric layer 16, generate polysilicon 17, define the contact-making surface of P type light dope diffusion region 11 and N doped germanium silicon 2 then through the figure that defines this dielectric layer and polysilicon simultaneously;
Four. on said P type light dope diffusion region 11, generate germanium silicon 2; And make the N type and mix; And on said germanium silicon 2, generate dielectric layer 6; On dielectric layer 6, generate polysilicon 7, define the contact-making surface of said N doped germanium silicon 2 and P type doping emitter-polysilicon 3 then through the figure that defines this dielectric layer and polysilicon simultaneously;
Five. generate on the said N doped germanium silicon 2 emitter-polysilicon 3 (will after step do the doping of P type); On said emitter-polysilicon 3, define the emitter-polysilicon figure then; On said N doped germanium silicon 2, define the germanium silicon graphics, form side wall 8 afterwards;
Six. the N type draw-out area 12 of definition N trap 10, and emitter-polysilicon 3 is made the P type mix, form described P type doping emitter-polysilicon;
Seven. the N type draw-out area 12 and P type light dope diffusion region 11 via through holes 4 of said N trap 10 are connected through metal wire 5, said N doped germanium silicon, P type doping emitter-polysilicon via through holes 4 are drawn metal wire 5 and be connected.
Claims (1)
1. the manufacturing approach of a thyristor structure is characterized in that, comprises following processing step:
One. on silicon substrate, form the N trap, and through an oxygen with the thyristor structure with other device isolation;
Two. definition and formation P type light dope diffusion region on said N trap upper strata;
Three. on said P type light dope diffusion region, generate dielectric layer, on dielectric layer, generate polysilicon, define the contact-making surface of P type light dope diffusion region and N doped germanium silicon then through the figure that defines this dielectric layer and polysilicon simultaneously;
Four. on said P type light dope diffusion region, generate germanium silicon; And make the N type and mix; On said N doped germanium silicon, generate dielectric layer then; On dielectric layer, generate polysilicon, define the contact-making surface of said N doped germanium silicon and P type doping emitter-polysilicon then through the figure that defines this dielectric layer and polysilicon simultaneously;
Five. on said N doped germanium silicon, generate emitter-polysilicon, define the figure of said emitter-polysilicon then, define the figure of said N doped germanium silicon again, form side wall afterwards;
Six. the N type draw-out area of definition N trap, simultaneously the emitter-polysilicon on the said N doped germanium silicon is carried out the P type and mix, form described P type doping emitter-polysilicon;
Seven. the N type draw-out area and the P type light dope diffusion region via through holes of said N trap are connected through metal wire, said N doped germanium silicon, P type doping emitter-polysilicon via through holes are drawn metal wire and be connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010027336 CN102130155B (en) | 2010-01-20 | 2010-01-20 | Manufacturing method of silicon control rectifier structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010027336 CN102130155B (en) | 2010-01-20 | 2010-01-20 | Manufacturing method of silicon control rectifier structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102130155A CN102130155A (en) | 2011-07-20 |
| CN102130155B true CN102130155B (en) | 2012-11-07 |
Family
ID=44268146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010027336 Active CN102130155B (en) | 2010-01-20 | 2010-01-20 | Manufacturing method of silicon control rectifier structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102130155B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348724B1 (en) * | 1999-09-13 | 2002-02-19 | U.S. Philips Corporation | Semiconductor device with ESD protection |
| CN1482680A (en) * | 2002-09-10 | 2004-03-17 | 萨尔诺夫公司 | Electrostatic discharge protection silicon controlled rectifier (esd-scr) for silicon germanium technologies |
-
2010
- 2010-01-20 CN CN 201010027336 patent/CN102130155B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348724B1 (en) * | 1999-09-13 | 2002-02-19 | U.S. Philips Corporation | Semiconductor device with ESD protection |
| CN1482680A (en) * | 2002-09-10 | 2004-03-17 | 萨尔诺夫公司 | Electrostatic discharge protection silicon controlled rectifier (esd-scr) for silicon germanium technologies |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102130155A (en) | 2011-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106298778A (en) | Semiconductor device and manufacture method thereof and include the electronic equipment of this device | |
| CN103219362B (en) | Esd protection circuit | |
| US9553145B2 (en) | Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness | |
| CN106252352A (en) | Quasiconductor is arranged and manufacture method and include the electronic equipment of this setting | |
| US8946041B2 (en) | Methods for forming high gain tunable bipolar transistors | |
| TWI422039B (en) | Thin film transistor device and manufacturing method thereof | |
| CN105932023A (en) | Transient voltage suppressor | |
| US9590039B2 (en) | Semiconductor structure and method for forming the same | |
| US9190501B2 (en) | Semiconductor devices including a lateral bipolar structure with high current gains | |
| CN108364998A (en) | With by contacting the thyristor with the cathode of diode trigger coupling | |
| CN103208521B (en) | HVMOS device and forming method thereof | |
| EP1646084A1 (en) | A method in the fabrication of an integrated injection logic circuit | |
| CN102130154B (en) | Silicon-controlled rectifier structure and manufacturing method thereof | |
| CN106558622A (en) | A kind of STI diodes for ESD protection | |
| CN108122906A (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN102130155B (en) | Manufacturing method of silicon control rectifier structure | |
| CN106298875A (en) | Semiconductor device and manufacture method thereof and include the electronic equipment of this device | |
| US10002761B2 (en) | Method for forming a multiple layer epitaxial layer on a wafer | |
| CN105932010A (en) | Transient voltage suppressor | |
| US9466598B1 (en) | Semiconductor structure suitable for electrostatic discharge protection application | |
| CN103426828A (en) | Bipolar high-voltage CMOS (complementary metal oxide semiconductor) single-polysilicon filling deep-channel device isolating process based on silicon on insulator material | |
| CN116564996B (en) | Multilayer epitaxial superjunction field effect transistor and preparation method thereof | |
| CN107516658A (en) | A kind of semiconductor devices and its manufacture method and electronic installation | |
| CN105355594B (en) | Integrated circuit structure | |
| CN107482003B (en) | Layout structure of transistor, transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |