CN102129413B - Serial interrupt processing method and device and computer system - Google Patents
Serial interrupt processing method and device and computer system Download PDFInfo
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- CN102129413B CN102129413B CN 201010042845 CN201010042845A CN102129413B CN 102129413 B CN102129413 B CN 102129413B CN 201010042845 CN201010042845 CN 201010042845 CN 201010042845 A CN201010042845 A CN 201010042845A CN 102129413 B CN102129413 B CN 102129413B
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Abstract
The invention is suitable for the computer field, in particular to a serial interrupt processing method and device and a computer system. Two input ends of the serial interrupt processing device are respectively connected with a reference clock generator and a PCI-to-ISA (Peripheral Command Indicator-to-Industry Standard Architecture) bridge; the output end of the serial interrupt processing device is connected with a CPU (Central Processing Unit) and comprises an interrupt mode processing module and/or an enquiry mode processing module, wherein the interrupt mode processing module is used for converting a serial interrupt signal output by the PCI-to-ISA bridge into a parallel interrupt signal in an interrupt mode; the enquiry mode processing module is used for converting a serial interrupt signal output by the PCI-to-ISA bridge into a parallel interrupt signal in an enquiry mode; and the interrupt which the parallel interrupt signal responds to is one of external interrupts permitted by a computer system. The computer system provided by the invention can process serial interrupts output by the PCI-to-ISA bridge without connection with a south bridge and has the advantages of low production cost, compact structure and easiness for miniaturization.
Description
Technical field
The invention belongs to computer realm, relate in particular to method, device and computer system that processing is interrupted in a kind of serial.
Background technology
Industrial standard architectures (Industry Standard Architecture, isa bus) is that IBM Corporation is the bus standard that the PC/AT computing machine is formulated, and is the architecture of 16 buses, also claims the AT standard.1987 IEEE (Institute for Electrical and Electronic Engineers, Institute of Electrical and Electronics Engineers) formally worked out isa bus standard (IEEE-996).
PC/104 is the extension of ISA (IEEE-996) standard, is a kind of Embedded bus specification.PC/104 was adopted as basic document in 1992, was referred to as the compatible PC flush bonding module of IEEE-P996.1 standard.PC/104 is a kind of industrial-controlled general line that defines for embedded Control specially.IEEE-996 is ISA industrial bus standard, IEEE association is IEEE-P996.1 with PC/104 industrial bus normalized definition, therefore PC/104 is exactly in fact a kind of IEEE-996 of compact, except electric and mechanical specification complete different, its signal definition and PC/AT basically identical are embedded control systems a kind of optimization, small-sized, nesting structural embedded control.
But, in PC microcomputer and modem computer systems, compatibility support to early stage ISA equipment progressively weakens, yet in the key areas that industry, control, electric power, traffic, transportation, boats and ships, national defence etc. involve the interests of the state and the people, particularly in embedded computer system and industrial control computer system, still using the I/O equipment based on isa bus and PC/104 bus at present in a large number.
In order to make the support that in above-mentioned field, is widely used of these ISA equipment, embedded computer system often carries out conversion between PCI agreement and the ISA agreement by articulate the PCI-to-ISA bridge chip at PCI master's bridge, realizes that the bus of striding of PCI equipment and ISA equipment intercoms mutually.This PCI-to-ISA bridging chip converts the visit for the I/O of PCI and PCI memory address space to ISA I/O and ISA internal storage access, is used for supporting ISA equipment.
The PCI-to-ISA bridge chip is except being responsible for the pci bus protocol conversion is become the isa bus agreement, also be responsible for receiving various interrupt request (IRQ) signal that sends based on isa bus protocol of I/O equipment, interrupt request (IRQ) signal that these I/O equipment send is to send in parallel mode.Simultaneously, the parallel look-at-me that the PCI-to-ISA bridge chip also will receive converts serial look-at-me (SERIRQ) to, namely transmit all possible interrupt request singal of ISA equipment with a signal wire, and (SERIRQ) signal is interrupted in this serial offers the system module circuit with serial interrupt handling capacity in response, for example South Bridge chip (South Bridge); Steering logic in this system module circuit is behind serial interruption (SERIRQ) signal of receiving from serial look-at-me line, by dissection process they are converted to independently and to be sent to its inner interrupt control logic after the interrupt request singal, and provide the CPU (central processing unit) of a signal to system (CPU) to indicate existing of the interrupt request singal that is untreated in response.CPU (central processing unit) (CPU) responds current look-at-me thereupon and number searches interrupt vector table or interrupt descriptors obtains the entry address of interrupt service routine by interrupt type, in order to carry out suitable interrupt service routine, handles interrupting.
Figure 1 shows that the block diagram of in computer system, realizing the serial of PCI-to-ISA bridging device is interrupted processing that prior art provides.This computer system comprises CPU (central processing unit) (CPU), south bridge (South Bridge), PCI-to-ISA bridge and based on the I/O equipment (Device41, Device42 and Device43) of isa bus and PC/104 bus.
South bridge in this computer system is except providing an enable signal to the PCI-to-ISA bridge that is connected on the pci bus, system power-up also provide an identical enable signal to the ISA equipment (Device41, Device42 and Device43) that is connected on the isa bus, so that can normally be visited PCI-to-ISA bridge and ISA equipment after starting.
South bridge in this computer system (South Bridge) internal logic has supports serial to interrupt the accommodation function module of agreement, and provides serial to interrupt (SERIRQ) input pin.Interrupt agreement according to isa bus and PC/104 bus, the serial of south bridge (South Bridge) is interrupted (SERIRQ) input pin and is received possible interrupt request (IRQ) signal as input from a serial look-at-me line, and these interrupt request (IRQ) signal is interrupted the output of (SERIRQ) output needle and driven serial look-at-me line by the serial of PCI-to-ISA bridge chip.After south bridge (South Bridge) receives a useful signal from serial look-at-me line, the accommodation function module of its internal support serial interruption agreement is resolved the serial look-at-me (SERIRQ) that receives, and suitable interrupt request (IRQ) signal offered CPU (central processing unit) (CPU), this interrupt request (IRQ) signal is consistent with the interrupt request that peripheral hardware ISA equipment responds, and CPU (central processing unit) (CPU) interrupts handling to this untreated interruption immediately.
In the prior art, (SERIRQ) signal is interrupted in the serial of PCI-to-ISA bridge output, need be connected on the south bridge (South Bridge) with dedicated serial interruption processing interface module, but at reduced instruction set computer (Reduced Instruction Set Computer, RISC) there is not South Bridge chip on the ordinary meaning in the embedded computer system that processor architecture (as the MPC8247 of PowerPC series etc.) makes up, and such processor itself does not carry the interface module that processing is interrupted in serial yet, therefore in no dedicated serial is interrupted the embedded computer system of Processing Interface, can't handle serial interruption (SERIRQ) request signal of PCI-to-ISA bridge output, thereby limit the application of ISA equipment in embedded computer system based on isa bus and PC/104 bus protocol.
Though in the embedded computer system that does not have dedicated serial interruption processing interface module, can handle the serial look-at-me that the PCI-to-ISA bridge transmits by connecting south bridge (South Bridge) according to traditional method for designing, but She Ji embedded computer system has only used a function in the abundant input and output I/O bus interface of south bridge (SouthBridge) like this, namely only use the serial interrupt interface module of south bridge (South Bridge), thereby cause the abundant IO interface function of south bridge (South Bridge) to can not get sufficient utilization, cause the waste of south bridge (SouthBridge) resource.
Meanwhile, only interrupting handling this simple function of interface module because of the serial of using south bridge (South Bridge) considers south bridge (South Bridge) is designed into and does not have dedicated serial and interrupt handling in the embedded computer system of interface module and can cause the high shortcoming of production cost; Consider the physical dimension size of south bridge (South Bridge) simultaneously, it is compact inadequately also can to produce layout, is unfavorable for the shortcoming of miniaturization.
In sum, prior art provides passes through to use in computer system the serial of south bridge to interrupt handling interface module to handle that the method for serial look-at-me of PCI-to-ISA bridge transmission is incompatible to be used in PC microcomputer system and modem computer systems.
Summary of the invention
The object of the present invention is to provide a kind of serial to interrupt method, device and the computer system of handling, be intended to solve no dedicated serial and interrupt handling the problem that the computer system of interface module can't be handled the serial look-at-me that the PCI-to-ISA bridge is exported.
The present invention realizes like this, treating apparatus is interrupted in a kind of serial, described device is applied in the computer system, described computer system comprises reference clock generator, PCI-to-ISA bridge and CPU (central processing unit), two input ends that treating apparatus is interrupted in described serial connect with reference clock generator and PCI-to-ISA bridging respectively, the output terminal that treating apparatus is interrupted in described serial is connected with CPU (central processing unit), and described serial is interrupted treating apparatus and comprised:
The interrupt mode processing module is used for converting parallel look-at-me to by the serial look-at-me that interrupt mode is exported the PCI-to-ISA bridge; And/or
The query pattern processing module is used for converting parallel look-at-me to by the serial look-at-me that query pattern is exported the PCI-to-ISA bridge;
The interruption that described parallel look-at-me responds is one of external interrupt of allowing of computer system;
Described interrupt mode processing module comprises:
Whether the start frame detection sub-module is effective for detection of the start frame of the serial look-at-me of PCI-to-ISA bridge output;
First Frame is gathered submodule, is used for gathering the Frame of described serial look-at-me when described start frame is effective;
The first data frame analyzing submodule is used for the Frame that collects is resolved, and converts one of external interrupt that computer system allows to.
Another object of the present invention is to provide a kind of computer system, described system comprises aforesaid serial interruption treating apparatus.
Another object of the present invention is to provide a kind of and adopt aforesaid serial to interrupt the method that treating apparatus is handled the serial look-at-me, described method comprises the steps:
The serial look-at-me that the interrupt mode processing module is exported the PCI-to-ISA bridge by interrupt mode converts parallel look-at-me to; And/or
The serial look-at-me that the query pattern processing module is exported the PCI-to-ISA bridge by query pattern converts parallel look-at-me to;
The interruption that described parallel look-at-me responds is one of external interrupt of allowing of computer system;
Described interrupt mode processing module comprises:
Start frame detection sub-module, first Frame are gathered submodule and the first data frame analyzing submodule;
The step that the serial look-at-me that described interrupt mode processing module is exported the PCI-to-ISA bridge by interrupt mode converts parallel look-at-me to is specially:
Whether the start frame of the serial look-at-me of start frame detection sub-module detection PCI-to-ISA bridge output is effective;
When described start frame was effective, first Frame was gathered submodule and is gathered the Frame of described serial look-at-me;
The first data frame analyzing submodule is resolved the Frame that collects, and converts one of external interrupt that computer system allows to.
In the present invention, serial is interrupted treating apparatus and is converted the serial look-at-me of PCI-to-ISA bridge output to external interrupt signal that computer system allows by query pattern or interrupt mode and export CPU (central processing unit) (CPU) to, CPU (central processing unit) (CPU) is called suitable interrupt service routine this external interrupt is handled, thereby can make the computer system with dedicated serial interruption processing module realize the serial look-at-me of PCI-to-ISA bridge output is handled.
Description of drawings
Fig. 1 is the structural representation of the computer system that provides of prior art;
Fig. 2 is the structural representation of the computer system that provides of the embodiment of the invention;
Fig. 3 is the structural representation that treating apparatus is interrupted in the serial that provides of the embodiment of the invention;
Fig. 4 is that treating apparatus start frame and stop frame transmission time sequence synoptic diagram when adopting interrupt mode is interrupted in the serial that provides of the embodiment of the invention;
Fig. 5 is that treating apparatus start frame and stop frame transmission time sequence synoptic diagram when adopting query pattern is interrupted in the serial that provides of the embodiment of the invention;
Fig. 6 is that data frame transfer sequential synoptic diagram is interrupted in the serial that the embodiment of the invention provides;
Fig. 7 is that the FB(flow block) that treating apparatus is handled the method for serial look-at-me is interrupted in the serial that the embodiment of the invention provides.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
In embodiments of the present invention, PCI-to-ISA bridge output serial in the computer system is interrupted (SERIRQ) signal to serial and is interrupted treating apparatus, serial is interrupted treating apparatus this signal is detected, gather, convert the external interrupt signal that computer system allows after the dissection process to and export CPU (central processing unit) (CPU) to, CPU (central processing unit) (CPU) is called suitable interrupt service routine this external interrupt is handled, thereby can make the computer system with dedicated serial interruption processing module realize the serial look-at-me of PCI-to-ISA bridge output is handled.
The structure of the computer system that Fig. 2 provides for the embodiment of the invention for convenience of explanation, only shows the part relevant with the embodiment of the invention, and many parts inoperative to the present invention or that do not comprise described computer system in the present invention do not indicate.
This computer system comprises: CPU (central processing unit) 10, PCI-to-ISA bridge 30, serial interrupt treating apparatus 31, working standard clock generator 50 and (this peripheral hardware 40 can comprise a plurality of ISA equipment or 104 equipment based on the peripheral hardware 40 of isa bus and PC/104 bus protocol, such as, comprise Device41, Device42 and Device43).Wherein, treating apparatus 31 is interrupted in serial can be any programming device, such as field programmable gate array (Field-Programmable Gate Array, FPGA), CPLD (Complex Programmable Logic Device, CPLD) or single-chip microcomputer.
In embodiments of the present invention, comprise an input pin EN and an output needle Sout based on each the ISA equipment in the peripheral hardware 40 of isa bus and PC/104 bus protocol or 104 equipment.And different Device41, Device42 and Device43 do not identify according to its type, and the external components based on isa bus and PC/104 bus protocol all can be used on the Computer Systems Organization of the present invention arbitrarily.Be understandable that, each ISA equipment in the computer system in the embodiment of the invention or 104 equipment can be configured to different interrupt request singal output (often arranging by the toggle switch on Device41, Device42 and the Device43), a plurality of ISA equipment or 104 equipment of while based on the peripheral hardware 40 of isa bus and PC/104 bus protocol can send an effective look-at-me with identical interrupt request (IRQ) signal, thereby allow a plurality of interruptions to share.This just provides a kind of mode for a plurality of ISA equipment in the computer system or 104 equipment produce any system interrupt signals that may allow.Device41, Device42 and Device43 can provide the input pin Sin of an effective look-at-me to PCI-to-ISA bridge 30 by output needle Sout, and this effective look-at-me is parallel signal.
In embodiments of the present invention, PCI-to-ISA bridge 30 comprises an input pin EN, three input pin Sin and an output needle SERIRQ, input pin Sin receives from ISA equipment or 104 equipment, such as, comprise the interrupt request singal (IRQ) of Device41,42,43 etc. peripheral hardware 40 outputs, be understandable that any possible system interrupt request signal (IRQ) that a plurality of I/O peripheral hardwares of described computer system provide in response is parallel look-at-me.PCI-to-ISA bridge 30 can convert these parallel look-at-mes that is coupled into input pin Sin to serial and interrupt (SERIRQ), simultaneously this serial look-at-me is coupled to drive a useful signal interrupts treating apparatus 31 to serial input pin Sin by output needle SERIRQ.
PCI-to-ISA bridge 30 and serial are interrupted that treating apparatus 31 receives clock signal PCICLK that reference clock generators 50 produce and are the working standard clock with this clock signal.
Referring to figs. 2 and 3, in embodiments of the present invention, serial is interrupted treating apparatus 31 and is comprised an input pin Sin, output needle Sout and internal register 316, and described internal register 316 comprises interrupt status register, interrupt mask register and the clear interrupt register that serial is interrupted the interruption status of register that treating apparatus 31 mode of operations arrange, expression peripheral hardware 40.According to the present invention, in optional embodiment, other suitable register architecture also can be used, and these and other similarly changes and makes up is that the present invention is understandable.Input pin Sin the serial that provides from PCI-to-ISA bridge 30 output needle SERIRQ is provided interrupts (SERIRQ) signal, after 31 pairs of these serials interruptions of serial interruption treating apparatus (SERIRQ) signal detects, gathers, resolves, (SERIRQ) signal is interrupted in this serial convert parallel the interruption to, and pass through the suitable interrupt request singal of its output needle Sout output to the input pin INTR of CPU (central processing unit) (CPU) 10, described suitable look-at-me is one of external interrupt of allowing of computer system of the present invention, for example INTA, INTB, INTC and INTD etc.According to the pci bus standard, what treating apparatus 31 and PCI-to-ISA bridge 30 were interrupted in serial once is called a serial interrupt cycle alternately, and the serial look-at-me of PCI-to-ISA bridge 30 outputs is by start frame, Frame and stop these three frame types of frame and form.In embodiments of the present invention, the clock signal PCICLK that serial interruption (SERIRQ) signal that the input pin Sin of serial interruption treating apparatus 31 receives and working standard clock generator 50 produce is synchronous, serial is interrupted treating apparatus 31 internal logics this serial is interrupted behind (SERIRQ) signal resolution according to effective interrupt request singal the interrupt status register of its internal register 316 being carried out corresponding set sign, and provide suitable external interrupt signal to CPU (central processing unit) (CPU) 10 from output needle Sout in response, in order to this untreated external interrupt signal is interrupted handling.
Wherein the structure of serial interruption treating apparatus 31 comprises: internal register 316, interrupt mode processing module 311 and/or query pattern processing module 312 as shown in Figure 3.Wherein, interrupt mode processing module 311 converts the serial look-at-me of PCI-to-ISA bridge output to parallel look-at-me by interrupt mode; Query pattern processing module 312 converts the serial look-at-me of PCI-to-ISA bridge output to parallel look-at-me by query pattern, and the interruption that this parallel look-at-me responds is one of external interrupt of allowing of computer system.
Wherein, interrupt mode processing module 311 comprises: start frame detection sub-module, first Frame are gathered submodule and the first data frame analyzing submodule.
Whether the start frame of the serial look-at-me of start frame detection sub-module detection PCI-to-ISA bridge 30 outputs is effective.In embodiments of the present invention, when start frame detection sub-module primary detection is effective to serial interruption (SERIRQ) start frame signal of input, be clock period of benchmark time-delay with the PCICLK clock signal, and then whether detect the start frame of serial look-at-me (SERIRQ) of input still effective.Fig. 4 is interrupt mode processing module 311 start frame and stop frame transmission time sequence synoptic diagram when adopting interrupt modes.If detected start frame is invalid again, think that then the serial look-at-me of detected input is that a undesired signal is not desired serial look-at-me (SERIRQ), and restart to detect the input signal that serial interruption treating apparatus 31 input pin Sin receive.If detected start frame is still effective again, then first Frame is gathered the Frame that submodule is gathered the serial look-at-me that input pin Sin that serial interrupts treating apparatus 31 receives, resolve the Frame of the serial look-at-me of its input pin Sin reception again by the first data frame analyzing submodule, thereby obtain the peripheral hardware 40 actual interrupt request singals that produce based on isa bus and PC/104 bus protocol, this interrupt request singal is one of external interrupt signal of allowing of computer system, the output needle Sout that treating apparatus 31 is interrupted in serial then exports this interrupt request singal to CPU (central processing unit) (CPU) 10, CPU (central processing unit) (CPU) 10 these possible external interrupt of response drive layer by peripheral hardware and call corresponding interrupt service routine.Fig. 6 is that data frame transfer sequential synoptic diagram is interrupted in serial, be understandable that the look-at-me that produces based on the peripheral hardware 40 of isa bus and PC/104 bus protocol all can make Frame produce effective look-at-me of correspondence with it in the corresponding PCICLK clock period.
Wherein, query pattern processing module 312 comprises: start frame inquiry submodule, second Frame are gathered submodule and the second data frame analyzing submodule.
If what serial interrupted that treating apparatus 31 adopts is query pattern, PCI-to-ISA bridge 30 is that benchmark sends start frame with the PCICLK clock period so, and Fig. 5 is that treating apparatus 31 start frame and stop frame transmission time sequence figure when adopting query patterns is interrupted in serial.Whether the start frame inquiry submodule inquiry of serial interruption treating apparatus 31 receives the start frame of serial look-at-me, if, then second Frame is gathered the Frame that submodule is gathered the serial look-at-me that input pin Sin that serial interrupts treating apparatus 31 receives, resolve the Frame of the serial look-at-me of its input pin Sin reception again by the second data frame analyzing submodule, referring to Fig. 6, thereby obtain based on the actual interrupt request singals that produce of the peripheral hardware 40 of isa bus and PC/104 bus protocol.
As an alternative embodiment of the invention, serial is interrupted treating apparatus 31 and is also comprised internal register initialization module 313, after computer system powered up startup, a succession of internal register 316 that serial is interrupted treating apparatus 31 and provided can be initialised by internal register initialization module 313.When producing, a plurality of ISA equipment of peripheral hardware 40 or 104 equipment have no progeny in parallel, PCI-to-ISA bridge 30 converts this parallel interruption to serial and interrupts being coupled to drive serial look-at-me line after (SERIRQ), and offers the input pin Sin of serial interruption treating apparatus 31 as input signal.Computer system according to the present invention, serial are interrupted treating apparatus 31 and are selected serial to interrupt the mode of operation for the treatment of apparatus 31 according to the initialization value that the mode of operation of internal register 316 arranges register, namely adopt interrupt mode or query pattern.Be understandable that the modification of described serial being interrupted treating apparatus 31 mode of operations need reconfigure the parameter value that mode of operation arranges register.
As a preferred embodiment of the present invention, serial is interrupted treating apparatus 31 and is also comprised register replacement module 314 and stop interruption processing module 315.After serial interruption treating apparatus 31 parses the peripheral hardware 40 actual interrupt request singals that produce, the interrupt status register of 314 pairs of internal registers 316 of allocating register replacement module carries out the set sign and time-delay is waited for, until all state settings of interrupting in the interrupt status register of internal register 316 are finished.When serial interrupt that treating apparatus 31 receives that serial that PCI-to-ISA bridge 30 sends interrupts stop frame the time, call and stop the processing that interruption processing module 315 finishes serial look-at-me (SERIRQ).Referring to Fig. 4, under interrupt mode, the serial look-at-me stop the useful signal that frame need keep 2 clock period, in order to determine the transmission mode of next frame serial look-at-me (SERIRQ) to remain interrupt mode.Referring to Fig. 5, under query pattern, the serial look-at-me stop the useful signal that frame need keep 3 clock period, in order to determine the transmission mode of next frame serial look-at-me (SERIRQ) to remain query pattern.
In another embodiment of the present invention, the serial of this computer system is interrupted treating apparatus 31 and is also comprised interrupt mask processing module 317.When serial interrupt that treating apparatus 31 receives that serial that PCI-to-ISA bridge 30 sends interrupts stop frame the time, call and stop the processing that interruption processing module 315 finishes serial look-at-me (SERIRQ), to resolve the interrupt request singal that serial interruption (SERIRQ) Frame obtains and send to interrupt mask processing module 317 by stopping interruption processing module 315 simultaneously, interrupt mask processing module 317 compares the interrupt mask register of this interrupt request singal and internal register 316, if the interrupt request singal conductively-closed that obtains of resolving, namely be not enabled, then call internal register initialization module 313 and reinitialize the interrupt mask register of internal register 316 in order to enable this interrupt request singal; If the interrupt request singal that obtains of resolving has enabled, the output needle Sout that treating apparatus 31 is interrupted in serial then exports the external interrupt signal that computer system allows, CPU (central processing unit) (CPU) 10 these possible external interrupt of response, drive layer by peripheral hardware and call corresponding interrupt service routine, after treating that this interruption is processed and finishing, the clear interrupt register that peripheral hardware drives 314 pairs of internal registers 316 of register replacement module of layer triggering serial interruption treating apparatus 31 carries out the set sign, keeps pending look-at-me in order to remove the look-at-me of having handled.Clear interrupt register is write-only register, carries out set by giving this clear interrupt register, makes the corresponding positions of interrupt status register by set again, and it is processed to identify this interruption.Peripheral hardware drives layer interrupt status register according to internal register 316 and judges whether that all interruptions are processed, if also have interruption not processed, then continues processing and interrupts processed finishing until all.
CPU (central processing unit) 10 is the embedded microprocessors according to the design of reduced instruction set computer (RISC) processor architecture, and sort processor framework self does not have the sophisticated interface module of handling the serial look-at-me.CPU (central processing unit) 10 receives from serial interrupts the interrupt request singal (IRQ) that treating apparatus 31 output needle Sout provide, this interrupt request singal (IRQ) can be one of possible external interrupt of allowing of computer system of the present invention, as INTA, INTB, INTC and INTD etc.CPU (central processing unit) 10 is made response to this effective look-at-me (IRQ), calls suitable interrupt service routine this untreated interrupt request singal (IRQ) is interrupted handling.
As a preferred embodiment of the present invention, computer system of the present invention also comprises PCI-to-PCI bridge 21, it is a kind of high-performance pci bus expansion bridge chip that all pci buss in the computer system are coupled together, and connects PCI-to-ISA bridge 30 and CPU (central processing unit) 10.Owing to be subjected to the restriction of electrical specification, in the simple computers system, only there is a pci bus, the PCI equipment number that it connects has constrained.After computer system of the present invention was introduced PCI-to-PCI bridge 21, system can use more PCI equipment.In an embodiment of the present invention, only when PCI-to-PCI bridge 21 is connected in the system, could realize breaking through articulating the restriction of PCI number of devices.
As another preferred embodiment of the present invention, computer system of the present invention also comprises EN logic maker 20, and it comprises an input pin Sin and an output needle Sout.The input pin Sin of EN logic maker 20 receives the control signal from CPU (central processing unit) (CPU) 10, and its output needle Sout is coupled to drive an enable signal to input pin EN and each ISA equipment of system peripheral 40 or the input pin EN of 104 equipment of PCI-to-ISA bridge 30.According to embodiment of the present invention, in case after powering up the described computer system of startup, EN logic maker 20 just continues to provide a useful signal to drive its output needle Sout to each ISA equipment of PCI-to-ISA bridge 30 and peripheral hardware 40 or the input pin EN of 104 equipment, guarantees that described computer system is to the correct visit of PCI-to-ISA bridge 30 and peripheral hardware 40.In some alternative embodiments, also can adopt other EN logic mechanism to finish identical functions.
Fig. 7 is that the method that treating apparatus is handled the serial interruption is interrupted in the serial that the embodiment of the invention provides, and details are as follows:
In step S701, by internal register initialization module initialization internal register.
According to embodiments of the invention, computer system is after powering up startup, by the internal register initialization module, a succession of internal register that serial is interrupted treating apparatus and provided can be initialised, be understandable that described internal register comprises that the mode of operation that the setting for the treatment of apparatus mode of operation is interrupted in serial arranges register, preserves interrupt status register, interrupt mask register and the clear interrupt register of the interruption status of the look-at-me that the peripheral hardware based on isa bus and PC/104 bus protocol sends.According to the present invention, in optional embodiment, other suitable register architecture also can be used, and these and other similarly changes and makes up is that the present invention is understandable.According to computer system of the present invention, serial interruption treating apparatus selects serial to interrupt the mode of operation for the treatment of apparatus according to the initialization value that the mode of operation in the internal register arranges register, namely adopts interrupt mode or query pattern.Be understandable that it also is the parameter value that mode of operation arranges register that the modification that the treating apparatus mode of operation is interrupted in serial need reconfigure the respective inner register.
In step S702, the interrupt mode processing module converts the serial look-at-me of PCI-to-ISA bridge output to parallel look-at-me and/or query pattern processing module by interrupt mode and converts the serial look-at-me of PCI-to-ISA bridge output to parallel look-at-me by query pattern, and the interruption that this parallel look-at-me responds is one of external interrupt of allowing of computer system.
When arranging value representation serial in the register, mode of operation interrupts treating apparatus will adopt interrupt mode to handle the serial interruption time, whether the start frame of the serial look-at-me of start frame detection sub-module detection PCI-to-ISA bridge 30 outputs is effective, when start frame detection sub-module primary detection is effective to serial interruption (SERIRQ) start frame signal of input, be clock period of benchmark time-delay with the PCICLK clock signal, and then whether detect the start frame of input serial look-at-me (SERIRQ) still effective.Fig. 4 is that treating apparatus start frame and stop frame transmission time sequence figure when adopting interrupt mode is interrupted in serial.If invalid, think that then detected input signal is that a undesired signal is not desired serial look-at-me (SERIRQ), and restart to detect the serial look-at-me that serial interruption treating apparatus input pin Sin receives.If it is still effective, then serial first Frame that interrupts treating apparatus is gathered the Frame that submodule is gathered the serial look-at-me that input pin Sin that serial interrupts treating apparatus receives, resolve the Frame of the serial look-at-me of its input pin Sin reception again by the first data frame analyzing submodule, thereby obtain the interrupt request singal based on the actual generation of peripheral hardware of isa bus and PC/104 bus protocol.Fig. 6 is that the data frame transfer sequential chart is interrupted in serial, is understandable that, the look-at-me that produces based on the peripheral hardware of isa bus and PC/104 bus protocol all can make Frame produce effective look-at-me of correspondence with it in the corresponding PCICLK clock period.Register replacement module is carried out set sign and time-delay wait according to the result of data frame analyzing to the interrupt status register in its internal register, until all state settings of interrupting in interrupt status register are finished.Wherein, when detect the serial look-at-me stop frame the time, stop the interruption processing module end to the processing of serial look-at-me (SERIRQ), referring to Fig. 4, stop the useful signal that frame need keep 2 clock period under the interrupt mode, in order to determine the transmission mode of next frame serial look-at-me (SERIRQ) to remain interrupt mode.
If what the treating apparatus employing was interrupted in serial is query pattern, serial interruption treating apparatus is that benchmark receives start frame with the PCICLK clock period so, whether the start frame inquiry submodule inquiry of serial interruption treating apparatus receives the start frame of serial look-at-me, if, then second Frame is gathered the Frame that submodule is gathered the serial look-at-me that input pin Sin that serial interrupts treating apparatus receives, resolve the Frame of the serial look-at-me of its input pin Sin reception again by the second data frame analyzing submodule, thereby obtain the interrupt request singal based on the actual generation of peripheral hardware of isa bus and PC/104 bus protocol, Fig. 5 is that treating apparatus start frame and stop frame transmission time sequence figure when adopting query pattern is interrupted in serial, then the Frame that treating apparatus is resolved the serial look-at-me is interrupted in serial, referring to Fig. 6, register replacement module is carried out set sign and time-delay wait according to the result of data frame analyzing to interrupt status register, until all state settings of interrupting in interrupt status register are finished.Wherein, when detect the serial look-at-me stop frame the time, stop interruption processing module and finish processing to serial look-at-me (SERIRQ).Referring to Fig. 5, stop the useful signal that frame need keep 3 clock period under the query pattern, in order to determine the transmission mode of next frame serial look-at-me (SERIRQ) to remain query pattern.
In addition, as a preferred embodiment of the present invention, when stopping interruption processing module and finish processing to serial look-at-me (SERIRQ), also will resolve serial interrupts the interrupt request singal that (SERIRQ) Frame obtains and sends to an interrupt mask processing module, the interrupt mask processing module with the interrupt mask register in this interrupt request singal and its internal register relatively, if the interrupt request singal conductively-closed that obtains of resolving, namely be not enabled, then need to reinitialize the interrupt mask register of internal register in order to enable this interrupt request singal; If the interrupt request singal that obtains of resolving enabled, the output needle Sout of serial interruption treating apparatus then exports external interrupt signal that computer system allows to CPU (central processing unit).
In embodiments of the present invention, interrupt treating apparatus by the serial in the computer system, convert the serial look-at-me of PCI-to-ISA bridge output to parallel look-at-me and be sent to CPU (central processing unit), CPU (central processing unit) responds the parallel look-at-me that treating apparatus output is interrupted in this serial, call corresponding external interrupt service routine and handle the look-at-me that to walk abreast, thereby the embedded computer system that utilizes reduced instruction set computer (RISC) processor to make up, need not connect south bridge (South Bridge) comes the serial of single processing PCI-to-ISA bridge output to interrupt, make self do not have serial interrupt the embedded computer system of Processing Interface can normal process terminal device (as: ISA equipment, PC104 equipment etc.) serial that passes over is interrupted, have and reduce cost, compact conformation, be easy to miniaturization, the design of simplification system greatly, reduce the characteristics of number of elements, can be widely used in industry, the control field.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. treating apparatus is interrupted in a serial, described device is applied in the computer system, described computer system comprises reference clock generator, PCI-to-ISA bridge and CPU (central processing unit), it is characterized in that, two input ends that treating apparatus is interrupted in described serial connect with reference clock generator and PCI-to-ISA bridging respectively, the output terminal that treating apparatus is interrupted in described serial is connected with CPU (central processing unit), and described serial is interrupted treating apparatus and comprised:
The interrupt mode processing module is used for converting parallel look-at-me to by the serial look-at-me that interrupt mode is exported the PCI-to-ISA bridge; And/or
The query pattern processing module is used for converting parallel look-at-me to by the serial look-at-me that query pattern is exported the PCI-to-ISA bridge;
The interruption that described parallel look-at-me responds is one of external interrupt of allowing of computer system;
Described interrupt mode processing module comprises:
Whether the start frame detection sub-module is effective for detection of the start frame of the serial look-at-me of PCI-to-ISA bridge output;
First Frame is gathered submodule, is used for gathering the Frame of described serial look-at-me when described start frame is effective;
The first data frame analyzing submodule is used for the Frame that collects is resolved, and converts one of external interrupt that computer system allows to.
2. treating apparatus is interrupted in serial as claimed in claim 1, it is characterized in that, described serial is interrupted treating apparatus and also comprised:
Internal register, described internal register comprises at least: mode of operation arranges register, interrupt status register, interrupt mask register and clear interrupt register;
Described mode of operation arranges register, is used for the mode of operation that treating apparatus is interrupted in the storage serial;
The internal register initialization module is used for the described internal register of initialization.
3. treating apparatus is interrupted in serial as claimed in claim 1, it is characterized in that,
Described query pattern processing module comprises:
Start frame inquiry submodule is for the start frame of the serial look-at-me of inquiring about the output of PCI-to-ISA bridge;
Second Frame is gathered submodule, is used for gathering the Frame of described serial look-at-me when inquiring start frame;
The second data frame analyzing submodule is used for the Frame that collects is resolved, and converts one of external interrupt that computer system allows to.
4. treating apparatus is interrupted in serial as claimed in claim 2, it is characterized in that, described serial is interrupted treating apparatus and also comprised register replacement module, stops one or combination in any in interruption processing module and the interrupt mask processing module:
Described register replacement module is used for according to the parallel look-at-me that is converted to the interrupt status register of internal register being carried out the set sign;
Described termination interruption processing module be used for when detect the serial look-at-me stop frame the time, end is to the processing of described serial look-at-me;
Described interrupt mask processing module, interrupt mask register for the parallel look-at-me that will be converted to and internal register compares, if the interrupt mask register that the internal register initialization module reinitializes internal register is then called in the parallel look-at-me conductively-closed that is converted to; Otherwise the parallel look-at-me that output is converted to is to CPU (central processing unit).
5. a computer system comprises PCI-to-ISA bridge and CPU (central processing unit), it is characterized in that, described computer system comprises each described serial interruption treating apparatus of claim 1 to 4, and described computer system also comprises:
The reference clock generator interrupts treating apparatus with described PCI-to-ISA bridge and described serial and is connected respectively, and the reference clock signal that provides described PCI-to-ISA bridge and described serial to interrupt treating apparatus work is provided;
The PCI-to-PCI bridge is connected between PCI-to-ISA bridge and the CPU (central processing unit) by pci bus, is used for expanding the PCI slot in the computer system; And/or
EN logic maker, be used for receiving the control signal from CPU (central processing unit), continue to provide a useful signal to the PCI-to-ISA bridge with based on the peripheral hardware of isa bus and PC/104 bus protocol, guarantee that computer system is to described PCI-to-ISA bridge with based on the correct visit of the peripheral hardware of isa bus and PC/104 bus protocol.
6. one kind is adopted serial as claimed in claim 1 to interrupt the method that treating apparatus is handled the serial look-at-me, it is characterized in that described method comprises the steps:
The serial look-at-me that the interrupt mode processing module is exported the PCI-to-ISA bridge by interrupt mode converts parallel look-at-me to; And/or
The serial look-at-me that the query pattern processing module is exported the PCI-to-ISA bridge by query pattern converts parallel look-at-me to;
The interruption that described parallel look-at-me responds is one of external interrupt of allowing of computer system;
Described interrupt mode processing module comprises:
Start frame detection sub-module, first Frame are gathered submodule and the first data frame analyzing submodule;
The step that the serial look-at-me that described interrupt mode processing module is exported the PCI-to-ISA bridge by interrupt mode converts parallel look-at-me to is specially:
Whether the start frame of the serial look-at-me of start frame detection sub-module detection PCI-to-ISA bridge output is effective;
When described start frame was effective, first Frame was gathered submodule and is gathered the Frame of described serial look-at-me;
The first data frame analyzing submodule is resolved the Frame that collects, and converts one of external interrupt that computer system allows to.
7. method as claimed in claim 6 is characterized in that, described serial is interrupted treating apparatus and also comprised:
The internal register initialization module; With
Internal register, described internal register comprises at least: mode of operation arranges register, interrupt status register, interrupt mask register and clear interrupt register;
Described mode of operation arranges register, is used for the mode of operation that treating apparatus is interrupted in the storage serial;
By interrupt mode the serial look-at-me of PCI-to-ISA bridge output is converted to before parallel look-at-me and/or query pattern processing module convert the serial look-at-me of PCI-to-ISA bridge output the step of parallel look-at-me to by query pattern in described interrupt mode processing module, described method also comprises the steps:
The internal register of internal register initialization module initialization serial interruptions reason device.
8. method as claimed in claim 6 is characterized in that, described query pattern processing module comprises:
Start frame inquiry submodule, second Frame are gathered submodule and the second data frame analyzing submodule;
The step that the serial look-at-me that described query pattern processing module is exported the PCI-to-ISA bridge by query pattern converts parallel look-at-me to is specially:
The start frame of the serial look-at-me of start frame inquiry submodule inquiry PCI-to-ISA bridge output;
When inquiring start frame, second Frame is gathered submodule and is gathered the Frame of described serial look-at-me;
The second data frame analyzing submodule is resolved the Frame that collects, and converts one of external interrupt that computer system allows to.
9. method as claimed in claim 6 is characterized in that, described interrupt mode processing module comprises:
Start frame detection sub-module, first Frame are gathered submodule and the first data frame analyzing submodule;
Described query pattern processing module comprises:
Start frame inquiry submodule, second Frame are gathered submodule and the second data frame analyzing submodule;
By interrupt mode the serial look-at-me of PCI-to-ISA bridge output is converted after parallel look-at-me and/or query pattern processing module convert the serial look-at-me of PCI-to-ISA bridge output the step of parallel look-at-me to by query pattern to one or combination in any during described method also comprises the steps in described interrupt mode processing module:
Register replacement module is carried out the set sign according to the parallel look-at-me that is converted to the interrupt status register in the internal register;
When detect the serial look-at-me stop frame the time, stop interruption processing module and finish processing to described serial look-at-me;
The parallel look-at-me that the interrupt mask processing module will be converted to and the interrupt mask register in the internal register are relatively, if the interrupt mask register that the internal register initialization module reinitializes internal register is then called in the parallel look-at-me conductively-closed that is converted to; Otherwise the parallel look-at-me that output is converted to is to CPU (central processing unit).
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| CN1157046A (en) * | 1994-12-07 | 1997-08-13 | 英特尔公司 | Serial interrupt bus protocol |
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| CN1157046A (en) * | 1994-12-07 | 1997-08-13 | 英特尔公司 | Serial interrupt bus protocol |
| CN1637732A (en) * | 2003-08-09 | 2005-07-13 | 得州仪器公司 | System for signaling serialized interrupts using message signaled interrupts |
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